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/openbmc/u-boot/doc/
H A DREADME.socfpga46 $ qsys-generate soc_system.qsys --upgrade-ip-cores
47 $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL]
73 Using the Qsys GUI
79 4. Run QSys [Tools->QSys]
80 4.1 In the Open dialog, select '<project_name>.qsys'
82 4.3 In the Qsys window, click on 'Generate HDL...' in bottom right corner
85 4.4 In the QSys window, click 'Finish'
H A DREADME.nios225 The device tree source must be generated from your qsys/sopc design
/openbmc/u-boot/doc/SPI/
H A DREADME.altera_spi2 - Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
3 - The controller base address is the "Base" in QSys + 0x400
/openbmc/u-boot/drivers/net/mscc_eswitch/
H A Docelot_switch.c99 QSYS, enumerator
227 writel(0, priv->regs[QSYS] + QSYS_QMAP); in ocelot_cpu_capture_setup()
260 setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT), in ocelot_cpu_capture_setup()
267 setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT)); in ocelot_cpu_capture_setup()
305 setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port - PORT0), in ocelot_port_init()
455 { QSYS, "qsys" }, in ocelot_probe()
/openbmc/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h1271 /* QSYS:SYSTEM:PORT_MODE */
1280 /* QSYS:SYSTEM:SWITCH_PORT_MODE */
1313 /* QSYS:SYSTEM:SW_STATUS */
1322 /* QSYS:SYSTEM:CPU_GROUP_MAP */
1325 /* QSYS:RES_CTRL:RES_CFG */
1328 /* QSYS:HSCH:CIR_CFG */
1343 /* QSYS:HSCH:SE_CFG */
1378 /* QSYS:TAS_CONFIG:TAS_CFG_CTRL */
1405 /* QSYS:TAS_CONFIG:TAS_GATE_STATE_CTRL */
1414 /* QSYS:TAS_CONFIG:TAS_STATEMACHINE_CFG */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmscc,vsc7514-switch.yaml108 - const: qsys
165 "port7", "port8", "port9", "port10", "qsys",
212 "port7", "port8", "port9", "port10", "qsys",
/openbmc/linux/arch/nios2/platform/
H A DKconfig.platform106 by Altera and which can be enabled in QSYS builder. This accelerates
113 Number of the instruction as configured in QSYS Builder.
/openbmc/linux/drivers/net/dsa/ocelot/
H A Docelot_ext.c48 [QSYS] = "qsys",
H A Dseville_vsc9953.c451 [QSYS] = vsc9953_qsys_regmap,
481 DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"),
494 [QSYS] = "qsys",
H A Dfelix_vsc9959.c510 [QSYS] = vsc9959_qsys_regmap,
537 DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"),
550 [QSYS] = "qsys",
/openbmc/u-boot/include/configs/
H A Dsocfpga_common.h73 * The base address is configurable in QSys, each board must specify the
76 * selected in QSys, since the SPI registers are at offset +0x400.
/openbmc/u-boot/doc/device-tree-bindings/cpu/
H A Dnios2.txt7 Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
/openbmc/linux/Documentation/devicetree/bindings/nios2/
H A Dnios2.txt7 Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
/openbmc/linux/drivers/net/ethernet/mscc/
H A Docelot_vsc7514.c251 { QSYS, "qsys" }, in mscc_ocelot_probe()
H A Dvsc7514_regs.c427 [QSYS] = vsc7514_qsys_regmap,
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_calendar.c13 /* QSYS calendar information */
159 /* Auto configure the QSYS calendar based on port configuration */
241 dev_err(sparx5->dev, "QSYS calendar error\n"); in sparx5_config_auto_calendar()
/openbmc/u-boot/include/
H A Dvsc9953.h402 /* VSC9953 QSYS structure */
462 /* END VSC9953 QSYS structure */
/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_gen5.c493 * Use ROWBITS from Quartus/QSys to calculate SDRAM size in sdram_calculate_size()
515 * Use CSBITs from Quartus/QSys to calculate SDRAM size in sdram_calculate_size()
/openbmc/linux/drivers/mfd/
H A Docelot-core.c143 DEFINE_RES_REG_NAMED(VSC7512_QSYS_RES_START, VSC7512_QSYS_RES_SIZE, "qsys"),
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,ocelot.dtsi140 "port10", "qsys", "ana";
/openbmc/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi143 "port7", "port8", "port9", "port10", "qsys",
/openbmc/linux/include/soc/mscc/
H A Docelot.h113 QSYS, enumerator
239 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria10_socdk_sdmmc_handoff.dtsi7 * handoffs from both Qsys and Quartus.
/openbmc/linux/drivers/net/ethernet/microchip/vcap/
H A Dvcap_ag_api.h520 * QSYS port number when FWD_MODE is redirect or copy
522 * QSYS queue number when FWD_MODE is redirect or copy
/openbmc/u-boot/drivers/serial/
H A DKconfig468 between a host PC and a Qsys system on an Altera FPGA. Please find

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