195acd4c7SLey Foon Tan* Nios II Processor Binding 295acd4c7SLey Foon Tan 395acd4c7SLey Foon TanThis binding specifies what properties available in the device tree 495acd4c7SLey Foon Tanrepresentation of a Nios II Processor Core. 595acd4c7SLey Foon Tan 695acd4c7SLey Foon TanUsers can use sopc2dts tool for generating device tree sources (dts) from a 795acd4c7SLey Foon TanQsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts 895acd4c7SLey Foon Tan 995acd4c7SLey Foon TanRequired properties: 1095acd4c7SLey Foon Tan 1195acd4c7SLey Foon Tan- compatible: Compatible property value should be "altr,nios2-1.0". 1295acd4c7SLey Foon Tan- reg: Contains CPU index. 1395acd4c7SLey Foon Tan- interrupt-controller: Specifies that the node is an interrupt controller 1495acd4c7SLey Foon Tan- #interrupt-cells: Specifies the number of cells needed to encode an 1595acd4c7SLey Foon Tan interrupt source, should be 1. 1695acd4c7SLey Foon Tan- clock-frequency: Contains the clock frequency for CPU, in Hz. 1795acd4c7SLey Foon Tan- dcache-line-size: Contains data cache line size. 1895acd4c7SLey Foon Tan- icache-line-size: Contains instruction line size. 1995acd4c7SLey Foon Tan- dcache-size: Contains data cache size. 2095acd4c7SLey Foon Tan- icache-size: Contains instruction cache size. 2195acd4c7SLey Foon Tan- altr,pid-num-bits: Specifies the number of bits to use to represent the process 2295acd4c7SLey Foon Tan identifier (PID). 2395acd4c7SLey Foon Tan- altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB. 2495acd4c7SLey Foon Tan- altr,tlb-num-entries: Specifies the number of entries in the TLB. 2595acd4c7SLey Foon Tan- altr,tlb-ptr-sz: Specifies size of TLB pointer. 26*47aab533SBjorn Helgaas- altr,has-mul: Specifies CPU hardware multiply support, should be 1. 2795acd4c7SLey Foon Tan- altr,has-mmu: Specifies CPU support MMU support, should be 1. 2895acd4c7SLey Foon Tan- altr,has-initda: Specifies CPU support initda instruction, should be 1. 2995acd4c7SLey Foon Tan- altr,reset-addr: Specifies CPU reset address 3095acd4c7SLey Foon Tan- altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address 3195acd4c7SLey Foon Tan- altr,exception-addr: Specifies CPU exception address 3295acd4c7SLey Foon Tan 3395acd4c7SLey Foon TanOptional properties: 3495acd4c7SLey Foon Tan- altr,has-div: Specifies CPU hardware divide support 3595acd4c7SLey Foon Tan- altr,implementation: Nios II core implementation, this should be "fast"; 3695acd4c7SLey Foon Tan 3795acd4c7SLey Foon TanExample: 3895acd4c7SLey Foon Tan 394c9847b7SMathieu Malaterrecpu@0 { 4095acd4c7SLey Foon Tan device_type = "cpu"; 4195acd4c7SLey Foon Tan compatible = "altr,nios2-1.0"; 4295acd4c7SLey Foon Tan reg = <0>; 4395acd4c7SLey Foon Tan interrupt-controller; 4495acd4c7SLey Foon Tan #interrupt-cells = <1>; 4595acd4c7SLey Foon Tan clock-frequency = <125000000>; 4695acd4c7SLey Foon Tan dcache-line-size = <32>; 4795acd4c7SLey Foon Tan icache-line-size = <32>; 4895acd4c7SLey Foon Tan dcache-size = <32768>; 4995acd4c7SLey Foon Tan icache-size = <32768>; 5095acd4c7SLey Foon Tan altr,implementation = "fast"; 5195acd4c7SLey Foon Tan altr,pid-num-bits = <8>; 5295acd4c7SLey Foon Tan altr,tlb-num-ways = <16>; 5395acd4c7SLey Foon Tan altr,tlb-num-entries = <128>; 5495acd4c7SLey Foon Tan altr,tlb-ptr-sz = <7>; 5595acd4c7SLey Foon Tan altr,has-div = <1>; 5695acd4c7SLey Foon Tan altr,has-mul = <1>; 5795acd4c7SLey Foon Tan altr,reset-addr = <0xc2800000>; 5895acd4c7SLey Foon Tan altr,fast-tlb-miss-addr = <0xc7fff400>; 5995acd4c7SLey Foon Tan altr,exception-addr = <0xd0000020>; 6095acd4c7SLey Foon Tan altr,has-initda = <1>; 6195acd4c7SLey Foon Tan altr,has-mmu = <1>; 6295acd4c7SLey Foon Tan}; 63