156051948SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT)
256051948SVladimir Oltean /* Copyright 2017 Microsemi Corporation
33c9cfb52SVladimir Oltean * Copyright 2018-2019 NXP
456051948SVladimir Oltean */
5bdeced75SVladimir Oltean #include <linux/fsl/enetc_mdio.h>
6de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_qsys.h>
707d985eeSVladimir Oltean #include <soc/mscc/ocelot_vcap.h>
87d4b564dSXiaoliang Yang #include <soc/mscc/ocelot_ana.h>
96505b680SVladimir Oltean #include <soc/mscc/ocelot_dev.h>
10de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_ptp.h>
1156051948SVladimir Oltean #include <soc/mscc/ocelot_sys.h>
1223ae3a78SXiaoliang Yang #include <net/tc_act/tc_gate.h>
1356051948SVladimir Oltean #include <soc/mscc/ocelot.h>
1440d3f295SVladimir Oltean #include <linux/dsa/ocelot.h>
15588d0550SIoana Ciornei #include <linux/pcs-lynx.h>
16de143c0eSXiaoliang Yang #include <net/pkt_sched.h>
1756051948SVladimir Oltean #include <linux/iopoll.h>
1816659b81SMichael Walle #include <linux/mdio.h>
1956051948SVladimir Oltean #include <linux/of.h>
20837ced3aSVladimir Oltean #include <linux/pci.h>
2156051948SVladimir Oltean #include <linux/time.h>
2256051948SVladimir Oltean #include "felix.h"
23acf242fcSColin Foster
24acf242fcSColin Foster #define VSC9959_NUM_PORTS 6
25de143c0eSXiaoliang Yang
2611afdc65SVladimir Oltean #define VSC9959_TAS_GCL_ENTRY_MAX 63
2777043c37SXiaoliang Yang #define VSC9959_TAS_MIN_GATE_LEN_NS 33
2877043c37SXiaoliang Yang #define VSC9959_VCAP_POLICER_BASE 63
29c9910484SColin Foster #define VSC9959_VCAP_POLICER_MAX 383
30c9910484SColin Foster #define VSC9959_SWITCH_PCI_BAR 4
31de143c0eSXiaoliang Yang #define VSC9959_IMDIO_PCI_BAR 0
32acf242fcSColin Foster
33acf242fcSColin Foster #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \
3411ecf341SVladimir Oltean OCELOT_PORT_MODE_QSGMII | \
35acf242fcSColin Foster OCELOT_PORT_MODE_1000BASEX | \
36acf242fcSColin Foster OCELOT_PORT_MODE_2500BASEX | \
37acf242fcSColin Foster OCELOT_PORT_MODE_USXGMII)
38acf242fcSColin Foster
39acf242fcSColin Foster static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = {
40acf242fcSColin Foster VSC9959_PORT_MODE_SERDES,
41acf242fcSColin Foster VSC9959_PORT_MODE_SERDES,
42acf242fcSColin Foster VSC9959_PORT_MODE_SERDES,
43acf242fcSColin Foster VSC9959_PORT_MODE_SERDES,
44a53cbe5dSVladimir Oltean OCELOT_PORT_MODE_INTERNAL,
45acf242fcSColin Foster OCELOT_PORT_MODE_INTERNAL,
46acf242fcSColin Foster };
4756051948SVladimir Oltean
4856051948SVladimir Oltean static const u32 vsc9959_ana_regmap[] = {
4956051948SVladimir Oltean REG(ANA_ADVLEARN, 0x0089a0),
5056051948SVladimir Oltean REG(ANA_VLANMASK, 0x0089a4),
5156051948SVladimir Oltean REG_RESERVED(ANA_PORT_B_DOMAIN),
5256051948SVladimir Oltean REG(ANA_ANAGEFIL, 0x0089ac),
5356051948SVladimir Oltean REG(ANA_ANEVENTS, 0x0089b0),
5456051948SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x0089b4),
5556051948SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x0089b8),
5656051948SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x0089c8),
5756051948SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x0089cc),
5856051948SVladimir Oltean REG(ANA_AUTOAGE, 0x0089d0),
5956051948SVladimir Oltean REG(ANA_MACTOPTIONS, 0x0089d4),
6056051948SVladimir Oltean REG(ANA_LEARNDISC, 0x0089d8),
6156051948SVladimir Oltean REG(ANA_AGENCTRL, 0x0089dc),
6256051948SVladimir Oltean REG(ANA_MIRRORPORTS, 0x0089e0),
6356051948SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x0089e4),
6456051948SVladimir Oltean REG(ANA_FLOODING, 0x0089e8),
6556051948SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x008a08),
6656051948SVladimir Oltean REG(ANA_SFLOW_CFG, 0x008a0c),
6756051948SVladimir Oltean REG(ANA_PORT_MODE, 0x008a28),
6856051948SVladimir Oltean REG(ANA_CUT_THRU_CFG, 0x008a48),
6956051948SVladimir Oltean REG(ANA_PGID_PGID, 0x008400),
7056051948SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x007f1c),
7156051948SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x007f20),
7256051948SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x007f24),
7356051948SVladimir Oltean REG(ANA_TABLES_STREAMDATA, 0x007f28),
7456051948SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x007f2c),
7556051948SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x007f30),
7656051948SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x007f34),
7756051948SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x007f38),
7856051948SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x007f3c),
7956051948SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x007f40),
8056051948SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x007f00),
8156051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44),
8256051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x007f48),
8356051948SVladimir Oltean REG(ANA_TABLES_STREAMACCESS, 0x007f4c),
8456051948SVladimir Oltean REG(ANA_TABLES_STREAMTIDX, 0x007f50),
8556051948SVladimir Oltean REG(ANA_TABLES_SEQ_HISTORY, 0x007f54),
8656051948SVladimir Oltean REG(ANA_TABLES_SEQ_MASK, 0x007f58),
8756051948SVladimir Oltean REG(ANA_TABLES_SFID_MASK, 0x007f5c),
8856051948SVladimir Oltean REG(ANA_TABLES_SFIDACCESS, 0x007f60),
8956051948SVladimir Oltean REG(ANA_TABLES_SFIDTIDX, 0x007f64),
9056051948SVladimir Oltean REG(ANA_MSTI_STATE, 0x008600),
9156051948SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x008000),
9256051948SVladimir Oltean REG(ANA_SG_ACCESS_CTRL, 0x008a64),
9356051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_1, 0x007fb0),
9456051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_2, 0x007fb4),
9556051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_3, 0x007fb8),
9656051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_4, 0x007fbc),
9756051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_5, 0x007fc0),
9856051948SVladimir Oltean REG(ANA_SG_GCL_GS_CONFIG, 0x007f80),
9956051948SVladimir Oltean REG(ANA_SG_GCL_TI_CONFIG, 0x007f90),
10056051948SVladimir Oltean REG(ANA_SG_STATUS_REG_1, 0x008980),
10156051948SVladimir Oltean REG(ANA_SG_STATUS_REG_2, 0x008984),
10256051948SVladimir Oltean REG(ANA_SG_STATUS_REG_3, 0x008988),
10356051948SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007800),
10456051948SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007804),
10556051948SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007808),
10656051948SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00780c),
10756051948SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810),
10856051948SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00781c),
10956051948SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007820),
11056051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007860),
11156051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864),
11256051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868),
11356051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c),
11456051948SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007870),
11556051948SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007874),
11656051948SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007878),
11756051948SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c),
11856051948SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007880),
11956051948SVladimir Oltean REG(ANA_PORT_SFID_CFG, 0x007884),
12056051948SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800),
12156051948SVladimir Oltean REG_RESERVED(ANA_PFC_PFC_TIMER),
12256051948SVladimir Oltean REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
12356051948SVladimir Oltean REG_RESERVED(ANA_IPT_IPT),
12456051948SVladimir Oltean REG_RESERVED(ANA_PPT_PPT),
12556051948SVladimir Oltean REG_RESERVED(ANA_FID_MAP_FID_MAP),
12656051948SVladimir Oltean REG(ANA_AGGR_CFG, 0x008a68),
12756051948SVladimir Oltean REG(ANA_CPUQ_CFG, 0x008a6c),
12856051948SVladimir Oltean REG_RESERVED(ANA_CPUQ_CFG2),
12956051948SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x008a74),
13056051948SVladimir Oltean REG(ANA_DSCP_CFG, 0x008ab4),
13156051948SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x008bb4),
13256051948SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4),
13356051948SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14),
13456051948SVladimir Oltean REG_RESERVED(ANA_VRAP_CFG),
13556051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_DATA),
13656051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_MASK),
13756051948SVladimir Oltean REG(ANA_DISCARD_CFG, 0x008c40),
13856051948SVladimir Oltean REG(ANA_FID_CFG, 0x008c44),
13956051948SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000),
14056051948SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004),
14156051948SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008),
14256051948SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c),
14356051948SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010),
14456051948SVladimir Oltean REG_RESERVED(ANA_POL_STATE),
14556051948SVladimir Oltean REG(ANA_POL_FLOWC, 0x008c48),
14656051948SVladimir Oltean REG(ANA_POL_HYST, 0x008cb4),
14756051948SVladimir Oltean REG_RESERVED(ANA_POL_MISC_CFG),
14856051948SVladimir Oltean };
14956051948SVladimir Oltean
15056051948SVladimir Oltean static const u32 vsc9959_qs_regmap[] = {
15156051948SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000),
15256051948SVladimir Oltean REG(QS_XTR_RD, 0x000008),
15356051948SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010),
15456051948SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018),
15556051948SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c),
15656051948SVladimir Oltean REG(QS_XTR_CFG, 0x000020),
15756051948SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024),
15856051948SVladimir Oltean REG(QS_INJ_WR, 0x00002c),
15956051948SVladimir Oltean REG(QS_INJ_CTRL, 0x000034),
16056051948SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c),
16156051948SVladimir Oltean REG(QS_INJ_ERR, 0x000040),
16256051948SVladimir Oltean REG_RESERVED(QS_INH_DBG),
16356051948SVladimir Oltean };
164c1c3993eSVladimir Oltean
165c1c3993eSVladimir Oltean static const u32 vsc9959_vcap_regmap[] = {
166c1c3993eSVladimir Oltean /* VCAP_CORE_CFG */
167c1c3993eSVladimir Oltean REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
168c1c3993eSVladimir Oltean REG(VCAP_CORE_MV_CFG, 0x000004),
169c1c3993eSVladimir Oltean /* VCAP_CORE_CACHE */
170c1c3993eSVladimir Oltean REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
171c1c3993eSVladimir Oltean REG(VCAP_CACHE_MASK_DAT, 0x000108),
172c1c3993eSVladimir Oltean REG(VCAP_CACHE_ACTION_DAT, 0x000208),
173c1c3993eSVladimir Oltean REG(VCAP_CACHE_CNT_DAT, 0x000308),
17420968054SVladimir Oltean REG(VCAP_CACHE_TG_DAT, 0x000388),
17520968054SVladimir Oltean /* VCAP_CONST */
17620968054SVladimir Oltean REG(VCAP_CONST_VCAP_VER, 0x000398),
17720968054SVladimir Oltean REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
17820968054SVladimir Oltean REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
17920968054SVladimir Oltean REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
18020968054SVladimir Oltean REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
18120968054SVladimir Oltean REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
18220968054SVladimir Oltean REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
18320968054SVladimir Oltean REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
18420968054SVladimir Oltean REG(VCAP_CONST_CORE_CNT, 0x0003b8),
18556051948SVladimir Oltean REG(VCAP_CONST_IF_CNT, 0x0003bc),
18656051948SVladimir Oltean };
18756051948SVladimir Oltean
18856051948SVladimir Oltean static const u32 vsc9959_qsys_regmap[] = {
18956051948SVladimir Oltean REG(QSYS_PORT_MODE, 0x00f460),
19056051948SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x00f480),
19156051948SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x00f49c),
19256051948SVladimir Oltean REG(QSYS_EEE_CFG, 0x00f4a0),
19356051948SVladimir Oltean REG(QSYS_EEE_THRES, 0x00f4b8),
19456051948SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x00f4bc),
19556051948SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x00f4c0),
19656051948SVladimir Oltean REG(QSYS_SW_STATUS, 0x00f4c4),
19756051948SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x00f4e0),
19856051948SVladimir Oltean REG_RESERVED(QSYS_PAD_CFG),
19956051948SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x00f4e8),
20056051948SVladimir Oltean REG_RESERVED(QSYS_QMAP),
20156051948SVladimir Oltean REG_RESERVED(QSYS_ISDX_SGRP),
20256051948SVladimir Oltean REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
20356051948SVladimir Oltean REG(QSYS_TFRM_MISC, 0x00f50c),
20456051948SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x00f510),
20556051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514),
20656051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518),
20756051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c),
20856051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520),
20956051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524),
21056051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528),
21156051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c),
21256051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530),
21356051948SVladimir Oltean REG(QSYS_RED_PROFILE, 0x00f534),
21456051948SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x00f574),
21556051948SVladimir Oltean REG(QSYS_RES_CFG, 0x00c000),
21656051948SVladimir Oltean REG(QSYS_RES_STAT, 0x00c004),
21756051948SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x00f578),
21856051948SVladimir Oltean REG(QSYS_EQ_CTRL, 0x00f57c),
21956051948SVladimir Oltean REG_RESERVED(QSYS_EVENTS_CORE),
22056051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_0, 0x00f584),
22156051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0),
22256051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc),
22356051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8),
22456051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4),
22556051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_5, 0x00f610),
22656051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_6, 0x00f62c),
22756051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_7, 0x00f648),
2280fbabf87SXiaoliang Yang REG(QSYS_PREEMPTION_CFG, 0x00f664),
22956051948SVladimir Oltean REG(QSYS_CIR_CFG, 0x000000),
23056051948SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004),
23156051948SVladimir Oltean REG(QSYS_SE_CFG, 0x000008),
23256051948SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c),
23356051948SVladimir Oltean REG_RESERVED(QSYS_SE_CONNECT),
23456051948SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040),
23556051948SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044),
23656051948SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048),
23756051948SVladimir Oltean REG_RESERVED(QSYS_SE_STATE),
23856051948SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x00f67c),
23956051948SVladimir Oltean REG(QSYS_TAG_CONFIG, 0x00f680),
24056051948SVladimir Oltean REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698),
24156051948SVladimir Oltean REG(QSYS_PORT_MAX_SDU, 0x00f69c),
24256051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_1, 0x00f440),
24356051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_2, 0x00f444),
24456051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_3, 0x00f448),
24556051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_4, 0x00f44c),
24656051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_5, 0x00f450),
24756051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_1, 0x00f454),
24856051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_2, 0x00f458),
24956051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_1, 0x00f400),
25056051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_2, 0x00f404),
25156051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_3, 0x00f408),
25256051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c),
25356051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_5, 0x00f410),
25456051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_6, 0x00f414),
25556051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_7, 0x00f418),
25656051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c),
25756051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_9, 0x00f420),
25856051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_1, 0x00f424),
25956051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_2, 0x00f428),
26056051948SVladimir Oltean };
26156051948SVladimir Oltean
26256051948SVladimir Oltean static const u32 vsc9959_rew_regmap[] = {
26356051948SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000),
26456051948SVladimir Oltean REG(REW_TAG_CFG, 0x000004),
26556051948SVladimir Oltean REG(REW_PORT_CFG, 0x000008),
26656051948SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c),
26756051948SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
26856051948SVladimir Oltean REG(REW_PTP_CFG, 0x000050),
26956051948SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054),
27056051948SVladimir Oltean REG(REW_RED_TAG_CFG, 0x000058),
27156051948SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000410),
27256051948SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000510),
27356051948SVladimir Oltean REG_RESERVED(REW_STAT_CFG),
27456051948SVladimir Oltean REG_RESERVED(REW_REW_STICKY),
27556051948SVladimir Oltean REG_RESERVED(REW_PPT),
27656051948SVladimir Oltean };
27756051948SVladimir Oltean
27856051948SVladimir Oltean static const u32 vsc9959_sys_regmap[] = {
279d4c36765SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000),
28056051948SVladimir Oltean REG(SYS_COUNT_RX_UNICAST, 0x000004),
281d4c36765SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008),
28256051948SVladimir Oltean REG(SYS_COUNT_RX_BROADCAST, 0x00000c),
28356051948SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010),
28456051948SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
285d4c36765SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018),
286d4c36765SVladimir Oltean REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c),
28756051948SVladimir Oltean REG(SYS_COUNT_RX_SYM_ERRS, 0x000020),
28856051948SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024),
28956051948SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028),
2905152de7bSVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c),
2915152de7bSVladimir Oltean REG(SYS_COUNT_RX_256_511, 0x000030),
2925152de7bSVladimir Oltean REG(SYS_COUNT_RX_512_1023, 0x000034),
2935152de7bSVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000038),
2945152de7bSVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x00003c),
2955152de7bSVladimir Oltean REG(SYS_COUNT_RX_PAUSE, 0x000040),
2965152de7bSVladimir Oltean REG(SYS_COUNT_RX_CONTROL, 0x000044),
297d4c36765SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000048),
298d4c36765SVladimir Oltean REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c),
299d4c36765SVladimir Oltean REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050),
300d4c36765SVladimir Oltean REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054),
301d4c36765SVladimir Oltean REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058),
302d4c36765SVladimir Oltean REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c),
303d4c36765SVladimir Oltean REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060),
304d4c36765SVladimir Oltean REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064),
305d4c36765SVladimir Oltean REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068),
306d4c36765SVladimir Oltean REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c),
307d4c36765SVladimir Oltean REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070),
308d4c36765SVladimir Oltean REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074),
309d4c36765SVladimir Oltean REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078),
310d4c36765SVladimir Oltean REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c),
311d4c36765SVladimir Oltean REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080),
312d4c36765SVladimir Oltean REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084),
313d4c36765SVladimir Oltean REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088),
314d4c36765SVladimir Oltean REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c),
315d4c36765SVladimir Oltean REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090),
316d4c36765SVladimir Oltean REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094),
317d4c36765SVladimir Oltean REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098),
318d4c36765SVladimir Oltean REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c),
319d4c36765SVladimir Oltean REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0),
320d4c36765SVladimir Oltean REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4),
321d4c36765SVladimir Oltean REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8),
322ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac),
323ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_ASSEMBLY_ERRS, 0x0000b0),
324ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_SMD_ERRS, 0x0000b4),
325ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_ASSEMBLY_OK, 0x0000b8),
326ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_MERGE_FRAGMENTS, 0x0000bc),
327ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_OCTETS, 0x0000c0),
328ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_UNICAST, 0x0000c4),
329ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_MULTICAST, 0x0000c8),
330ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_BROADCAST, 0x0000cc),
331ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_SHORTS, 0x0000d0),
332ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_FRAGMENTS, 0x0000d4),
333ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_JABBERS, 0x0000d8),
334ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS, 0x0000dc),
335ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_SYM_ERRS, 0x0000e0),
336ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_64, 0x0000e4),
337ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_65_127, 0x0000e8),
338ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_128_255, 0x0000ec),
339ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_256_511, 0x0000f0),
340ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_512_1023, 0x0000f4),
341ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_1024_1526, 0x0000f8),
342ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_1527_MAX, 0x0000fc),
343ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_PAUSE, 0x000100),
344ab3f97a9SVladimir Oltean REG(SYS_COUNT_RX_PMAC_CONTROL, 0x000104),
34556051948SVladimir Oltean REG(SYS_COUNT_RX_PMAC_LONGS, 0x000108),
346d4c36765SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000200),
347d4c36765SVladimir Oltean REG(SYS_COUNT_TX_UNICAST, 0x000204),
348d4c36765SVladimir Oltean REG(SYS_COUNT_TX_MULTICAST, 0x000208),
34956051948SVladimir Oltean REG(SYS_COUNT_TX_BROADCAST, 0x00020c),
35056051948SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000210),
351d4c36765SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000214),
35256051948SVladimir Oltean REG(SYS_COUNT_TX_PAUSE, 0x000218),
35356051948SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00021c),
3545152de7bSVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000220),
3555152de7bSVladimir Oltean REG(SYS_COUNT_TX_128_255, 0x000224),
3565152de7bSVladimir Oltean REG(SYS_COUNT_TX_256_511, 0x000228),
3575152de7bSVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x00022c),
3585152de7bSVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x000230),
359d4c36765SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000234),
360d4c36765SVladimir Oltean REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238),
361d4c36765SVladimir Oltean REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c),
362d4c36765SVladimir Oltean REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240),
363d4c36765SVladimir Oltean REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244),
364d4c36765SVladimir Oltean REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248),
365d4c36765SVladimir Oltean REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c),
366d4c36765SVladimir Oltean REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250),
367d4c36765SVladimir Oltean REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254),
368d4c36765SVladimir Oltean REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258),
369d4c36765SVladimir Oltean REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c),
370d4c36765SVladimir Oltean REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260),
371d4c36765SVladimir Oltean REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264),
372d4c36765SVladimir Oltean REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268),
373d4c36765SVladimir Oltean REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c),
374d4c36765SVladimir Oltean REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270),
375be5c13f2SVladimir Oltean REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274),
376ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_AGED, 0x000278),
377ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_MM_HOLD, 0x00027c),
378ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_MERGE_FRAGMENTS, 0x000280),
379ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_OCTETS, 0x000284),
380ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_UNICAST, 0x000288),
381ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_MULTICAST, 0x00028c),
382ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_BROADCAST, 0x000290),
383ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_PAUSE, 0x000294),
384ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_64, 0x000298),
385ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_65_127, 0x00029c),
386ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_128_255, 0x0002a0),
387ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_256_511, 0x0002a4),
388ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_512_1023, 0x0002a8),
389ab3f97a9SVladimir Oltean REG(SYS_COUNT_TX_PMAC_1024_1526, 0x0002ac),
390d4c36765SVladimir Oltean REG(SYS_COUNT_TX_PMAC_1527_MAX, 0x0002b0),
391d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_LOCAL, 0x000400),
392d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_TAIL, 0x000404),
393d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408),
394d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c),
395d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410),
396d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414),
397d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418),
398d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c),
399d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420),
400d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424),
401d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428),
402d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c),
403d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430),
404d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434),
405d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438),
406d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c),
407d4c36765SVladimir Oltean REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440),
4080a2360c5SVladimir Oltean REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444),
4090a2360c5SVladimir Oltean REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800),
4100a2360c5SVladimir Oltean REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804),
4110a2360c5SVladimir Oltean REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808),
41256051948SVladimir Oltean REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c),
41356051948SVladimir Oltean REG(SYS_RESET_CFG, 0x000e00),
41456051948SVladimir Oltean REG(SYS_SR_ETYPE_CFG, 0x000e04),
41556051948SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000e08),
41656051948SVladimir Oltean REG(SYS_PORT_MODE, 0x000e0c),
41756051948SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000e2c),
41856051948SVladimir Oltean REG(SYS_FRM_AGING, 0x000e44),
41956051948SVladimir Oltean REG(SYS_STAT_CFG, 0x000e48),
42056051948SVladimir Oltean REG(SYS_SW_STATUS, 0x000e4c),
42156051948SVladimir Oltean REG_RESERVED(SYS_MISC_CFG),
42256051948SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c),
42356051948SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x000e84),
42456051948SVladimir Oltean REG(SYS_TIMESTAMP_OFFSET, 0x000e9c),
42556051948SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000ea0),
42656051948SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000ebc),
42756051948SVladimir Oltean REG(SYS_ATOP, 0x000ec0),
42856051948SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x000edc),
42956051948SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000ee0),
43056051948SVladimir Oltean REG(SYS_MMGT, 0x000ef8),
43156051948SVladimir Oltean REG_RESERVED(SYS_MMGT_FAST),
43256051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_DIF),
43356051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_CORE),
43456051948SVladimir Oltean REG(SYS_PTP_STATUS, 0x000f14),
43556051948SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x000f18),
43656051948SVladimir Oltean REG(SYS_PTP_NXT, 0x000f1c),
43756051948SVladimir Oltean REG(SYS_PTP_CFG, 0x000f20),
43856051948SVladimir Oltean REG(SYS_RAM_INIT, 0x000f24),
43956051948SVladimir Oltean REG_RESERVED(SYS_CM_ADDR),
44056051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_WR),
44156051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_RD),
44256051948SVladimir Oltean REG_RESERVED(SYS_CM_OP),
44356051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA),
44456051948SVladimir Oltean };
4455df66c48SYangbo Lu
4465df66c48SYangbo Lu static const u32 vsc9959_ptp_regmap[] = {
4475df66c48SYangbo Lu REG(PTP_PIN_CFG, 0x000000),
4485df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
4495df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
45094aca082SYangbo Lu REG(PTP_PIN_TOD_NSEC, 0x00000c),
45194aca082SYangbo Lu REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
4525df66c48SYangbo Lu REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
4535df66c48SYangbo Lu REG(PTP_CFG_MISC, 0x0000a0),
4545df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
4555df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
4565df66c48SYangbo Lu };
45756051948SVladimir Oltean
45856051948SVladimir Oltean static const u32 vsc9959_gcb_regmap[] = {
45956051948SVladimir Oltean REG(GCB_SOFT_RST, 0x000004),
46056051948SVladimir Oltean };
46191c724cfSVladimir Oltean
46291c724cfSVladimir Oltean static const u32 vsc9959_dev_gmii_regmap[] = {
46391c724cfSVladimir Oltean REG(DEV_CLOCK_CFG, 0x0),
46491c724cfSVladimir Oltean REG(DEV_PORT_MISC, 0x4),
46591c724cfSVladimir Oltean REG(DEV_EVENTS, 0x8),
46691c724cfSVladimir Oltean REG(DEV_EEE_CFG, 0xc),
46791c724cfSVladimir Oltean REG(DEV_RX_PATH_DELAY, 0x10),
46891c724cfSVladimir Oltean REG(DEV_TX_PATH_DELAY, 0x14),
46991c724cfSVladimir Oltean REG(DEV_PTP_PREDICT_CFG, 0x18),
47091c724cfSVladimir Oltean REG(DEV_MAC_ENA_CFG, 0x1c),
47191c724cfSVladimir Oltean REG(DEV_MAC_MODE_CFG, 0x20),
47291c724cfSVladimir Oltean REG(DEV_MAC_MAXLEN_CFG, 0x24),
47391c724cfSVladimir Oltean REG(DEV_MAC_TAGS_CFG, 0x28),
47491c724cfSVladimir Oltean REG(DEV_MAC_ADV_CHK_CFG, 0x2c),
47591c724cfSVladimir Oltean REG(DEV_MAC_IFG_CFG, 0x30),
47691c724cfSVladimir Oltean REG(DEV_MAC_HDX_CFG, 0x34),
47791c724cfSVladimir Oltean REG(DEV_MAC_DBG_CFG, 0x38),
47891c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c),
47991c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40),
4806505b680SVladimir Oltean REG(DEV_MAC_STICKY, 0x44),
4816505b680SVladimir Oltean REG(DEV_MM_ENABLE_CONFIG, 0x48),
4826505b680SVladimir Oltean REG(DEV_MM_VERIF_CONFIG, 0x4C),
48391c724cfSVladimir Oltean REG(DEV_MM_STATUS, 0x50),
48491c724cfSVladimir Oltean REG_RESERVED(PCS1G_CFG),
48591c724cfSVladimir Oltean REG_RESERVED(PCS1G_MODE_CFG),
48691c724cfSVladimir Oltean REG_RESERVED(PCS1G_SD_CFG),
48791c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_CFG),
48891c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_CFG),
48991c724cfSVladimir Oltean REG_RESERVED(PCS1G_LB_CFG),
49091c724cfSVladimir Oltean REG_RESERVED(PCS1G_DBG_CFG),
49191c724cfSVladimir Oltean REG_RESERVED(PCS1G_CDET_CFG),
49291c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_STATUS),
49391c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_STATUS),
49491c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_STATUS),
49591c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_DOWN_CNT),
49691c724cfSVladimir Oltean REG_RESERVED(PCS1G_STICKY),
49791c724cfSVladimir Oltean REG_RESERVED(PCS1G_DEBUG_STATUS),
49891c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_CFG),
49991c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
50091c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_STATUS),
50191c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
50291c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_STATUS),
50391c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_CFG),
50491c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_STATUS),
50591c724cfSVladimir Oltean };
50691c724cfSVladimir Oltean
50756051948SVladimir Oltean static const u32 *vsc9959_regmap[TARGET_MAX] = {
50856051948SVladimir Oltean [ANA] = vsc9959_ana_regmap,
50956051948SVladimir Oltean [QS] = vsc9959_qs_regmap,
51056051948SVladimir Oltean [QSYS] = vsc9959_qsys_regmap,
51156051948SVladimir Oltean [REW] = vsc9959_rew_regmap,
512e3aea296SVladimir Oltean [SYS] = vsc9959_sys_regmap,
513a61e365dSVladimir Oltean [S0] = vsc9959_vcap_regmap,
514c1c3993eSVladimir Oltean [S1] = vsc9959_vcap_regmap,
5155df66c48SYangbo Lu [S2] = vsc9959_vcap_regmap,
51656051948SVladimir Oltean [PTP] = vsc9959_ptp_regmap,
51791c724cfSVladimir Oltean [GCB] = vsc9959_gcb_regmap,
51856051948SVladimir Oltean [DEV_GMII] = vsc9959_dev_gmii_regmap,
51956051948SVladimir Oltean };
520b4024c9eSClaudiu Manoil
5211109b97bSVladimir Oltean /* Addresses are relative to the PCI device's base address */
5221109b97bSVladimir Oltean static const struct resource vsc9959_resources[] = {
5231109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"),
5241109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"),
5251109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"),
5261109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"),
5271109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"),
5281109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"),
5291109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"),
530044d447aSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"),
531044d447aSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"),
532044d447aSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"),
533044d447aSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"),
534044d447aSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"),
535044d447aSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"),
5361109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"),
5371109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"),
5381109b97bSVladimir Oltean DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"),
5391109b97bSVladimir Oltean };
5401109b97bSVladimir Oltean
5411109b97bSVladimir Oltean static const char * const vsc9959_resource_names[TARGET_MAX] = {
5421109b97bSVladimir Oltean [SYS] = "sys",
5431109b97bSVladimir Oltean [REW] = "rew",
5441109b97bSVladimir Oltean [S0] = "s0",
5451109b97bSVladimir Oltean [S1] = "s1",
5461109b97bSVladimir Oltean [S2] = "s2",
5471109b97bSVladimir Oltean [GCB] = "devcpu_gcb",
5481109b97bSVladimir Oltean [QS] = "qs",
5491109b97bSVladimir Oltean [PTP] = "ptp",
5501109b97bSVladimir Oltean [QSYS] = "qsys",
55156051948SVladimir Oltean [ANA] = "ana",
55256051948SVladimir Oltean };
553bdeced75SVladimir Oltean
554bdeced75SVladimir Oltean /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
555bdeced75SVladimir Oltean * SGMII/QSGMII MAC PCS can be found.
556044d447aSVladimir Oltean */
557940af261SVladimir Oltean static const struct resource vsc9959_imdio_res =
558bdeced75SVladimir Oltean DEFINE_RES_MEM_NAMED(0x8030, 0x10, "imdio");
5592789658fSMaxim Kochetkov
56056051948SVladimir Oltean static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
56156051948SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
56256051948SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
56356051948SVladimir Oltean [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
56456051948SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
56556051948SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
56656051948SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
56756051948SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
56856051948SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
56956051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
57056051948SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
57156051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
57256051948SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
57356051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
57456051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
57556051948SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
57656051948SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
57756051948SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
57856051948SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
57956051948SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
58056051948SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
58156051948SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
58256051948SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
58356051948SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
58456051948SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
58556051948SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
58656051948SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
58756051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
58856051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
58956051948SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
59056051948SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
59156051948SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
59256051948SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
593886e1387SVladimir Oltean [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
594886e1387SVladimir Oltean /* Replicated per number of ports (7), register size 4 per port */
595886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
596886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
597886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
598886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
599886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
600886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
601886e1387SVladimir Oltean [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
602886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
603886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
604541132f0SMaxim Kochetkov [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
605541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
606541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
60756051948SVladimir Oltean [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
60856051948SVladimir Oltean };
609e3aea296SVladimir Oltean
610e3aea296SVladimir Oltean static const struct vcap_field vsc9959_vcap_es0_keys[] = {
611e3aea296SVladimir Oltean [VCAP_ES0_EGR_PORT] = { 0, 3},
612e3aea296SVladimir Oltean [VCAP_ES0_IGR_PORT] = { 3, 3},
613e3aea296SVladimir Oltean [VCAP_ES0_RSV] = { 6, 2},
614e3aea296SVladimir Oltean [VCAP_ES0_L2_MC] = { 8, 1},
615e3aea296SVladimir Oltean [VCAP_ES0_L2_BC] = { 9, 1},
616e3aea296SVladimir Oltean [VCAP_ES0_VID] = { 10, 12},
617e3aea296SVladimir Oltean [VCAP_ES0_DP] = { 22, 1},
618e3aea296SVladimir Oltean [VCAP_ES0_PCP] = { 23, 3},
619e3aea296SVladimir Oltean };
620e3aea296SVladimir Oltean
621e3aea296SVladimir Oltean static const struct vcap_field vsc9959_vcap_es0_actions[] = {
622e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2},
623e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1},
624e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2},
625e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1},
626e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2},
627e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2},
628e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2},
629e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1},
630e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2},
631e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2},
632e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12},
633e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3},
634e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1},
635e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12},
636e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3},
637e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1},
638e3aea296SVladimir Oltean [VCAP_ES0_ACT_RSV] = { 49, 23},
639e3aea296SVladimir Oltean [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1},
640e3aea296SVladimir Oltean };
641a61e365dSVladimir Oltean
642a61e365dSVladimir Oltean static const struct vcap_field vsc9959_vcap_is1_keys[] = {
643a61e365dSVladimir Oltean [VCAP_IS1_HK_TYPE] = { 0, 1},
644a61e365dSVladimir Oltean [VCAP_IS1_HK_LOOKUP] = { 1, 2},
645a61e365dSVladimir Oltean [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7},
646a61e365dSVladimir Oltean [VCAP_IS1_HK_RSV] = { 10, 9},
647a61e365dSVladimir Oltean [VCAP_IS1_HK_OAM_Y1731] = { 19, 1},
648a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_MC] = { 20, 1},
649a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_BC] = { 21, 1},
650a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_MC] = { 22, 1},
651a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1},
652a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1},
653a61e365dSVladimir Oltean [VCAP_IS1_HK_TPID] = { 25, 1},
654a61e365dSVladimir Oltean [VCAP_IS1_HK_VID] = { 26, 12},
655a61e365dSVladimir Oltean [VCAP_IS1_HK_DEI] = { 38, 1},
656a61e365dSVladimir Oltean [VCAP_IS1_HK_PCP] = { 39, 3},
657a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_NORMAL */
658a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_SMAC] = { 42, 48},
659a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1},
660a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE] = { 91, 16},
661a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_SNAP] = {107, 1},
662a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4] = {108, 1},
663a61e365dSVladimir Oltean /* Layer-3 Information */
664a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1},
665a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1},
666a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_OPTIONS] = {111, 1},
667a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_DSCP] = {112, 6},
668a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32},
669a61e365dSVladimir Oltean /* Layer-4 Information */
670a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP_UDP] = {150, 1},
671a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP] = {151, 1},
672a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_SPORT] = {152, 16},
673a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_RNG] = {168, 8},
674a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
675a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1},
676a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12},
677a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1},
678a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3},
679a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP4] = { 59, 1},
680a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1},
681a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1},
682a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1},
683a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6},
684a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32},
685a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32},
686a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8},
687a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1},
688a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP] = {142, 1},
689a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8},
690a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32},
691a61e365dSVladimir Oltean };
692a61e365dSVladimir Oltean
693a61e365dSVladimir Oltean static const struct vcap_field vsc9959_vcap_is1_actions[] = {
694a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1},
695a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6},
696a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_ENA] = { 7, 1},
697a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_VAL] = { 8, 3},
698a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_ENA] = { 11, 1},
699a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_VAL] = { 12, 1},
700a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8},
701a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_VAL] = { 21, 8},
70275944fdaSXiaoliang Yang [VCAP_IS1_ACT_RSV] = { 29, 9},
703a61e365dSVladimir Oltean /* The fields below are incorrectly shifted by 2 in the manual */
704a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1},
705a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12},
706a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_SEL] = { 51, 2},
707a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_VAL] = { 53, 13},
708a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1},
709a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_VAL] = { 67, 3},
710a61e365dSVladimir Oltean [VCAP_IS1_ACT_DEI_VAL] = { 70, 1},
711a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1},
712a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2},
713a61e365dSVladimir Oltean [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4},
714a61e365dSVladimir Oltean [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1},
715a61e365dSVladimir Oltean };
7163ab4ceb6SVladimir Oltean
71707d985eeSVladimir Oltean static struct vcap_field vsc9959_vcap_is2_keys[] = {
71807d985eeSVladimir Oltean /* Common: 41 bits */
71907d985eeSVladimir Oltean [VCAP_IS2_TYPE] = { 0, 4},
72007d985eeSVladimir Oltean [VCAP_IS2_HK_FIRST] = { 4, 1},
72107d985eeSVladimir Oltean [VCAP_IS2_HK_PAG] = { 5, 8},
72207d985eeSVladimir Oltean [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7},
72307d985eeSVladimir Oltean [VCAP_IS2_HK_RSV2] = { 20, 1},
72407d985eeSVladimir Oltean [VCAP_IS2_HK_HOST_MATCH] = { 21, 1},
72507d985eeSVladimir Oltean [VCAP_IS2_HK_L2_MC] = { 22, 1},
72607d985eeSVladimir Oltean [VCAP_IS2_HK_L2_BC] = { 23, 1},
72707d985eeSVladimir Oltean [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1},
72807d985eeSVladimir Oltean [VCAP_IS2_HK_VID] = { 25, 12},
72907d985eeSVladimir Oltean [VCAP_IS2_HK_DEI] = { 37, 1},
73007d985eeSVladimir Oltean [VCAP_IS2_HK_PCP] = { 38, 3},
73107d985eeSVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
73207d985eeSVladimir Oltean [VCAP_IS2_HK_L2_DMAC] = { 41, 48},
73307d985eeSVladimir Oltean [VCAP_IS2_HK_L2_SMAC] = { 89, 48},
73407d985eeSVladimir Oltean /* MAC_ETYPE (TYPE=000) */
73507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16},
73607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16},
73707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8},
73807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3},
73907d985eeSVladimir Oltean /* MAC_LLC (TYPE=001) */
74007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40},
74107d985eeSVladimir Oltean /* MAC_SNAP (TYPE=010) */
74207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40},
74307d985eeSVladimir Oltean /* MAC_ARP (TYPE=011) */
74407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48},
74507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1},
74607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1},
74707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1},
74807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1},
74907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1},
75007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1},
75107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2},
75207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32},
75307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32},
75407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1},
75507d985eeSVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */
75607d985eeSVladimir Oltean [VCAP_IS2_HK_IP4] = { 41, 1},
75707d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1},
75807d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1},
75907d985eeSVladimir Oltean [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1},
76007d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1},
76107d985eeSVladimir Oltean [VCAP_IS2_HK_L3_TOS] = { 46, 8},
76207d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32},
76307d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32},
76407d985eeSVladimir Oltean [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1},
76507d985eeSVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */
7668b9e03cdSXiaoliang Yang [VCAP_IS2_HK_TCP] = {119, 1},
7678b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_DPORT] = {120, 16},
76807d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT] = {136, 16},
76907d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RNG] = {152, 8},
77007d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1},
7718b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1},
7728b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_FIN] = {162, 1},
7738b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_SYN] = {163, 1},
7748b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_RST] = {164, 1},
7758b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_PSH] = {165, 1},
7768b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_ACK] = {166, 1},
77707d985eeSVladimir Oltean [VCAP_IS2_HK_L4_URG] = {167, 1},
77807d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_DOM] = {168, 8},
77907d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_VER] = {176, 4},
78007d985eeSVladimir Oltean /* IP4_OTHER (TYPE=101) */
78107d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8},
78207d985eeSVladimir Oltean [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56},
78307d985eeSVladimir Oltean /* IP6_STD (TYPE=110) */
78407d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1},
78507d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128},
78607d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8},
78707d985eeSVladimir Oltean /* OAM (TYPE=111) */
78807d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7},
78907d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_VER] = {144, 5},
79007d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_OPCODE] = {149, 8},
79107d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_FLAGS] = {157, 8},
79207d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEPID] = {165, 16},
79307d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1},
79407d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1},
79507d985eeSVladimir Oltean };
7963ab4ceb6SVladimir Oltean
79707d985eeSVladimir Oltean static struct vcap_field vsc9959_vcap_is2_actions[] = {
79807d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1},
79907d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1},
80007d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3},
80107d985eeSVladimir Oltean [VCAP_IS2_ACT_MASK_MODE] = { 5, 2},
80207d985eeSVladimir Oltean [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1},
80307d985eeSVladimir Oltean [VCAP_IS2_ACT_LRN_DIS] = { 8, 1},
80407d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1},
80507d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9},
806460e985eSVladimir Oltean [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1},
807460e985eSVladimir Oltean [VCAP_IS2_ACT_PORT_MASK] = { 20, 6},
808460e985eSVladimir Oltean [VCAP_IS2_ACT_REW_OP] = { 26, 9},
809460e985eSVladimir Oltean [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1},
810460e985eSVladimir Oltean [VCAP_IS2_ACT_RSV] = { 36, 2},
811460e985eSVladimir Oltean [VCAP_IS2_ACT_ACL_ID] = { 38, 6},
81207d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_CNT] = { 44, 32},
81307d985eeSVladimir Oltean };
81420968054SVladimir Oltean
815e3aea296SVladimir Oltean static struct vcap_props vsc9959_vcap_props[] = {
816e3aea296SVladimir Oltean [VCAP_ES0] = {
817e3aea296SVladimir Oltean .action_type_width = 0,
818e3aea296SVladimir Oltean .action_table = {
819e3aea296SVladimir Oltean [ES0_ACTION_TYPE_NORMAL] = {
820e3aea296SVladimir Oltean .width = 72, /* HIT_STICKY not included */
821e3aea296SVladimir Oltean .count = 1,
822e3aea296SVladimir Oltean },
823e3aea296SVladimir Oltean },
824e3aea296SVladimir Oltean .target = S0,
825e3aea296SVladimir Oltean .keys = vsc9959_vcap_es0_keys,
826e3aea296SVladimir Oltean .actions = vsc9959_vcap_es0_actions,
827a61e365dSVladimir Oltean },
828a61e365dSVladimir Oltean [VCAP_IS1] = {
829a61e365dSVladimir Oltean .action_type_width = 0,
830a61e365dSVladimir Oltean .action_table = {
831a61e365dSVladimir Oltean [IS1_ACTION_TYPE_NORMAL] = {
832a61e365dSVladimir Oltean .width = 78, /* HIT_STICKY not included */
833a61e365dSVladimir Oltean .count = 4,
834a61e365dSVladimir Oltean },
835a61e365dSVladimir Oltean },
836a61e365dSVladimir Oltean .target = S1,
837a61e365dSVladimir Oltean .keys = vsc9959_vcap_is1_keys,
838a61e365dSVladimir Oltean .actions = vsc9959_vcap_is1_actions,
83907d985eeSVladimir Oltean },
84007d985eeSVladimir Oltean [VCAP_IS2] = {
84107d985eeSVladimir Oltean .action_type_width = 1,
84207d985eeSVladimir Oltean .action_table = {
84307d985eeSVladimir Oltean [IS2_ACTION_TYPE_NORMAL] = {
84407d985eeSVladimir Oltean .width = 44,
84507d985eeSVladimir Oltean .count = 2
84607d985eeSVladimir Oltean },
84707d985eeSVladimir Oltean [IS2_ACTION_TYPE_SMAC_SIP] = {
84807d985eeSVladimir Oltean .width = 6,
84907d985eeSVladimir Oltean .count = 4
85007d985eeSVladimir Oltean },
851c1c3993eSVladimir Oltean },
852c1c3993eSVladimir Oltean .target = S2,
853c1c3993eSVladimir Oltean .keys = vsc9959_vcap_is2_keys,
85407d985eeSVladimir Oltean .actions = vsc9959_vcap_is2_actions,
85507d985eeSVladimir Oltean },
85607d985eeSVladimir Oltean };
8572ac7c6c5SVladimir Oltean
8582ac7c6c5SVladimir Oltean static const struct ptp_clock_info vsc9959_ptp_caps = {
8592ac7c6c5SVladimir Oltean .owner = THIS_MODULE,
8602ac7c6c5SVladimir Oltean .name = "felix ptp",
8612ac7c6c5SVladimir Oltean .max_adj = 0x7fffffff,
8622ac7c6c5SVladimir Oltean .n_alarm = 0,
8632ac7c6c5SVladimir Oltean .n_ext_ts = 0,
8642ac7c6c5SVladimir Oltean .n_per_out = OCELOT_PTP_PINS_NUM,
8652ac7c6c5SVladimir Oltean .n_pins = OCELOT_PTP_PINS_NUM,
8662ac7c6c5SVladimir Oltean .pps = 0,
8672ac7c6c5SVladimir Oltean .gettime64 = ocelot_ptp_gettime64,
8682ac7c6c5SVladimir Oltean .settime64 = ocelot_ptp_settime64,
8692ac7c6c5SVladimir Oltean .adjtime = ocelot_ptp_adjtime,
8702ac7c6c5SVladimir Oltean .adjfine = ocelot_ptp_adjfine,
8712ac7c6c5SVladimir Oltean .verify = ocelot_ptp_verify,
8722ac7c6c5SVladimir Oltean .enable = ocelot_ptp_enable,
8732ac7c6c5SVladimir Oltean };
87456051948SVladimir Oltean
87556051948SVladimir Oltean #define VSC9959_INIT_TIMEOUT 50000
87656051948SVladimir Oltean #define VSC9959_GCB_RST_SLEEP 100
87756051948SVladimir Oltean #define VSC9959_SYS_RAMINIT_SLEEP 80
87856051948SVladimir Oltean
vsc9959_gcb_soft_rst_status(struct ocelot * ocelot)87956051948SVladimir Oltean static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
88056051948SVladimir Oltean {
88156051948SVladimir Oltean int val;
88275cea9cbSVladimir Oltean
88356051948SVladimir Oltean ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
88456051948SVladimir Oltean
88556051948SVladimir Oltean return val;
88656051948SVladimir Oltean }
88756051948SVladimir Oltean
vsc9959_sys_ram_init_status(struct ocelot * ocelot)88856051948SVladimir Oltean static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
88956051948SVladimir Oltean {
89056051948SVladimir Oltean return ocelot_read(ocelot, SYS_RAM_INIT);
89156051948SVladimir Oltean }
892c129fc55SVladimir Oltean
893c129fc55SVladimir Oltean /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
894c129fc55SVladimir Oltean * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT
89556051948SVladimir Oltean */
vsc9959_reset(struct ocelot * ocelot)89656051948SVladimir Oltean static int vsc9959_reset(struct ocelot *ocelot)
89756051948SVladimir Oltean {
89856051948SVladimir Oltean int val, err;
89956051948SVladimir Oltean
90075cea9cbSVladimir Oltean /* soft-reset the switch core */
90156051948SVladimir Oltean ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
90256051948SVladimir Oltean
90356051948SVladimir Oltean err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
90456051948SVladimir Oltean VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
90556051948SVladimir Oltean if (err) {
90656051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch core reset\n");
90756051948SVladimir Oltean return err;
90856051948SVladimir Oltean }
90956051948SVladimir Oltean
91056051948SVladimir Oltean /* initialize switch mem ~40us */
91156051948SVladimir Oltean ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
91256051948SVladimir Oltean err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
91356051948SVladimir Oltean VSC9959_SYS_RAMINIT_SLEEP,
91456051948SVladimir Oltean VSC9959_INIT_TIMEOUT);
91556051948SVladimir Oltean if (err) {
91656051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch sram init\n");
91756051948SVladimir Oltean return err;
91856051948SVladimir Oltean }
91956051948SVladimir Oltean
92075cea9cbSVladimir Oltean /* enable switch core */
92156051948SVladimir Oltean ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
92256051948SVladimir Oltean
92356051948SVladimir Oltean return 0;
92456051948SVladimir Oltean }
925aa92d836SMaxim Kochetkov
926aa92d836SMaxim Kochetkov /* Watermark encode
927aa92d836SMaxim Kochetkov * Bit 8: Unit; 0:1, 1:16
928aa92d836SMaxim Kochetkov * Bit 7-0: Value to be multiplied with unit
929aa92d836SMaxim Kochetkov */
vsc9959_wm_enc(u16 value)930aa92d836SMaxim Kochetkov static u16 vsc9959_wm_enc(u16 value)
93101326493SVladimir Oltean {
93201326493SVladimir Oltean WARN_ON(value >= 16 * BIT(8));
933aa92d836SMaxim Kochetkov
934aa92d836SMaxim Kochetkov if (value >= BIT(8))
935aa92d836SMaxim Kochetkov return BIT(8) | (value / 16);
936aa92d836SMaxim Kochetkov
937aa92d836SMaxim Kochetkov return value;
938aa92d836SMaxim Kochetkov }
939703b7621SVladimir Oltean
vsc9959_wm_dec(u16 wm)940703b7621SVladimir Oltean static u16 vsc9959_wm_dec(u16 wm)
941703b7621SVladimir Oltean {
942703b7621SVladimir Oltean WARN_ON(wm & ~GENMASK(8, 0));
943703b7621SVladimir Oltean
944703b7621SVladimir Oltean if (wm & BIT(8))
945703b7621SVladimir Oltean return (wm & GENMASK(7, 0)) * 16;
946703b7621SVladimir Oltean
947703b7621SVladimir Oltean return wm;
948703b7621SVladimir Oltean }
949703b7621SVladimir Oltean
vsc9959_wm_stat(u32 val,u32 * inuse,u32 * maxuse)950703b7621SVladimir Oltean static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
951703b7621SVladimir Oltean {
952703b7621SVladimir Oltean *inuse = (val & GENMASK(23, 12)) >> 12;
953703b7621SVladimir Oltean *maxuse = val & GENMASK(11, 0);
954703b7621SVladimir Oltean }
955bdeced75SVladimir Oltean
vsc9959_mdio_bus_alloc(struct ocelot * ocelot)956bdeced75SVladimir Oltean static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
9571382ba68SVladimir Oltean {
958bdeced75SVladimir Oltean struct pci_dev *pdev = to_pci_dev(ocelot->dev);
959bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot);
960bdeced75SVladimir Oltean struct enetc_mdio_priv *mdio_priv;
9611382ba68SVladimir Oltean struct device *dev = ocelot->dev;
962bdeced75SVladimir Oltean resource_size_t imdio_base;
963b4024c9eSClaudiu Manoil void __iomem *imdio_regs;
964bdeced75SVladimir Oltean struct resource res;
965bdeced75SVladimir Oltean struct enetc_hw *hw;
966bdeced75SVladimir Oltean struct mii_bus *bus;
967bdeced75SVladimir Oltean int port;
968bdeced75SVladimir Oltean int rc;
969bdeced75SVladimir Oltean
970e7026f15SColin Foster felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
971bdeced75SVladimir Oltean sizeof(struct phylink_pcs *),
972bdeced75SVladimir Oltean GFP_KERNEL);
973bdeced75SVladimir Oltean if (!felix->pcs) {
974bdeced75SVladimir Oltean dev_err(dev, "failed to allocate array for PCS PHYs\n");
975bdeced75SVladimir Oltean return -ENOMEM;
976bdeced75SVladimir Oltean }
9771382ba68SVladimir Oltean
9781382ba68SVladimir Oltean imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR);
9795fc080deSVladimir Oltean
9801382ba68SVladimir Oltean memcpy(&res, &vsc9959_imdio_res, sizeof(res));
9811382ba68SVladimir Oltean res.start += imdio_base;
982bdeced75SVladimir Oltean res.end += imdio_base;
983b4024c9eSClaudiu Manoil
984a180be79SGuobin Huang imdio_regs = devm_ioremap_resource(dev, &res);
985bdeced75SVladimir Oltean if (IS_ERR(imdio_regs))
986bdeced75SVladimir Oltean return PTR_ERR(imdio_regs);
987bdeced75SVladimir Oltean
988bdeced75SVladimir Oltean hw = enetc_hw_alloc(dev, imdio_regs);
989bdeced75SVladimir Oltean if (IS_ERR(hw)) {
990bdeced75SVladimir Oltean dev_err(dev, "failed to allocate ENETC HW structure\n");
991bdeced75SVladimir Oltean return PTR_ERR(hw);
992bdeced75SVladimir Oltean }
993209bdb7eSVladimir Oltean
994bdeced75SVladimir Oltean bus = mdiobus_alloc_size(sizeof(*mdio_priv));
995bdeced75SVladimir Oltean if (!bus)
996bdeced75SVladimir Oltean return -ENOMEM;
997bdeced75SVladimir Oltean
99880e87442SAndrew Lunn bus->name = "VSC9959 internal MDIO bus";
99980e87442SAndrew Lunn bus->read = enetc_mdio_read_c22;
100080e87442SAndrew Lunn bus->write = enetc_mdio_write_c22;
100180e87442SAndrew Lunn bus->read_c45 = enetc_mdio_read_c45;
1002bdeced75SVladimir Oltean bus->write_c45 = enetc_mdio_write_c45;
1003bdeced75SVladimir Oltean bus->parent = dev;
1004bdeced75SVladimir Oltean mdio_priv = bus->priv;
1005bdeced75SVladimir Oltean mdio_priv->hw = hw;
1006bdeced75SVladimir Oltean /* This gets added to imdio_regs, which already maps addresses
1007bdeced75SVladimir Oltean * starting with the proper offset.
1008bdeced75SVladimir Oltean */
1009bdeced75SVladimir Oltean mdio_priv->mdio_base = 0;
1010bdeced75SVladimir Oltean snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1011bdeced75SVladimir Oltean
1012bdeced75SVladimir Oltean /* Needed in order to initialize the bus mutex lock */
1013bdeced75SVladimir Oltean rc = mdiobus_register(bus);
1014bdeced75SVladimir Oltean if (rc < 0) {
1015209bdb7eSVladimir Oltean dev_err(dev, "failed to register MDIO bus\n");
1016bdeced75SVladimir Oltean mdiobus_free(bus);
1017bdeced75SVladimir Oltean return rc;
1018bdeced75SVladimir Oltean }
1019bdeced75SVladimir Oltean
1020bdeced75SVladimir Oltean felix->imdio = bus;
1021bdeced75SVladimir Oltean
1022bdeced75SVladimir Oltean for (port = 0; port < felix->info->num_ports; port++) {
1023e7026f15SColin Foster struct ocelot_port *ocelot_port = ocelot->ports[port];
1024bdeced75SVladimir Oltean struct phylink_pcs *phylink_pcs;
1025588d0550SIoana Ciornei
1026588d0550SIoana Ciornei if (dsa_is_unused_port(felix->ds, port))
1027bdeced75SVladimir Oltean continue;
1028588d0550SIoana Ciornei
1029588d0550SIoana Ciornei if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1030588d0550SIoana Ciornei continue;
10315767c6a8SRussell King (Oracle)
10325767c6a8SRussell King (Oracle) phylink_pcs = lynx_pcs_create_mdiodev(felix->imdio, port);
1033bdeced75SVladimir Oltean if (IS_ERR(phylink_pcs))
1034bdeced75SVladimir Oltean continue;
1035e7026f15SColin Foster
1036bdeced75SVladimir Oltean felix->pcs[port] = phylink_pcs;
1037bdeced75SVladimir Oltean
1038bdeced75SVladimir Oltean dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1039bdeced75SVladimir Oltean }
1040bdeced75SVladimir Oltean
1041bdeced75SVladimir Oltean return 0;
1042bdeced75SVladimir Oltean }
1043ccfdbab5SVladimir Oltean
vsc9959_mdio_bus_free(struct ocelot * ocelot)1044bdeced75SVladimir Oltean static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1045bdeced75SVladimir Oltean {
1046bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot);
1047bdeced75SVladimir Oltean int port;
1048bdeced75SVladimir Oltean
1049e7026f15SColin Foster for (port = 0; port < ocelot->num_phys_ports; port++) {
1050bdeced75SVladimir Oltean struct phylink_pcs *phylink_pcs = felix->pcs[port];
10515767c6a8SRussell King (Oracle)
1052e7026f15SColin Foster if (phylink_pcs)
1053bdeced75SVladimir Oltean lynx_pcs_destroy(phylink_pcs);
1054bdeced75SVladimir Oltean }
1055209bdb7eSVladimir Oltean mdiobus_unregister(felix->imdio);
1056bdeced75SVladimir Oltean mdiobus_free(felix->imdio);
1057bdeced75SVladimir Oltean }
105811afdc65SVladimir Oltean
105911afdc65SVladimir Oltean /* The switch considers any frame (regardless of size) as eligible for
106011afdc65SVladimir Oltean * transmission if the traffic class gate is open for at least 33 ns.
106111afdc65SVladimir Oltean * Overruns are prevented by cropping an interval at the end of the gate time
106211afdc65SVladimir Oltean * slot for which egress scheduling is blocked, but we need to still keep 33 ns
106311afdc65SVladimir Oltean * available for one packet to be transmitted, otherwise the port tc will hang.
106411afdc65SVladimir Oltean * This function returns the size of a gate interval that remains available for
106511afdc65SVladimir Oltean * setting the guard band, after reserving the space for one egress frame.
106611afdc65SVladimir Oltean */
vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns)106711afdc65SVladimir Oltean static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns)
106811afdc65SVladimir Oltean {
106911afdc65SVladimir Oltean /* Gate always open */
107011afdc65SVladimir Oltean if (gate_len_ns == U64_MAX)
107111afdc65SVladimir Oltean return U64_MAX;
1072*d44036caSVladimir Oltean
1073*d44036caSVladimir Oltean if (gate_len_ns < VSC9959_TAS_MIN_GATE_LEN_NS)
1074*d44036caSVladimir Oltean return 0;
107511afdc65SVladimir Oltean
107611afdc65SVladimir Oltean return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC;
107711afdc65SVladimir Oltean }
107855a515b1SVladimir Oltean
107955a515b1SVladimir Oltean /* Extract shortest continuous gate open intervals in ns for each traffic class
108055a515b1SVladimir Oltean * of a cyclic tc-taprio schedule. If a gate is always open, the duration is
108155a515b1SVladimir Oltean * considered U64_MAX. If the gate is always closed, it is considered 0.
108255a515b1SVladimir Oltean */
vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload * taprio,u64 min_gate_len[OCELOT_NUM_TC])108355a515b1SVladimir Oltean static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio,
108455a515b1SVladimir Oltean u64 min_gate_len[OCELOT_NUM_TC])
108555a515b1SVladimir Oltean {
108655a515b1SVladimir Oltean struct tc_taprio_sched_entry *entry;
10877e4babffSVladimir Oltean u64 gate_len[OCELOT_NUM_TC];
108855a515b1SVladimir Oltean u8 gates_ever_opened = 0;
108955a515b1SVladimir Oltean int tc, i, n;
109055a515b1SVladimir Oltean
109155a515b1SVladimir Oltean /* Initialize arrays */
109255a515b1SVladimir Oltean for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
109355a515b1SVladimir Oltean min_gate_len[tc] = U64_MAX;
109455a515b1SVladimir Oltean gate_len[tc] = 0;
109555a515b1SVladimir Oltean }
109655a515b1SVladimir Oltean
109755a515b1SVladimir Oltean /* If we don't have taprio, consider all gates as permanently open */
109855a515b1SVladimir Oltean if (!taprio)
109955a515b1SVladimir Oltean return;
110055a515b1SVladimir Oltean
110155a515b1SVladimir Oltean n = taprio->num_entries;
110255a515b1SVladimir Oltean
110355a515b1SVladimir Oltean /* Walk through the gate list twice to determine the length
110455a515b1SVladimir Oltean * of consecutively open gates for a traffic class, including
110555a515b1SVladimir Oltean * open gates that wrap around. We are just interested in the
110655a515b1SVladimir Oltean * minimum window size, and this doesn't change what the
110755a515b1SVladimir Oltean * minimum is (if the gate never closes, min_gate_len will
110855a515b1SVladimir Oltean * remain U64_MAX).
110955a515b1SVladimir Oltean */
111055a515b1SVladimir Oltean for (i = 0; i < 2 * n; i++) {
111155a515b1SVladimir Oltean entry = &taprio->entries[i % n];
111255a515b1SVladimir Oltean
111355a515b1SVladimir Oltean for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
111455a515b1SVladimir Oltean if (entry->gate_mask & BIT(tc)) {
11157e4babffSVladimir Oltean gate_len[tc] += entry->interval;
111655a515b1SVladimir Oltean gates_ever_opened |= BIT(tc);
111755a515b1SVladimir Oltean } else {
111855a515b1SVladimir Oltean /* Gate closes now, record a potential new
111955a515b1SVladimir Oltean * minimum and reinitialize length
11207e4babffSVladimir Oltean */
11217e4babffSVladimir Oltean if (min_gate_len[tc] > gate_len[tc] &&
112255a515b1SVladimir Oltean gate_len[tc])
112355a515b1SVladimir Oltean min_gate_len[tc] = gate_len[tc];
112455a515b1SVladimir Oltean gate_len[tc] = 0;
112555a515b1SVladimir Oltean }
112655a515b1SVladimir Oltean }
11277e4babffSVladimir Oltean }
11287e4babffSVladimir Oltean
11297e4babffSVladimir Oltean /* min_gate_len[tc] actually tracks minimum *open* gate time, so for
11307e4babffSVladimir Oltean * permanently closed gates, min_gate_len[tc] will still be U64_MAX.
11317e4babffSVladimir Oltean * Therefore they are currently indistinguishable from permanently
11327e4babffSVladimir Oltean * open gates. Overwrite the gate len with 0 when we know they're
11337e4babffSVladimir Oltean * actually permanently closed, i.e. after the loop above.
11347e4babffSVladimir Oltean */
11357e4babffSVladimir Oltean for (tc = 0; tc < OCELOT_NUM_TC; tc++)
11367e4babffSVladimir Oltean if (!(gates_ever_opened & BIT(tc)))
113755a515b1SVladimir Oltean min_gate_len[tc] = 0;
113855a515b1SVladimir Oltean }
1139843794bbSVladimir Oltean
1140843794bbSVladimir Oltean /* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ,
1141843794bbSVladimir Oltean * so we need to spell out the register access to each traffic class in helper
1142843794bbSVladimir Oltean * functions, to simplify callers
1143843794bbSVladimir Oltean */
vsc9959_port_qmaxsdu_set(struct ocelot * ocelot,int port,int tc,u32 max_sdu)1144843794bbSVladimir Oltean static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc,
1145843794bbSVladimir Oltean u32 max_sdu)
1146843794bbSVladimir Oltean {
1147843794bbSVladimir Oltean switch (tc) {
1148843794bbSVladimir Oltean case 0:
1149843794bbSVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0,
1150843794bbSVladimir Oltean port);
1151843794bbSVladimir Oltean break;
1152843794bbSVladimir Oltean case 1:
1153843794bbSVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1,
1154843794bbSVladimir Oltean port);
1155843794bbSVladimir Oltean break;
1156843794bbSVladimir Oltean case 2:
1157843794bbSVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2,
1158843794bbSVladimir Oltean port);
1159843794bbSVladimir Oltean break;
1160843794bbSVladimir Oltean case 3:
1161843794bbSVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3,
1162843794bbSVladimir Oltean port);
1163843794bbSVladimir Oltean break;
1164843794bbSVladimir Oltean case 4:
1165843794bbSVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4,
1166843794bbSVladimir Oltean port);
1167843794bbSVladimir Oltean break;
1168843794bbSVladimir Oltean case 5:
1169843794bbSVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5,
1170843794bbSVladimir Oltean port);
1171843794bbSVladimir Oltean break;
1172843794bbSVladimir Oltean case 6:
1173843794bbSVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6,
1174843794bbSVladimir Oltean port);
1175843794bbSVladimir Oltean break;
1176843794bbSVladimir Oltean case 7:
1177843794bbSVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7,
1178843794bbSVladimir Oltean port);
1179843794bbSVladimir Oltean break;
1180843794bbSVladimir Oltean }
1181843794bbSVladimir Oltean }
1182843794bbSVladimir Oltean
vsc9959_port_qmaxsdu_get(struct ocelot * ocelot,int port,int tc)1183843794bbSVladimir Oltean static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc)
1184843794bbSVladimir Oltean {
1185843794bbSVladimir Oltean switch (tc) {
1186843794bbSVladimir Oltean case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port);
1187843794bbSVladimir Oltean case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port);
1188843794bbSVladimir Oltean case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port);
1189843794bbSVladimir Oltean case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port);
1190843794bbSVladimir Oltean case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port);
1191843794bbSVladimir Oltean case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port);
1192843794bbSVladimir Oltean case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port);
1193843794bbSVladimir Oltean case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port);
1194843794bbSVladimir Oltean default:
1195843794bbSVladimir Oltean return 0;
1196843794bbSVladimir Oltean }
1197843794bbSVladimir Oltean }
11981712be05SVladimir Oltean
vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload * taprio,int tc)11991712be05SVladimir Oltean static u32 vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload *taprio, int tc)
12001712be05SVladimir Oltean {
12011712be05SVladimir Oltean if (!taprio || !taprio->max_sdu[tc])
12021712be05SVladimir Oltean return 0;
12031712be05SVladimir Oltean
12041712be05SVladimir Oltean return taprio->max_sdu[tc] + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN;
12051712be05SVladimir Oltean }
120655a515b1SVladimir Oltean
120755a515b1SVladimir Oltean /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the
120855a515b1SVladimir Oltean * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU
120955a515b1SVladimir Oltean * values (the default value is 1518). Also, for traffic class windows smaller
121055a515b1SVladimir Oltean * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame
121155a515b1SVladimir Oltean * dropping, such that these won't hang the port, as they will never be sent.
121255a515b1SVladimir Oltean */
vsc9959_tas_guard_bands_update(struct ocelot * ocelot,int port)121355a515b1SVladimir Oltean static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port)
121455a515b1SVladimir Oltean {
1215c6efb4aeSVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port];
12161712be05SVladimir Oltean struct ocelot_mm_state *mm = &ocelot->mm[port];
121755a515b1SVladimir Oltean struct tc_taprio_qopt_offload *taprio;
1218c6efb4aeSVladimir Oltean u64 min_gate_len[OCELOT_NUM_TC];
1219c6efb4aeSVladimir Oltean u32 val, maxlen, add_frag_size;
122055a515b1SVladimir Oltean u64 needed_min_frag_time_ps;
122155a515b1SVladimir Oltean int speed, picos_per_byte;
122255a515b1SVladimir Oltean u64 needed_bit_time_ps;
122355a515b1SVladimir Oltean u8 tas_speed;
122455a515b1SVladimir Oltean int tc;
1225009d30f1SVladimir Oltean
122655a515b1SVladimir Oltean lockdep_assert_held(&ocelot->fwd_domain_lock);
12271712be05SVladimir Oltean
12281712be05SVladimir Oltean taprio = ocelot_port->taprio;
122955a515b1SVladimir Oltean
123055a515b1SVladimir Oltean val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port);
123155a515b1SVladimir Oltean tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val);
123255a515b1SVladimir Oltean
123355a515b1SVladimir Oltean switch (tas_speed) {
123455a515b1SVladimir Oltean case OCELOT_SPEED_10:
123555a515b1SVladimir Oltean speed = SPEED_10;
123655a515b1SVladimir Oltean break;
123755a515b1SVladimir Oltean case OCELOT_SPEED_100:
123855a515b1SVladimir Oltean speed = SPEED_100;
123955a515b1SVladimir Oltean break;
124055a515b1SVladimir Oltean case OCELOT_SPEED_1000:
124155a515b1SVladimir Oltean speed = SPEED_1000;
124255a515b1SVladimir Oltean break;
124355a515b1SVladimir Oltean case OCELOT_SPEED_2500:
124455a515b1SVladimir Oltean speed = SPEED_2500;
124555a515b1SVladimir Oltean break;
124655a515b1SVladimir Oltean default:
124755a515b1SVladimir Oltean return;
124855a515b1SVladimir Oltean }
124955a515b1SVladimir Oltean
125055a515b1SVladimir Oltean picos_per_byte = (USEC_PER_SEC * 8) / speed;
125155a515b1SVladimir Oltean
125255a515b1SVladimir Oltean val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG);
125355a515b1SVladimir Oltean /* MAXLEN_CFG accounts automatically for VLAN. We need to include it
125455a515b1SVladimir Oltean * manually in the bit time calculation, plus the preamble and SFD.
125555a515b1SVladimir Oltean */
125655a515b1SVladimir Oltean maxlen = val + 2 * VLAN_HLEN;
125755a515b1SVladimir Oltean /* Consider the standard Ethernet overhead of 8 octets preamble+SFD,
125855a515b1SVladimir Oltean * 4 octets FCS, 12 octets IFG.
12596ac7a27aSVladimir Oltean */
126055a515b1SVladimir Oltean needed_bit_time_ps = (u64)(maxlen + 24) * picos_per_byte;
1261c6efb4aeSVladimir Oltean
1262c6efb4aeSVladimir Oltean /* Preemptible TCs don't need to pass a full MTU, the port will
1263c6efb4aeSVladimir Oltean * automatically emit a HOLD request when a preemptible TC gate closes
1264c6efb4aeSVladimir Oltean */
1265c6efb4aeSVladimir Oltean val = ocelot_read_rix(ocelot, QSYS_PREEMPTION_CFG, port);
1266c6efb4aeSVladimir Oltean add_frag_size = QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(val);
1267c6efb4aeSVladimir Oltean needed_min_frag_time_ps = picos_per_byte *
1268c6efb4aeSVladimir Oltean (u64)(24 + 2 * ethtool_mm_frag_size_add_to_min(add_frag_size));
126955a515b1SVladimir Oltean
1270c6efb4aeSVladimir Oltean dev_dbg(ocelot->dev,
1271c6efb4aeSVladimir Oltean "port %d: max frame size %d needs %llu ps, %llu ps for mPackets at speed %d\n",
1272c6efb4aeSVladimir Oltean port, maxlen, needed_bit_time_ps, needed_min_frag_time_ps,
127355a515b1SVladimir Oltean speed);
12741712be05SVladimir Oltean
127555a515b1SVladimir Oltean vsc9959_tas_min_gate_lengths(taprio, min_gate_len);
127655a515b1SVladimir Oltean
12771712be05SVladimir Oltean for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
127811afdc65SVladimir Oltean u32 requested_max_sdu = vsc9959_tas_tc_max_sdu(taprio, tc);
127955a515b1SVladimir Oltean u64 remaining_gate_len_ps;
128055a515b1SVladimir Oltean u32 max_sdu;
128111afdc65SVladimir Oltean
128211afdc65SVladimir Oltean remaining_gate_len_ps =
128311afdc65SVladimir Oltean vsc9959_tas_remaining_gate_len_ps(min_gate_len[tc]);
1284c6efb4aeSVladimir Oltean
1285c6efb4aeSVladimir Oltean if ((mm->active_preemptible_tcs & BIT(tc)) ?
1286c6efb4aeSVladimir Oltean remaining_gate_len_ps > needed_min_frag_time_ps :
128755a515b1SVladimir Oltean remaining_gate_len_ps > needed_bit_time_ps) {
128855a515b1SVladimir Oltean /* Setting QMAXSDU_CFG to 0 disables oversized frame
128955a515b1SVladimir Oltean * dropping.
12901712be05SVladimir Oltean */
129155a515b1SVladimir Oltean max_sdu = requested_max_sdu;
129255a515b1SVladimir Oltean dev_dbg(ocelot->dev,
129355a515b1SVladimir Oltean "port %d tc %d min gate len %llu"
129455a515b1SVladimir Oltean ", sending all frames\n",
129555a515b1SVladimir Oltean port, tc, min_gate_len[tc]);
129655a515b1SVladimir Oltean } else {
129755a515b1SVladimir Oltean /* If traffic class doesn't support a full MTU sized
129855a515b1SVladimir Oltean * frame, make sure to enable oversize frame dropping
129911afdc65SVladimir Oltean * for frames larger than the smallest that would fit.
130011afdc65SVladimir Oltean *
130111afdc65SVladimir Oltean * However, the exact same register, QSYS_QMAXSDU_CFG_*,
130211afdc65SVladimir Oltean * controls not only oversized frame dropping, but also
130311afdc65SVladimir Oltean * per-tc static guard band lengths, so it reduces the
130411afdc65SVladimir Oltean * useful gate interval length. Therefore, be careful
130511afdc65SVladimir Oltean * to calculate a guard band (and therefore max_sdu)
130655a515b1SVladimir Oltean * that still leaves 33 ns available in the time slot.
130711afdc65SVladimir Oltean */
130855a515b1SVladimir Oltean max_sdu = div_u64(remaining_gate_len_ps, picos_per_byte);
130955a515b1SVladimir Oltean /* A TC gate may be completely closed, which is a
131055a515b1SVladimir Oltean * special case where all packets are oversized.
131155a515b1SVladimir Oltean * Any limit smaller than 64 octets accomplishes this
131255a515b1SVladimir Oltean */
131355a515b1SVladimir Oltean if (!max_sdu)
131455a515b1SVladimir Oltean max_sdu = 1;
131555a515b1SVladimir Oltean /* Take L1 overhead into account, but just don't allow
131655a515b1SVladimir Oltean * max_sdu to go negative or to 0. Here we use 20
131755a515b1SVladimir Oltean * because QSYS_MAXSDU_CFG_* already counts the 4 FCS
131855a515b1SVladimir Oltean * octets as part of packet size.
131955a515b1SVladimir Oltean */
132055a515b1SVladimir Oltean if (max_sdu > 20)
13211712be05SVladimir Oltean max_sdu -= 20;
13221712be05SVladimir Oltean
13231712be05SVladimir Oltean if (requested_max_sdu && requested_max_sdu < max_sdu)
13241712be05SVladimir Oltean max_sdu = requested_max_sdu;
132555a515b1SVladimir Oltean
132655a515b1SVladimir Oltean dev_info(ocelot->dev,
132755a515b1SVladimir Oltean "port %d tc %d min gate length %llu"
132855a515b1SVladimir Oltean " ns not enough for max frame size %d at %d"
132955a515b1SVladimir Oltean " Mbps, dropping frames over %d"
133055a515b1SVladimir Oltean " octets including FCS\n",
133155a515b1SVladimir Oltean port, tc, min_gate_len[tc], maxlen, speed,
133255a515b1SVladimir Oltean max_sdu);
133355a515b1SVladimir Oltean }
1334843794bbSVladimir Oltean
133555a515b1SVladimir Oltean vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu);
133655a515b1SVladimir Oltean }
133755a515b1SVladimir Oltean
1338843794bbSVladimir Oltean ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port);
1339843794bbSVladimir Oltean
134055a515b1SVladimir Oltean ocelot->ops->cut_through_fwd(ocelot);
134155a515b1SVladimir Oltean }
1342de143c0eSXiaoliang Yang
vsc9959_sched_speed_set(struct ocelot * ocelot,int port,u32 speed)1343de143c0eSXiaoliang Yang static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1344de143c0eSXiaoliang Yang u32 speed)
134555a515b1SVladimir Oltean {
1346dba1e466SXiaoliang Yang struct ocelot_port *ocelot_port = ocelot->ports[port];
1347dba1e466SXiaoliang Yang u8 tas_speed;
1348dba1e466SXiaoliang Yang
1349dba1e466SXiaoliang Yang switch (speed) {
1350dba1e466SXiaoliang Yang case SPEED_10:
1351dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_10;
1352dba1e466SXiaoliang Yang break;
1353dba1e466SXiaoliang Yang case SPEED_100:
1354dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_100;
1355dba1e466SXiaoliang Yang break;
1356dba1e466SXiaoliang Yang case SPEED_1000:
1357dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_1000;
1358dba1e466SXiaoliang Yang break;
1359dba1e466SXiaoliang Yang case SPEED_2500:
1360dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_2500;
1361dba1e466SXiaoliang Yang break;
1362dba1e466SXiaoliang Yang default:
1363dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_1000;
1364dba1e466SXiaoliang Yang break;
1365dba1e466SXiaoliang Yang }
1366009d30f1SVladimir Oltean
1367a4bb481aSVladimir Oltean mutex_lock(&ocelot->fwd_domain_lock);
1368de143c0eSXiaoliang Yang
1369dba1e466SXiaoliang Yang ocelot_rmw_rix(ocelot,
1370de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED(tas_speed),
1371de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED_M,
137255a515b1SVladimir Oltean QSYS_TAG_CONFIG, port);
137355a515b1SVladimir Oltean
137455a515b1SVladimir Oltean if (ocelot_port->taprio)
137555a515b1SVladimir Oltean vsc9959_tas_guard_bands_update(ocelot, port);
1376009d30f1SVladimir Oltean
1377de143c0eSXiaoliang Yang mutex_unlock(&ocelot->fwd_domain_lock);
1378de143c0eSXiaoliang Yang }
1379de143c0eSXiaoliang Yang
vsc9959_new_base_time(struct ocelot * ocelot,ktime_t base_time,u64 cycle_time,struct timespec64 * new_base_ts)1380de143c0eSXiaoliang Yang static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1381de143c0eSXiaoliang Yang u64 cycle_time,
1382de143c0eSXiaoliang Yang struct timespec64 *new_base_ts)
1383de143c0eSXiaoliang Yang {
1384de143c0eSXiaoliang Yang struct timespec64 ts;
1385de143c0eSXiaoliang Yang ktime_t new_base_time;
1386de143c0eSXiaoliang Yang ktime_t current_time;
1387de143c0eSXiaoliang Yang
1388de143c0eSXiaoliang Yang ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1389de143c0eSXiaoliang Yang current_time = timespec64_to_ktime(ts);
1390de143c0eSXiaoliang Yang new_base_time = base_time;
1391de143c0eSXiaoliang Yang
1392de143c0eSXiaoliang Yang if (base_time < current_time) {
1393de143c0eSXiaoliang Yang u64 nr_of_cycles = current_time - base_time;
1394de143c0eSXiaoliang Yang
1395de143c0eSXiaoliang Yang do_div(nr_of_cycles, cycle_time);
1396de143c0eSXiaoliang Yang new_base_time += cycle_time * (nr_of_cycles + 1);
1397de143c0eSXiaoliang Yang }
1398de143c0eSXiaoliang Yang
1399de143c0eSXiaoliang Yang *new_base_ts = ktime_to_timespec64(new_base_time);
1400de143c0eSXiaoliang Yang }
1401de143c0eSXiaoliang Yang
vsc9959_tas_read_cfg_status(struct ocelot * ocelot)1402de143c0eSXiaoliang Yang static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1403de143c0eSXiaoliang Yang {
1404de143c0eSXiaoliang Yang return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1405de143c0eSXiaoliang Yang }
1406de143c0eSXiaoliang Yang
vsc9959_tas_gcl_set(struct ocelot * ocelot,const u32 gcl_ix,struct tc_taprio_sched_entry * entry)1407de143c0eSXiaoliang Yang static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1408de143c0eSXiaoliang Yang struct tc_taprio_sched_entry *entry)
1409de143c0eSXiaoliang Yang {
1410de143c0eSXiaoliang Yang ocelot_write(ocelot,
1411de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1412de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1413de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1);
1414de143c0eSXiaoliang Yang ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1415de143c0eSXiaoliang Yang }
1416de143c0eSXiaoliang Yang
vsc9959_qos_port_tas_set(struct ocelot * ocelot,int port,struct tc_taprio_qopt_offload * taprio)1417de143c0eSXiaoliang Yang static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1418de143c0eSXiaoliang Yang struct tc_taprio_qopt_offload *taprio)
14198670dc33SXiaoliang Yang {
1420de143c0eSXiaoliang Yang struct ocelot_port *ocelot_port = ocelot->ports[port];
1421de143c0eSXiaoliang Yang struct timespec64 base_ts;
1422de143c0eSXiaoliang Yang int ret, i;
1423de143c0eSXiaoliang Yang u32 val;
1424009d30f1SVladimir Oltean
14258670dc33SXiaoliang Yang mutex_lock(&ocelot->fwd_domain_lock);
14262d800bc5SVladimir Oltean
1427a1ca9f8bSVladimir Oltean if (taprio->cmd == TAPRIO_CMD_DESTROY) {
1428d68a373bSVladimir Oltean ocelot_port_mqprio(ocelot, port, &taprio->mqprio);
1429de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,
1430de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port);
14311c9017e4SVladimir Oltean
14321c9017e4SVladimir Oltean taprio_offload_free(ocelot_port->taprio);
14331c9017e4SVladimir Oltean ocelot_port->taprio = NULL;
143455a515b1SVladimir Oltean
143555a515b1SVladimir Oltean vsc9959_tas_guard_bands_update(ocelot, port);
1436009d30f1SVladimir Oltean
1437de143c0eSXiaoliang Yang mutex_unlock(&ocelot->fwd_domain_lock);
14382d800bc5SVladimir Oltean return 0;
1439cad7526fSDan Carpenter } else if (taprio->cmd != TAPRIO_CMD_REPLACE) {
1440cad7526fSDan Carpenter ret = -EOPNOTSUPP;
1441de143c0eSXiaoliang Yang goto err_unlock;
1442de143c0eSXiaoliang Yang }
1443a1ca9f8bSVladimir Oltean
1444a1ca9f8bSVladimir Oltean ret = ocelot_port_mqprio(ocelot, port, &taprio->mqprio);
1445a1ca9f8bSVladimir Oltean if (ret)
1446a1ca9f8bSVladimir Oltean goto err_unlock;
1447de143c0eSXiaoliang Yang
14488670dc33SXiaoliang Yang if (taprio->cycle_time > NSEC_PER_SEC ||
14498670dc33SXiaoliang Yang taprio->cycle_time_extension >= NSEC_PER_SEC) {
1450a1ca9f8bSVladimir Oltean ret = -EINVAL;
14518670dc33SXiaoliang Yang goto err_reset_tc;
1452de143c0eSXiaoliang Yang }
14538670dc33SXiaoliang Yang
14548670dc33SXiaoliang Yang if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) {
1455a1ca9f8bSVladimir Oltean ret = -ERANGE;
14568670dc33SXiaoliang Yang goto err_reset_tc;
1457de143c0eSXiaoliang Yang }
1458297c4de6SMichael Walle
1459297c4de6SMichael Walle /* Enable guard band. The switch will schedule frames without taking
1460297c4de6SMichael Walle * their length into account. Thus we'll always need to enable the
1461297c4de6SMichael Walle * guard band which reserves the time of a maximum sized frame at the
1462297c4de6SMichael Walle * end of the time window.
1463297c4de6SMichael Walle *
1464297c4de6SMichael Walle * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we
1465297c4de6SMichael Walle * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n
1466316bcffeSXiaoliang Yang * operate on the port number.
1467297c4de6SMichael Walle */
1468297c4de6SMichael Walle ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1469de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1470de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1471de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1472de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL);
1473de143c0eSXiaoliang Yang
1474de143c0eSXiaoliang Yang /* Hardware errata - Admin config could not be overwritten if
1475de143c0eSXiaoliang Yang * config is pending, need reset the TAS module
1476de143c0eSXiaoliang Yang */
14778670dc33SXiaoliang Yang val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
14788670dc33SXiaoliang Yang if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) {
1479a1ca9f8bSVladimir Oltean ret = -EBUSY;
14808670dc33SXiaoliang Yang goto err_reset_tc;
1481de143c0eSXiaoliang Yang }
1482de143c0eSXiaoliang Yang
1483de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot,
1484de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE |
1485de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1486de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1487de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE |
1488de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1489de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1490de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port);
1491de143c0eSXiaoliang Yang
1492de143c0eSXiaoliang Yang vsc9959_new_base_time(ocelot, taprio->base_time,
1493de143c0eSXiaoliang Yang taprio->cycle_time, &base_ts);
1494de143c0eSXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1495de143c0eSXiaoliang Yang ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1496de143c0eSXiaoliang Yang val = upper_32_bits(base_ts.tv_sec);
1497de143c0eSXiaoliang Yang ocelot_write(ocelot,
1498de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1499de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1500de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3);
1501de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1502de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1503de143c0eSXiaoliang Yang
1504de143c0eSXiaoliang Yang for (i = 0; i < taprio->num_entries; i++)
1505de143c0eSXiaoliang Yang vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1506de143c0eSXiaoliang Yang
1507de143c0eSXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1508de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1509de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL);
1510de143c0eSXiaoliang Yang
1511de143c0eSXiaoliang Yang ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1512de143c0eSXiaoliang Yang !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
15131c9017e4SVladimir Oltean 10, 100000);
1514a1ca9f8bSVladimir Oltean if (ret)
15151c9017e4SVladimir Oltean goto err_reset_tc;
15161c9017e4SVladimir Oltean
151755a515b1SVladimir Oltean ocelot_port->taprio = taprio_offload_get(taprio);
1518de143c0eSXiaoliang Yang vsc9959_tas_guard_bands_update(ocelot, port);
1519009d30f1SVladimir Oltean
1520a1ca9f8bSVladimir Oltean mutex_unlock(&ocelot->fwd_domain_lock);
1521a1ca9f8bSVladimir Oltean
1522a1ca9f8bSVladimir Oltean return 0;
1523a1ca9f8bSVladimir Oltean
1524a1ca9f8bSVladimir Oltean err_reset_tc:
1525a1ca9f8bSVladimir Oltean taprio->mqprio.qopt.num_tc = 0;
1526a1ca9f8bSVladimir Oltean ocelot_port_mqprio(ocelot, port, &taprio->mqprio);
1527009d30f1SVladimir Oltean err_unlock:
15288670dc33SXiaoliang Yang mutex_unlock(&ocelot->fwd_domain_lock);
1529de143c0eSXiaoliang Yang
1530de143c0eSXiaoliang Yang return ret;
1531de143c0eSXiaoliang Yang }
15328670dc33SXiaoliang Yang
vsc9959_tas_clock_adjust(struct ocelot * ocelot)15338670dc33SXiaoliang Yang static void vsc9959_tas_clock_adjust(struct ocelot *ocelot)
15341c9017e4SVladimir Oltean {
15358670dc33SXiaoliang Yang struct tc_taprio_qopt_offload *taprio;
15368670dc33SXiaoliang Yang struct ocelot_port *ocelot_port;
15378670dc33SXiaoliang Yang struct timespec64 base_ts;
15388670dc33SXiaoliang Yang int port;
15398670dc33SXiaoliang Yang u32 val;
1540009d30f1SVladimir Oltean
15418670dc33SXiaoliang Yang mutex_lock(&ocelot->fwd_domain_lock);
15428670dc33SXiaoliang Yang
15431c9017e4SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) {
15441c9017e4SVladimir Oltean ocelot_port = ocelot->ports[port];
15451c9017e4SVladimir Oltean taprio = ocelot_port->taprio;
15468670dc33SXiaoliang Yang if (!taprio)
15478670dc33SXiaoliang Yang continue;
15488670dc33SXiaoliang Yang
15498670dc33SXiaoliang Yang ocelot_rmw(ocelot,
15508670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port),
15518670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M,
15528670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL);
1553d68a373bSVladimir Oltean
1554d68a373bSVladimir Oltean /* Disable time-aware shaper */
15558670dc33SXiaoliang Yang ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,
15568670dc33SXiaoliang Yang QSYS_TAG_CONFIG, port);
15571c9017e4SVladimir Oltean
15581c9017e4SVladimir Oltean vsc9959_new_base_time(ocelot, taprio->base_time,
15598670dc33SXiaoliang Yang taprio->cycle_time, &base_ts);
15608670dc33SXiaoliang Yang
15618670dc33SXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
15628670dc33SXiaoliang Yang ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec),
15638670dc33SXiaoliang Yang QSYS_PARAM_CFG_REG_2);
15648670dc33SXiaoliang Yang val = upper_32_bits(base_ts.tv_sec);
15658670dc33SXiaoliang Yang ocelot_rmw(ocelot,
15668670dc33SXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val),
15678670dc33SXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M,
15688670dc33SXiaoliang Yang QSYS_PARAM_CFG_REG_3);
15698670dc33SXiaoliang Yang
15708670dc33SXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
15718670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
15728670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL);
1573d68a373bSVladimir Oltean
1574d68a373bSVladimir Oltean /* Re-enable time-aware shaper */
15758670dc33SXiaoliang Yang ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE,
15768670dc33SXiaoliang Yang QSYS_TAG_CONFIG_ENABLE,
15778670dc33SXiaoliang Yang QSYS_TAG_CONFIG, port);
1578009d30f1SVladimir Oltean }
15798670dc33SXiaoliang Yang mutex_unlock(&ocelot->fwd_domain_lock);
15808670dc33SXiaoliang Yang }
15810fbabf87SXiaoliang Yang
vsc9959_qos_port_cbs_set(struct dsa_switch * ds,int port,struct tc_cbs_qopt_offload * cbs_qopt)15820fbabf87SXiaoliang Yang static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
15830fbabf87SXiaoliang Yang struct tc_cbs_qopt_offload *cbs_qopt)
15840fbabf87SXiaoliang Yang {
15850fbabf87SXiaoliang Yang struct ocelot *ocelot = ds->priv;
15860fbabf87SXiaoliang Yang int port_ix = port * 8 + cbs_qopt->queue;
15870fbabf87SXiaoliang Yang u32 rate, burst;
15880fbabf87SXiaoliang Yang
15890fbabf87SXiaoliang Yang if (cbs_qopt->queue >= ds->num_tx_queues)
15900fbabf87SXiaoliang Yang return -EINVAL;
15910fbabf87SXiaoliang Yang
15920fbabf87SXiaoliang Yang if (!cbs_qopt->enable) {
15930fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
15940fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(0),
15950fbabf87SXiaoliang Yang QSYS_CIR_CFG, port_ix);
15960fbabf87SXiaoliang Yang
15970fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
15980fbabf87SXiaoliang Yang QSYS_SE_CFG, port_ix);
15990fbabf87SXiaoliang Yang
16000fbabf87SXiaoliang Yang return 0;
16010fbabf87SXiaoliang Yang }
16020fbabf87SXiaoliang Yang
16030fbabf87SXiaoliang Yang /* Rate unit is 100 kbps */
16040fbabf87SXiaoliang Yang rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
16050fbabf87SXiaoliang Yang /* Avoid using zero rate */
16060fbabf87SXiaoliang Yang rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
16070fbabf87SXiaoliang Yang /* Burst unit is 4kB */
16080fbabf87SXiaoliang Yang burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1609b014d043SColin Ian King /* Avoid using zero burst size */
16100fbabf87SXiaoliang Yang burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
16110fbabf87SXiaoliang Yang ocelot_write_gix(ocelot,
16120fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_RATE(rate) |
16130fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(burst),
16140fbabf87SXiaoliang Yang QSYS_CIR_CFG,
16150fbabf87SXiaoliang Yang port_ix);
16160fbabf87SXiaoliang Yang
16170fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot,
16180fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE(0) |
16190fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA,
16200fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA |
16210fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE_M,
16220fbabf87SXiaoliang Yang QSYS_SE_CFG,
16230fbabf87SXiaoliang Yang port_ix);
16240fbabf87SXiaoliang Yang
16250fbabf87SXiaoliang Yang return 0;
16260fbabf87SXiaoliang Yang }
16271712be05SVladimir Oltean
vsc9959_qos_query_caps(struct tc_query_caps_base * base)16281712be05SVladimir Oltean static int vsc9959_qos_query_caps(struct tc_query_caps_base *base)
16291712be05SVladimir Oltean {
1630aac80140SVladimir Oltean switch (base->type) {
1631aac80140SVladimir Oltean case TC_SETUP_QDISC_MQPRIO: {
1632aac80140SVladimir Oltean struct tc_mqprio_caps *caps = base->caps;
1633aac80140SVladimir Oltean
1634aac80140SVladimir Oltean caps->validate_queue_counts = true;
1635aac80140SVladimir Oltean
1636aac80140SVladimir Oltean return 0;
16371712be05SVladimir Oltean }
16381712be05SVladimir Oltean case TC_SETUP_QDISC_TAPRIO: {
16391712be05SVladimir Oltean struct tc_taprio_caps *caps = base->caps;
16401712be05SVladimir Oltean
16411712be05SVladimir Oltean caps->supports_queue_max_sdu = true;
16421712be05SVladimir Oltean
16431712be05SVladimir Oltean return 0;
16441712be05SVladimir Oltean }
16451712be05SVladimir Oltean default:
16461712be05SVladimir Oltean return -EOPNOTSUPP;
16471712be05SVladimir Oltean }
16481712be05SVladimir Oltean }
1649009d30f1SVladimir Oltean
vsc9959_qos_port_mqprio(struct ocelot * ocelot,int port,struct tc_mqprio_qopt_offload * mqprio)1650009d30f1SVladimir Oltean static int vsc9959_qos_port_mqprio(struct ocelot *ocelot, int port,
1651009d30f1SVladimir Oltean struct tc_mqprio_qopt_offload *mqprio)
1652009d30f1SVladimir Oltean {
1653009d30f1SVladimir Oltean int ret;
1654009d30f1SVladimir Oltean
1655009d30f1SVladimir Oltean mutex_lock(&ocelot->fwd_domain_lock);
1656009d30f1SVladimir Oltean ret = ocelot_port_mqprio(ocelot, port, mqprio);
1657009d30f1SVladimir Oltean mutex_unlock(&ocelot->fwd_domain_lock);
1658009d30f1SVladimir Oltean
1659009d30f1SVladimir Oltean return ret;
1660009d30f1SVladimir Oltean }
1661de143c0eSXiaoliang Yang
vsc9959_port_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)1662de143c0eSXiaoliang Yang static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1663de143c0eSXiaoliang Yang enum tc_setup_type type,
1664de143c0eSXiaoliang Yang void *type_data)
1665de143c0eSXiaoliang Yang {
1666de143c0eSXiaoliang Yang struct ocelot *ocelot = ds->priv;
1667de143c0eSXiaoliang Yang
16681712be05SVladimir Oltean switch (type) {
16691712be05SVladimir Oltean case TC_QUERY_CAPS:
1670de143c0eSXiaoliang Yang return vsc9959_qos_query_caps(type_data);
1671de143c0eSXiaoliang Yang case TC_SETUP_QDISC_TAPRIO:
1672aac80140SVladimir Oltean return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1673009d30f1SVladimir Oltean case TC_SETUP_QDISC_MQPRIO:
16740fbabf87SXiaoliang Yang return vsc9959_qos_port_mqprio(ocelot, port, type_data);
16750fbabf87SXiaoliang Yang case TC_SETUP_QDISC_CBS:
1676de143c0eSXiaoliang Yang return vsc9959_qos_port_cbs_set(ds, port, type_data);
1677de143c0eSXiaoliang Yang default:
1678de143c0eSXiaoliang Yang return -EOPNOTSUPP;
1679de143c0eSXiaoliang Yang }
1680de143c0eSXiaoliang Yang }
16817d4b564dSXiaoliang Yang
16827d4b564dSXiaoliang Yang #define VSC9959_PSFP_SFID_MAX 175
168376c13edeSXiaoliang Yang #define VSC9959_PSFP_GATE_ID_MAX 183
16847d4b564dSXiaoliang Yang #define VSC9959_PSFP_POLICER_BASE 63
168523ae3a78SXiaoliang Yang #define VSC9959_PSFP_POLICER_MAX 383
168623ae3a78SXiaoliang Yang #define VSC9959_PSFP_GATE_LIST_NUM 4
16877d4b564dSXiaoliang Yang #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000
16887d4b564dSXiaoliang Yang
16897d4b564dSXiaoliang Yang struct felix_stream {
16907d4b564dSXiaoliang Yang struct list_head list;
1691a7e13edfSXiaoliang Yang unsigned long id;
1692a7e13edfSXiaoliang Yang bool dummy;
1693a7e13edfSXiaoliang Yang int ports;
16947d4b564dSXiaoliang Yang int port;
16957d4b564dSXiaoliang Yang u8 dmac[ETH_ALEN];
16967d4b564dSXiaoliang Yang u16 vid;
16977d4b564dSXiaoliang Yang s8 prio;
16987d4b564dSXiaoliang Yang u8 sfid_valid;
16997d4b564dSXiaoliang Yang u8 ssid_valid;
17007d4b564dSXiaoliang Yang u32 sfid;
17017d4b564dSXiaoliang Yang u32 ssid;
17027d4b564dSXiaoliang Yang };
170325027c84SVladimir Oltean
170425027c84SVladimir Oltean struct felix_stream_filter_counters {
170525027c84SVladimir Oltean u64 match;
170625027c84SVladimir Oltean u64 not_pass_gate;
170725027c84SVladimir Oltean u64 not_pass_sdu;
170825027c84SVladimir Oltean u64 red;
170925027c84SVladimir Oltean };
17107d4b564dSXiaoliang Yang
171125027c84SVladimir Oltean struct felix_stream_filter {
17127d4b564dSXiaoliang Yang struct felix_stream_filter_counters stats;
17137d4b564dSXiaoliang Yang struct list_head list;
17147d4b564dSXiaoliang Yang refcount_t refcount;
17157d4b564dSXiaoliang Yang u32 index;
1716a7e13edfSXiaoliang Yang u8 enable;
17177d4b564dSXiaoliang Yang int portmask;
17187d4b564dSXiaoliang Yang u8 sg_valid;
17197d4b564dSXiaoliang Yang u32 sgid;
17207d4b564dSXiaoliang Yang u8 fm_valid;
17217d4b564dSXiaoliang Yang u32 fmid;
17227d4b564dSXiaoliang Yang u8 prio_valid;
17237d4b564dSXiaoliang Yang u8 prio;
17247d4b564dSXiaoliang Yang u32 maxsdu;
17257d4b564dSXiaoliang Yang };
172623ae3a78SXiaoliang Yang
172723ae3a78SXiaoliang Yang struct felix_stream_gate {
172823ae3a78SXiaoliang Yang u32 index;
172923ae3a78SXiaoliang Yang u8 enable;
173023ae3a78SXiaoliang Yang u8 ipv_valid;
173123ae3a78SXiaoliang Yang u8 init_ipv;
173223ae3a78SXiaoliang Yang u64 basetime;
173323ae3a78SXiaoliang Yang u64 cycletime;
173423ae3a78SXiaoliang Yang u64 cycletime_ext;
1735dcad856fSkernel test robot u32 num_entries;
173623ae3a78SXiaoliang Yang struct action_gate_entry entries[];
173723ae3a78SXiaoliang Yang };
173823ae3a78SXiaoliang Yang
173923ae3a78SXiaoliang Yang struct felix_stream_gate_entry {
174023ae3a78SXiaoliang Yang struct list_head list;
174123ae3a78SXiaoliang Yang refcount_t refcount;
174223ae3a78SXiaoliang Yang u32 index;
174323ae3a78SXiaoliang Yang };
17447d4b564dSXiaoliang Yang
vsc9959_stream_identify(struct flow_cls_offload * f,struct felix_stream * stream)17457d4b564dSXiaoliang Yang static int vsc9959_stream_identify(struct flow_cls_offload *f,
17467d4b564dSXiaoliang Yang struct felix_stream *stream)
17477d4b564dSXiaoliang Yang {
17487d4b564dSXiaoliang Yang struct flow_rule *rule = flow_cls_offload_flow_rule(f);
17497d4b564dSXiaoliang Yang struct flow_dissector *dissector = rule->match.dissector;
17507d4b564dSXiaoliang Yang
17517d4b564dSXiaoliang Yang if (dissector->used_keys &
17527d4b564dSXiaoliang Yang ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
17537d4b564dSXiaoliang Yang BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
17547d4b564dSXiaoliang Yang BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
17557d4b564dSXiaoliang Yang BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS)))
17567d4b564dSXiaoliang Yang return -EOPNOTSUPP;
17577d4b564dSXiaoliang Yang
17587d4b564dSXiaoliang Yang if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
17597d4b564dSXiaoliang Yang struct flow_match_eth_addrs match;
17607d4b564dSXiaoliang Yang
17617d4b564dSXiaoliang Yang flow_rule_match_eth_addrs(rule, &match);
17627d4b564dSXiaoliang Yang ether_addr_copy(stream->dmac, match.key->dst);
17637d4b564dSXiaoliang Yang if (!is_zero_ether_addr(match.mask->src))
17647d4b564dSXiaoliang Yang return -EOPNOTSUPP;
17657d4b564dSXiaoliang Yang } else {
17667d4b564dSXiaoliang Yang return -EOPNOTSUPP;
17677d4b564dSXiaoliang Yang }
17687d4b564dSXiaoliang Yang
17697d4b564dSXiaoliang Yang if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
17707d4b564dSXiaoliang Yang struct flow_match_vlan match;
17717d4b564dSXiaoliang Yang
17727d4b564dSXiaoliang Yang flow_rule_match_vlan(rule, &match);
17737d4b564dSXiaoliang Yang if (match.mask->vlan_priority)
17747d4b564dSXiaoliang Yang stream->prio = match.key->vlan_priority;
17757d4b564dSXiaoliang Yang else
17767d4b564dSXiaoliang Yang stream->prio = -1;
17777d4b564dSXiaoliang Yang
17787d4b564dSXiaoliang Yang if (!match.mask->vlan_id)
17797d4b564dSXiaoliang Yang return -EOPNOTSUPP;
17807d4b564dSXiaoliang Yang stream->vid = match.key->vlan_id;
17817d4b564dSXiaoliang Yang } else {
17827d4b564dSXiaoliang Yang return -EOPNOTSUPP;
17837d4b564dSXiaoliang Yang }
17847d4b564dSXiaoliang Yang
17857d4b564dSXiaoliang Yang stream->id = f->cookie;
17867d4b564dSXiaoliang Yang
17877d4b564dSXiaoliang Yang return 0;
17887d4b564dSXiaoliang Yang }
17897d4b564dSXiaoliang Yang
vsc9959_mact_stream_set(struct ocelot * ocelot,struct felix_stream * stream,struct netlink_ext_ack * extack)17907d4b564dSXiaoliang Yang static int vsc9959_mact_stream_set(struct ocelot *ocelot,
17917d4b564dSXiaoliang Yang struct felix_stream *stream,
17927d4b564dSXiaoliang Yang struct netlink_ext_ack *extack)
17937d4b564dSXiaoliang Yang {
17947d4b564dSXiaoliang Yang enum macaccess_entry_type type;
17957d4b564dSXiaoliang Yang int ret, sfid, ssid;
17967d4b564dSXiaoliang Yang u32 vid, dst_idx;
17977d4b564dSXiaoliang Yang u8 mac[ETH_ALEN];
17987d4b564dSXiaoliang Yang
17997d4b564dSXiaoliang Yang ether_addr_copy(mac, stream->dmac);
18007d4b564dSXiaoliang Yang vid = stream->vid;
18017d4b564dSXiaoliang Yang
18027d4b564dSXiaoliang Yang /* Stream identification desn't support to add a stream with non
18037d4b564dSXiaoliang Yang * existent MAC (The MAC entry has not been learned in MAC table).
18047d4b564dSXiaoliang Yang */
18057d4b564dSXiaoliang Yang ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type);
18067d4b564dSXiaoliang Yang if (ret) {
18077d4b564dSXiaoliang Yang if (extack)
18087d4b564dSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table");
18097d4b564dSXiaoliang Yang return -EOPNOTSUPP;
18107d4b564dSXiaoliang Yang }
18117d4b564dSXiaoliang Yang
18127d4b564dSXiaoliang Yang if ((stream->sfid_valid || stream->ssid_valid) &&
18137d4b564dSXiaoliang Yang type == ENTRYTYPE_NORMAL)
18147d4b564dSXiaoliang Yang type = ENTRYTYPE_LOCKED;
18157d4b564dSXiaoliang Yang
18167d4b564dSXiaoliang Yang sfid = stream->sfid_valid ? stream->sfid : -1;
18177d4b564dSXiaoliang Yang ssid = stream->ssid_valid ? stream->ssid : -1;
18187d4b564dSXiaoliang Yang
18197d4b564dSXiaoliang Yang ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type,
18207d4b564dSXiaoliang Yang sfid, ssid);
18217d4b564dSXiaoliang Yang
18227d4b564dSXiaoliang Yang return ret;
18237d4b564dSXiaoliang Yang }
18247d4b564dSXiaoliang Yang
18257d4b564dSXiaoliang Yang static struct felix_stream *
vsc9959_stream_table_lookup(struct list_head * stream_list,struct felix_stream * stream)18267d4b564dSXiaoliang Yang vsc9959_stream_table_lookup(struct list_head *stream_list,
18277d4b564dSXiaoliang Yang struct felix_stream *stream)
18287d4b564dSXiaoliang Yang {
18297d4b564dSXiaoliang Yang struct felix_stream *tmp;
18307d4b564dSXiaoliang Yang
18317d4b564dSXiaoliang Yang list_for_each_entry(tmp, stream_list, list)
18327d4b564dSXiaoliang Yang if (ether_addr_equal(tmp->dmac, stream->dmac) &&
18337d4b564dSXiaoliang Yang tmp->vid == stream->vid)
18347d4b564dSXiaoliang Yang return tmp;
18357d4b564dSXiaoliang Yang
18367d4b564dSXiaoliang Yang return NULL;
18377d4b564dSXiaoliang Yang }
18387d4b564dSXiaoliang Yang
vsc9959_stream_table_add(struct ocelot * ocelot,struct list_head * stream_list,struct felix_stream * stream,struct netlink_ext_ack * extack)18397d4b564dSXiaoliang Yang static int vsc9959_stream_table_add(struct ocelot *ocelot,
18407d4b564dSXiaoliang Yang struct list_head *stream_list,
18417d4b564dSXiaoliang Yang struct felix_stream *stream,
18427d4b564dSXiaoliang Yang struct netlink_ext_ack *extack)
18437d4b564dSXiaoliang Yang {
18447d4b564dSXiaoliang Yang struct felix_stream *stream_entry;
18457d4b564dSXiaoliang Yang int ret;
1846e44aecc7SYihao Han
18477d4b564dSXiaoliang Yang stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL);
18487d4b564dSXiaoliang Yang if (!stream_entry)
18497d4b564dSXiaoliang Yang return -ENOMEM;
1850a7e13edfSXiaoliang Yang
18517d4b564dSXiaoliang Yang if (!stream->dummy) {
18527d4b564dSXiaoliang Yang ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack);
18537d4b564dSXiaoliang Yang if (ret) {
18547d4b564dSXiaoliang Yang kfree(stream_entry);
18557d4b564dSXiaoliang Yang return ret;
1856a7e13edfSXiaoliang Yang }
18577d4b564dSXiaoliang Yang }
18587d4b564dSXiaoliang Yang
18597d4b564dSXiaoliang Yang list_add_tail(&stream_entry->list, stream_list);
18607d4b564dSXiaoliang Yang
18617d4b564dSXiaoliang Yang return 0;
18627d4b564dSXiaoliang Yang }
18637d4b564dSXiaoliang Yang
18647d4b564dSXiaoliang Yang static struct felix_stream *
vsc9959_stream_table_get(struct list_head * stream_list,unsigned long id)18657d4b564dSXiaoliang Yang vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id)
18667d4b564dSXiaoliang Yang {
18677d4b564dSXiaoliang Yang struct felix_stream *tmp;
18687d4b564dSXiaoliang Yang
18697d4b564dSXiaoliang Yang list_for_each_entry(tmp, stream_list, list)
18707d4b564dSXiaoliang Yang if (tmp->id == id)
18717d4b564dSXiaoliang Yang return tmp;
18727d4b564dSXiaoliang Yang
18737d4b564dSXiaoliang Yang return NULL;
18747d4b564dSXiaoliang Yang }
18757d4b564dSXiaoliang Yang
vsc9959_stream_table_del(struct ocelot * ocelot,struct felix_stream * stream)18767d4b564dSXiaoliang Yang static void vsc9959_stream_table_del(struct ocelot *ocelot,
18777d4b564dSXiaoliang Yang struct felix_stream *stream)
1878a7e13edfSXiaoliang Yang {
18797d4b564dSXiaoliang Yang if (!stream->dummy)
18807d4b564dSXiaoliang Yang vsc9959_mact_stream_set(ocelot, stream, NULL);
18817d4b564dSXiaoliang Yang
18827d4b564dSXiaoliang Yang list_del(&stream->list);
18837d4b564dSXiaoliang Yang kfree(stream);
18847d4b564dSXiaoliang Yang }
18857d4b564dSXiaoliang Yang
vsc9959_sfi_access_status(struct ocelot * ocelot)18867d4b564dSXiaoliang Yang static u32 vsc9959_sfi_access_status(struct ocelot *ocelot)
18877d4b564dSXiaoliang Yang {
18887d4b564dSXiaoliang Yang return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS);
18897d4b564dSXiaoliang Yang }
18907d4b564dSXiaoliang Yang
vsc9959_psfp_sfi_set(struct ocelot * ocelot,struct felix_stream_filter * sfi)18917d4b564dSXiaoliang Yang static int vsc9959_psfp_sfi_set(struct ocelot *ocelot,
18927d4b564dSXiaoliang Yang struct felix_stream_filter *sfi)
18937d4b564dSXiaoliang Yang {
18947d4b564dSXiaoliang Yang u32 val;
18957d4b564dSXiaoliang Yang
18967d4b564dSXiaoliang Yang if (sfi->index > VSC9959_PSFP_SFID_MAX)
18977d4b564dSXiaoliang Yang return -EINVAL;
18987d4b564dSXiaoliang Yang
18997d4b564dSXiaoliang Yang if (!sfi->enable) {
19007d4b564dSXiaoliang Yang ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
19017d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX);
19027d4b564dSXiaoliang Yang
19037d4b564dSXiaoliang Yang val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE);
19047d4b564dSXiaoliang Yang ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS);
19057d4b564dSXiaoliang Yang
19067d4b564dSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
19077d4b564dSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
19087d4b564dSXiaoliang Yang 10, 100000);
19097d4b564dSXiaoliang Yang }
19107d4b564dSXiaoliang Yang
19117d4b564dSXiaoliang Yang if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX ||
19127d4b564dSXiaoliang Yang sfi->fmid > VSC9959_PSFP_POLICER_MAX)
19137d4b564dSXiaoliang Yang return -EINVAL;
19147d4b564dSXiaoliang Yang
19157d4b564dSXiaoliang Yang ocelot_write(ocelot,
19167d4b564dSXiaoliang Yang (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) |
19177d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) |
19187d4b564dSXiaoliang Yang (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) |
19197d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) |
19207d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
19217d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX);
19227d4b564dSXiaoliang Yang
19237d4b564dSXiaoliang Yang ocelot_write(ocelot,
19247d4b564dSXiaoliang Yang (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) |
19257d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) |
19267d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) |
19277d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
19287d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS);
19297d4b564dSXiaoliang Yang
19307d4b564dSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
19317d4b564dSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
19327d4b564dSXiaoliang Yang 10, 100000);
19337d4b564dSXiaoliang Yang }
1934a7e13edfSXiaoliang Yang
vsc9959_psfp_sfidmask_set(struct ocelot * ocelot,u32 sfid,int ports)19357d4b564dSXiaoliang Yang static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports)
1936a7e13edfSXiaoliang Yang {
1937a7e13edfSXiaoliang Yang u32 val;
1938a7e13edfSXiaoliang Yang
1939a7e13edfSXiaoliang Yang ocelot_rmw(ocelot,
1940a7e13edfSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid),
1941a7e13edfSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX_M,
1942a7e13edfSXiaoliang Yang ANA_TABLES_SFIDTIDX);
1943a7e13edfSXiaoliang Yang
1944a7e13edfSXiaoliang Yang ocelot_write(ocelot,
1945a7e13edfSXiaoliang Yang ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) |
1946a7e13edfSXiaoliang Yang ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA,
1947a7e13edfSXiaoliang Yang ANA_TABLES_SFID_MASK);
1948a7e13edfSXiaoliang Yang
1949a7e13edfSXiaoliang Yang ocelot_rmw(ocelot,
1950a7e13edfSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1951a7e13edfSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M,
1952a7e13edfSXiaoliang Yang ANA_TABLES_SFIDACCESS);
1953a7e13edfSXiaoliang Yang
1954a7e13edfSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1955a7e13edfSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1956a7e13edfSXiaoliang Yang 10, 100000);
1957a7e13edfSXiaoliang Yang }
1958a7e13edfSXiaoliang Yang
vsc9959_psfp_sfi_list_add(struct ocelot * ocelot,struct felix_stream_filter * sfi,struct list_head * pos)1959a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot,
1960a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi,
1961a7e13edfSXiaoliang Yang struct list_head *pos)
1962a7e13edfSXiaoliang Yang {
19637d4b564dSXiaoliang Yang struct felix_stream_filter *sfi_entry;
19647d4b564dSXiaoliang Yang int ret;
1965e44aecc7SYihao Han
19667d4b564dSXiaoliang Yang sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL);
19677d4b564dSXiaoliang Yang if (!sfi_entry)
19687d4b564dSXiaoliang Yang return -ENOMEM;
19697d4b564dSXiaoliang Yang
19707d4b564dSXiaoliang Yang refcount_set(&sfi_entry->refcount, 1);
19717d4b564dSXiaoliang Yang
19727d4b564dSXiaoliang Yang ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry);
19737d4b564dSXiaoliang Yang if (ret) {
19747d4b564dSXiaoliang Yang kfree(sfi_entry);
19757d4b564dSXiaoliang Yang return ret;
19767d4b564dSXiaoliang Yang }
1977a7e13edfSXiaoliang Yang
1978a7e13edfSXiaoliang Yang vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask);
1979a7e13edfSXiaoliang Yang
19807d4b564dSXiaoliang Yang list_add(&sfi_entry->list, pos);
19817d4b564dSXiaoliang Yang
19827d4b564dSXiaoliang Yang return 0;
19837d4b564dSXiaoliang Yang }
1984a7e13edfSXiaoliang Yang
vsc9959_psfp_sfi_table_add(struct ocelot * ocelot,struct felix_stream_filter * sfi)1985a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot,
1986a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi)
1987a7e13edfSXiaoliang Yang {
1988a7e13edfSXiaoliang Yang struct list_head *pos, *q, *last;
1989a7e13edfSXiaoliang Yang struct felix_stream_filter *tmp;
1990a7e13edfSXiaoliang Yang struct ocelot_psfp_list *psfp;
1991a7e13edfSXiaoliang Yang u32 insert = 0;
1992a7e13edfSXiaoliang Yang
1993a7e13edfSXiaoliang Yang psfp = &ocelot->psfp;
1994a7e13edfSXiaoliang Yang last = &psfp->sfi_list;
1995a7e13edfSXiaoliang Yang
1996a7e13edfSXiaoliang Yang list_for_each_safe(pos, q, &psfp->sfi_list) {
1997a7e13edfSXiaoliang Yang tmp = list_entry(pos, struct felix_stream_filter, list);
1998a7e13edfSXiaoliang Yang if (sfi->sg_valid == tmp->sg_valid &&
1999a7e13edfSXiaoliang Yang sfi->fm_valid == tmp->fm_valid &&
2000a7e13edfSXiaoliang Yang sfi->portmask == tmp->portmask &&
2001a7e13edfSXiaoliang Yang tmp->sgid == sfi->sgid &&
2002a7e13edfSXiaoliang Yang tmp->fmid == sfi->fmid) {
2003a7e13edfSXiaoliang Yang sfi->index = tmp->index;
2004a7e13edfSXiaoliang Yang refcount_inc(&tmp->refcount);
2005a7e13edfSXiaoliang Yang return 0;
2006a7e13edfSXiaoliang Yang }
2007a7e13edfSXiaoliang Yang /* Make sure that the index is increasing in order. */
2008a7e13edfSXiaoliang Yang if (tmp->index == insert) {
2009a7e13edfSXiaoliang Yang last = pos;
2010a7e13edfSXiaoliang Yang insert++;
2011a7e13edfSXiaoliang Yang }
2012a7e13edfSXiaoliang Yang }
2013a7e13edfSXiaoliang Yang sfi->index = insert;
2014a7e13edfSXiaoliang Yang
2015a7e13edfSXiaoliang Yang return vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
2016a7e13edfSXiaoliang Yang }
2017a7e13edfSXiaoliang Yang
vsc9959_psfp_sfi_table_add2(struct ocelot * ocelot,struct felix_stream_filter * sfi,struct felix_stream_filter * sfi2)2018a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot,
2019a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi,
2020a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi2)
2021a7e13edfSXiaoliang Yang {
2022a7e13edfSXiaoliang Yang struct felix_stream_filter *tmp;
2023a7e13edfSXiaoliang Yang struct list_head *pos, *q, *last;
2024a7e13edfSXiaoliang Yang struct ocelot_psfp_list *psfp;
2025a7e13edfSXiaoliang Yang u32 insert = 0;
2026a7e13edfSXiaoliang Yang int ret;
2027a7e13edfSXiaoliang Yang
2028a7e13edfSXiaoliang Yang psfp = &ocelot->psfp;
2029a7e13edfSXiaoliang Yang last = &psfp->sfi_list;
2030a7e13edfSXiaoliang Yang
2031a7e13edfSXiaoliang Yang list_for_each_safe(pos, q, &psfp->sfi_list) {
2032a7e13edfSXiaoliang Yang tmp = list_entry(pos, struct felix_stream_filter, list);
2033a7e13edfSXiaoliang Yang /* Make sure that the index is increasing in order. */
2034a7e13edfSXiaoliang Yang if (tmp->index >= insert + 2)
2035a7e13edfSXiaoliang Yang break;
2036a7e13edfSXiaoliang Yang
2037a7e13edfSXiaoliang Yang insert = tmp->index + 1;
2038a7e13edfSXiaoliang Yang last = pos;
2039a7e13edfSXiaoliang Yang }
2040a7e13edfSXiaoliang Yang sfi->index = insert;
2041a7e13edfSXiaoliang Yang
2042a7e13edfSXiaoliang Yang ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
2043a7e13edfSXiaoliang Yang if (ret)
2044a7e13edfSXiaoliang Yang return ret;
2045a7e13edfSXiaoliang Yang
2046a7e13edfSXiaoliang Yang sfi2->index = insert + 1;
2047a7e13edfSXiaoliang Yang
2048a7e13edfSXiaoliang Yang return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next);
2049a7e13edfSXiaoliang Yang }
205023ae3a78SXiaoliang Yang
205123ae3a78SXiaoliang Yang static struct felix_stream_filter *
vsc9959_psfp_sfi_table_get(struct list_head * sfi_list,u32 index)205223ae3a78SXiaoliang Yang vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index)
205323ae3a78SXiaoliang Yang {
205423ae3a78SXiaoliang Yang struct felix_stream_filter *tmp;
205523ae3a78SXiaoliang Yang
205623ae3a78SXiaoliang Yang list_for_each_entry(tmp, sfi_list, list)
205723ae3a78SXiaoliang Yang if (tmp->index == index)
205823ae3a78SXiaoliang Yang return tmp;
205923ae3a78SXiaoliang Yang
206023ae3a78SXiaoliang Yang return NULL;
206123ae3a78SXiaoliang Yang }
20627d4b564dSXiaoliang Yang
vsc9959_psfp_sfi_table_del(struct ocelot * ocelot,u32 index)20637d4b564dSXiaoliang Yang static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index)
20647d4b564dSXiaoliang Yang {
20657d4b564dSXiaoliang Yang struct felix_stream_filter *tmp, *n;
20667d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp;
20677d4b564dSXiaoliang Yang u8 z;
20687d4b564dSXiaoliang Yang
20697d4b564dSXiaoliang Yang psfp = &ocelot->psfp;
20707d4b564dSXiaoliang Yang
20717d4b564dSXiaoliang Yang list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list)
20727d4b564dSXiaoliang Yang if (tmp->index == index) {
20737d4b564dSXiaoliang Yang z = refcount_dec_and_test(&tmp->refcount);
20747d4b564dSXiaoliang Yang if (z) {
20757d4b564dSXiaoliang Yang tmp->enable = 0;
20767d4b564dSXiaoliang Yang vsc9959_psfp_sfi_set(ocelot, tmp);
20777d4b564dSXiaoliang Yang list_del(&tmp->list);
20787d4b564dSXiaoliang Yang kfree(tmp);
20797d4b564dSXiaoliang Yang }
20807d4b564dSXiaoliang Yang break;
20817d4b564dSXiaoliang Yang }
20827d4b564dSXiaoliang Yang }
208323ae3a78SXiaoliang Yang
vsc9959_psfp_parse_gate(const struct flow_action_entry * entry,struct felix_stream_gate * sgi)208423ae3a78SXiaoliang Yang static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry,
208523ae3a78SXiaoliang Yang struct felix_stream_gate *sgi)
20865a995900SBaowen Zheng {
208723ae3a78SXiaoliang Yang sgi->index = entry->hw_index;
208823ae3a78SXiaoliang Yang sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1;
208923ae3a78SXiaoliang Yang sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0;
209023ae3a78SXiaoliang Yang sgi->basetime = entry->gate.basetime;
209123ae3a78SXiaoliang Yang sgi->cycletime = entry->gate.cycletime;
209223ae3a78SXiaoliang Yang sgi->num_entries = entry->gate.num_entries;
209323ae3a78SXiaoliang Yang sgi->enable = 1;
209423ae3a78SXiaoliang Yang
209523ae3a78SXiaoliang Yang memcpy(sgi->entries, entry->gate.entries,
209623ae3a78SXiaoliang Yang entry->gate.num_entries * sizeof(struct action_gate_entry));
209723ae3a78SXiaoliang Yang }
209823ae3a78SXiaoliang Yang
vsc9959_sgi_cfg_status(struct ocelot * ocelot)209923ae3a78SXiaoliang Yang static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot)
210023ae3a78SXiaoliang Yang {
210123ae3a78SXiaoliang Yang return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL);
210223ae3a78SXiaoliang Yang }
210323ae3a78SXiaoliang Yang
vsc9959_psfp_sgi_set(struct ocelot * ocelot,struct felix_stream_gate * sgi)210423ae3a78SXiaoliang Yang static int vsc9959_psfp_sgi_set(struct ocelot *ocelot,
210523ae3a78SXiaoliang Yang struct felix_stream_gate *sgi)
210623ae3a78SXiaoliang Yang {
210723ae3a78SXiaoliang Yang struct action_gate_entry *e;
210823ae3a78SXiaoliang Yang struct timespec64 base_ts;
210923ae3a78SXiaoliang Yang u32 interval_sum = 0;
211023ae3a78SXiaoliang Yang u32 val;
211123ae3a78SXiaoliang Yang int i;
211223ae3a78SXiaoliang Yang
211323ae3a78SXiaoliang Yang if (sgi->index > VSC9959_PSFP_GATE_ID_MAX)
211423ae3a78SXiaoliang Yang return -EINVAL;
211523ae3a78SXiaoliang Yang
211623ae3a78SXiaoliang Yang ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index),
211723ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL);
211823ae3a78SXiaoliang Yang
211923ae3a78SXiaoliang Yang if (!sgi->enable) {
212023ae3a78SXiaoliang Yang ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE,
212123ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
212223ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_GATE_ENABLE,
212323ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3);
212423ae3a78SXiaoliang Yang
212523ae3a78SXiaoliang Yang return 0;
212623ae3a78SXiaoliang Yang }
212723ae3a78SXiaoliang Yang
212823ae3a78SXiaoliang Yang if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN ||
212923ae3a78SXiaoliang Yang sgi->cycletime > NSEC_PER_SEC)
213023ae3a78SXiaoliang Yang return -EINVAL;
213123ae3a78SXiaoliang Yang
213223ae3a78SXiaoliang Yang if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM)
213323ae3a78SXiaoliang Yang return -EINVAL;
213423ae3a78SXiaoliang Yang
213523ae3a78SXiaoliang Yang vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts);
213623ae3a78SXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1);
213723ae3a78SXiaoliang Yang val = lower_32_bits(base_ts.tv_sec);
213823ae3a78SXiaoliang Yang ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2);
213923ae3a78SXiaoliang Yang
214023ae3a78SXiaoliang Yang val = upper_32_bits(base_ts.tv_sec);
214123ae3a78SXiaoliang Yang ocelot_write(ocelot,
214223ae3a78SXiaoliang Yang (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) |
214323ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) |
214423ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_GATE_ENABLE |
214523ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) |
214623ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
214723ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val),
214823ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3);
214923ae3a78SXiaoliang Yang
215023ae3a78SXiaoliang Yang ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4);
215123ae3a78SXiaoliang Yang
215223ae3a78SXiaoliang Yang e = sgi->entries;
215323ae3a78SXiaoliang Yang for (i = 0; i < sgi->num_entries; i++) {
215423ae3a78SXiaoliang Yang u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8);
215523ae3a78SXiaoliang Yang
215623ae3a78SXiaoliang Yang ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) |
215723ae3a78SXiaoliang Yang (e[i].gate_state ?
215823ae3a78SXiaoliang Yang ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0),
215923ae3a78SXiaoliang Yang ANA_SG_GCL_GS_CONFIG, i);
216023ae3a78SXiaoliang Yang
216123ae3a78SXiaoliang Yang interval_sum += e[i].interval;
216223ae3a78SXiaoliang Yang ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i);
216323ae3a78SXiaoliang Yang }
216423ae3a78SXiaoliang Yang
216523ae3a78SXiaoliang Yang ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
216623ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
216723ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL);
216823ae3a78SXiaoliang Yang
216923ae3a78SXiaoliang Yang return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val,
217023ae3a78SXiaoliang Yang (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)),
217123ae3a78SXiaoliang Yang 10, 100000);
217223ae3a78SXiaoliang Yang }
217323ae3a78SXiaoliang Yang
vsc9959_psfp_sgi_table_add(struct ocelot * ocelot,struct felix_stream_gate * sgi)217423ae3a78SXiaoliang Yang static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot,
217523ae3a78SXiaoliang Yang struct felix_stream_gate *sgi)
217623ae3a78SXiaoliang Yang {
217723ae3a78SXiaoliang Yang struct felix_stream_gate_entry *tmp;
217823ae3a78SXiaoliang Yang struct ocelot_psfp_list *psfp;
217923ae3a78SXiaoliang Yang int ret;
218023ae3a78SXiaoliang Yang
218123ae3a78SXiaoliang Yang psfp = &ocelot->psfp;
218223ae3a78SXiaoliang Yang
218323ae3a78SXiaoliang Yang list_for_each_entry(tmp, &psfp->sgi_list, list)
218423ae3a78SXiaoliang Yang if (tmp->index == sgi->index) {
218523ae3a78SXiaoliang Yang refcount_inc(&tmp->refcount);
218623ae3a78SXiaoliang Yang return 0;
218723ae3a78SXiaoliang Yang }
218823ae3a78SXiaoliang Yang
218923ae3a78SXiaoliang Yang tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
219023ae3a78SXiaoliang Yang if (!tmp)
219123ae3a78SXiaoliang Yang return -ENOMEM;
219223ae3a78SXiaoliang Yang
219323ae3a78SXiaoliang Yang ret = vsc9959_psfp_sgi_set(ocelot, sgi);
219423ae3a78SXiaoliang Yang if (ret) {
219523ae3a78SXiaoliang Yang kfree(tmp);
219623ae3a78SXiaoliang Yang return ret;
219723ae3a78SXiaoliang Yang }
219823ae3a78SXiaoliang Yang
219923ae3a78SXiaoliang Yang tmp->index = sgi->index;
220023ae3a78SXiaoliang Yang refcount_set(&tmp->refcount, 1);
220123ae3a78SXiaoliang Yang list_add_tail(&tmp->list, &psfp->sgi_list);
220223ae3a78SXiaoliang Yang
220323ae3a78SXiaoliang Yang return 0;
220423ae3a78SXiaoliang Yang }
220523ae3a78SXiaoliang Yang
vsc9959_psfp_sgi_table_del(struct ocelot * ocelot,u32 index)220623ae3a78SXiaoliang Yang static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot,
220723ae3a78SXiaoliang Yang u32 index)
220823ae3a78SXiaoliang Yang {
220923ae3a78SXiaoliang Yang struct felix_stream_gate_entry *tmp, *n;
221023ae3a78SXiaoliang Yang struct felix_stream_gate sgi = {0};
221123ae3a78SXiaoliang Yang struct ocelot_psfp_list *psfp;
221223ae3a78SXiaoliang Yang u8 z;
221323ae3a78SXiaoliang Yang
221423ae3a78SXiaoliang Yang psfp = &ocelot->psfp;
221523ae3a78SXiaoliang Yang
221623ae3a78SXiaoliang Yang list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list)
221723ae3a78SXiaoliang Yang if (tmp->index == index) {
221823ae3a78SXiaoliang Yang z = refcount_dec_and_test(&tmp->refcount);
221923ae3a78SXiaoliang Yang if (z) {
222023ae3a78SXiaoliang Yang sgi.index = index;
222123ae3a78SXiaoliang Yang sgi.enable = 0;
222223ae3a78SXiaoliang Yang vsc9959_psfp_sgi_set(ocelot, &sgi);
222323ae3a78SXiaoliang Yang list_del(&tmp->list);
222423ae3a78SXiaoliang Yang kfree(tmp);
222523ae3a78SXiaoliang Yang }
222623ae3a78SXiaoliang Yang break;
222723ae3a78SXiaoliang Yang }
222823ae3a78SXiaoliang Yang }
2229a7e13edfSXiaoliang Yang
vsc9959_psfp_filter_add(struct ocelot * ocelot,int port,struct flow_cls_offload * f)22307d4b564dSXiaoliang Yang static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port,
22317d4b564dSXiaoliang Yang struct flow_cls_offload *f)
22327d4b564dSXiaoliang Yang {
2233a7e13edfSXiaoliang Yang struct netlink_ext_ack *extack = f->common.extack;
22347d4b564dSXiaoliang Yang struct felix_stream_filter old_sfi, *sfi_entry;
22357d4b564dSXiaoliang Yang struct felix_stream_filter sfi = {0};
22367d4b564dSXiaoliang Yang const struct flow_action_entry *a;
22377d4b564dSXiaoliang Yang struct felix_stream *stream_entry;
223823ae3a78SXiaoliang Yang struct felix_stream stream = {0};
22397d4b564dSXiaoliang Yang struct felix_stream_gate *sgi;
224076c13edeSXiaoliang Yang struct ocelot_psfp_list *psfp;
224123ae3a78SXiaoliang Yang struct ocelot_policer pol;
224276c13edeSXiaoliang Yang int ret, i, size;
224376c13edeSXiaoliang Yang u64 rate, burst;
22447d4b564dSXiaoliang Yang u32 index;
22457d4b564dSXiaoliang Yang
22467d4b564dSXiaoliang Yang psfp = &ocelot->psfp;
22477d4b564dSXiaoliang Yang
22487d4b564dSXiaoliang Yang ret = vsc9959_stream_identify(f, &stream);
22497d4b564dSXiaoliang Yang if (ret) {
22507d4b564dSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC");
22517d4b564dSXiaoliang Yang return ret;
22527d4b564dSXiaoliang Yang }
225325027c84SVladimir Oltean
225425027c84SVladimir Oltean mutex_lock(&psfp->lock);
22557d4b564dSXiaoliang Yang
22567d4b564dSXiaoliang Yang flow_action_for_each(i, a, &f->rule->action) {
22577d4b564dSXiaoliang Yang switch (a->id) {
225823ae3a78SXiaoliang Yang case FLOW_ACTION_GATE:
225923ae3a78SXiaoliang Yang size = struct_size(sgi, entries, a->gate.num_entries);
2260866b7a27SZheng Yongjun sgi = kzalloc(size, GFP_KERNEL);
2261866b7a27SZheng Yongjun if (!sgi) {
2262866b7a27SZheng Yongjun ret = -ENOMEM;
2263866b7a27SZheng Yongjun goto err;
226423ae3a78SXiaoliang Yang }
226523ae3a78SXiaoliang Yang vsc9959_psfp_parse_gate(a, sgi);
226623ae3a78SXiaoliang Yang ret = vsc9959_psfp_sgi_table_add(ocelot, sgi);
226723ae3a78SXiaoliang Yang if (ret) {
226876c13edeSXiaoliang Yang kfree(sgi);
226923ae3a78SXiaoliang Yang goto err;
227023ae3a78SXiaoliang Yang }
227123ae3a78SXiaoliang Yang sfi.sg_valid = 1;
227223ae3a78SXiaoliang Yang sfi.sgid = sgi->index;
227323ae3a78SXiaoliang Yang kfree(sgi);
22747d4b564dSXiaoliang Yang break;
22755a995900SBaowen Zheng case FLOW_ACTION_POLICE:
227676c13edeSXiaoliang Yang index = a->hw_index + VSC9959_PSFP_POLICER_BASE;
227776c13edeSXiaoliang Yang if (index > VSC9959_PSFP_POLICER_MAX) {
227876c13edeSXiaoliang Yang ret = -EINVAL;
227976c13edeSXiaoliang Yang goto err;
228076c13edeSXiaoliang Yang }
228176c13edeSXiaoliang Yang
228276c13edeSXiaoliang Yang rate = a->police.rate_bytes_ps;
228376c13edeSXiaoliang Yang burst = rate * PSCHED_NS2TICKS(a->police.burst);
228476c13edeSXiaoliang Yang pol = (struct ocelot_policer) {
228576c13edeSXiaoliang Yang .burst = div_u64(burst, PSCHED_TICKS_PER_SEC),
228676c13edeSXiaoliang Yang .rate = div_u64(rate, 1000) * 8,
228776c13edeSXiaoliang Yang };
228876c13edeSXiaoliang Yang ret = ocelot_vcap_policer_add(ocelot, index, &pol);
228976c13edeSXiaoliang Yang if (ret)
229076c13edeSXiaoliang Yang goto err;
229176c13edeSXiaoliang Yang
229276c13edeSXiaoliang Yang sfi.fm_valid = 1;
229376c13edeSXiaoliang Yang sfi.fmid = index;
229476c13edeSXiaoliang Yang sfi.maxsdu = a->police.mtu;
22957d4b564dSXiaoliang Yang break;
229625027c84SVladimir Oltean default:
22977d4b564dSXiaoliang Yang mutex_unlock(&psfp->lock);
22987d4b564dSXiaoliang Yang return -EOPNOTSUPP;
22997d4b564dSXiaoliang Yang }
23007d4b564dSXiaoliang Yang }
2301a7e13edfSXiaoliang Yang
2302a7e13edfSXiaoliang Yang stream.ports = BIT(port);
23037d4b564dSXiaoliang Yang stream.port = port;
2304a7e13edfSXiaoliang Yang
23057d4b564dSXiaoliang Yang sfi.portmask = stream.ports;
23067d4b564dSXiaoliang Yang sfi.prio_valid = (stream.prio < 0 ? 0 : 1);
23077d4b564dSXiaoliang Yang sfi.prio = (sfi.prio_valid ? stream.prio : 0);
23087d4b564dSXiaoliang Yang sfi.enable = 1;
2309a7e13edfSXiaoliang Yang
2310a7e13edfSXiaoliang Yang /* Check if stream is set. */
2311a7e13edfSXiaoliang Yang stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream);
2312a7e13edfSXiaoliang Yang if (stream_entry) {
2313a7e13edfSXiaoliang Yang if (stream_entry->ports & BIT(port)) {
2314a7e13edfSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack,
2315a7e13edfSXiaoliang Yang "The stream is added on this port");
2316a7e13edfSXiaoliang Yang ret = -EEXIST;
2317a7e13edfSXiaoliang Yang goto err;
2318a7e13edfSXiaoliang Yang }
2319a7e13edfSXiaoliang Yang
2320a7e13edfSXiaoliang Yang if (stream_entry->ports != BIT(stream_entry->port)) {
2321a7e13edfSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack,
2322a7e13edfSXiaoliang Yang "The stream is added on two ports");
2323a7e13edfSXiaoliang Yang ret = -EEXIST;
2324a7e13edfSXiaoliang Yang goto err;
2325a7e13edfSXiaoliang Yang }
2326a7e13edfSXiaoliang Yang
2327a7e13edfSXiaoliang Yang stream_entry->ports |= BIT(port);
2328a7e13edfSXiaoliang Yang stream.ports = stream_entry->ports;
2329a7e13edfSXiaoliang Yang
2330a7e13edfSXiaoliang Yang sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list,
2331a7e13edfSXiaoliang Yang stream_entry->sfid);
2332a7e13edfSXiaoliang Yang memcpy(&old_sfi, sfi_entry, sizeof(old_sfi));
2333a7e13edfSXiaoliang Yang
2334a7e13edfSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid);
2335a7e13edfSXiaoliang Yang
2336a7e13edfSXiaoliang Yang old_sfi.portmask = stream_entry->ports;
2337a7e13edfSXiaoliang Yang sfi.portmask = stream.ports;
2338a7e13edfSXiaoliang Yang
2339a7e13edfSXiaoliang Yang if (stream_entry->port > port) {
2340a7e13edfSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi,
2341a7e13edfSXiaoliang Yang &old_sfi);
2342a7e13edfSXiaoliang Yang stream_entry->dummy = true;
2343a7e13edfSXiaoliang Yang } else {
2344a7e13edfSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi,
2345a7e13edfSXiaoliang Yang &sfi);
2346a7e13edfSXiaoliang Yang stream.dummy = true;
2347a7e13edfSXiaoliang Yang }
2348a7e13edfSXiaoliang Yang if (ret)
2349a7e13edfSXiaoliang Yang goto err;
2350a7e13edfSXiaoliang Yang
2351a7e13edfSXiaoliang Yang stream_entry->sfid = old_sfi.index;
23527d4b564dSXiaoliang Yang } else {
23537d4b564dSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi);
235423ae3a78SXiaoliang Yang if (ret)
2355a7e13edfSXiaoliang Yang goto err;
23567d4b564dSXiaoliang Yang }
23577d4b564dSXiaoliang Yang
23587d4b564dSXiaoliang Yang stream.sfid = sfi.index;
23597d4b564dSXiaoliang Yang stream.sfid_valid = 1;
23607d4b564dSXiaoliang Yang ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list,
236123ae3a78SXiaoliang Yang &stream, extack);
23627d4b564dSXiaoliang Yang if (ret) {
236323ae3a78SXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream.sfid);
236423ae3a78SXiaoliang Yang goto err;
236523ae3a78SXiaoliang Yang }
236625027c84SVladimir Oltean
236725027c84SVladimir Oltean mutex_unlock(&psfp->lock);
236823ae3a78SXiaoliang Yang
236923ae3a78SXiaoliang Yang return 0;
237023ae3a78SXiaoliang Yang
237123ae3a78SXiaoliang Yang err:
237223ae3a78SXiaoliang Yang if (sfi.sg_valid)
23737d4b564dSXiaoliang Yang vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid);
237476c13edeSXiaoliang Yang
237576c13edeSXiaoliang Yang if (sfi.fm_valid)
237676c13edeSXiaoliang Yang ocelot_vcap_policer_del(ocelot, sfi.fmid);
237725027c84SVladimir Oltean
237825027c84SVladimir Oltean mutex_unlock(&psfp->lock);
23797d4b564dSXiaoliang Yang
23807d4b564dSXiaoliang Yang return ret;
23817d4b564dSXiaoliang Yang }
23827d4b564dSXiaoliang Yang
vsc9959_psfp_filter_del(struct ocelot * ocelot,struct flow_cls_offload * f)23837d4b564dSXiaoliang Yang static int vsc9959_psfp_filter_del(struct ocelot *ocelot,
23847d4b564dSXiaoliang Yang struct flow_cls_offload *f)
2385a7e13edfSXiaoliang Yang {
238625027c84SVladimir Oltean struct felix_stream *stream, tmp, *stream_entry;
238723ae3a78SXiaoliang Yang struct ocelot_psfp_list *psfp = &ocelot->psfp;
23887d4b564dSXiaoliang Yang static struct felix_stream_filter *sfi;
238925027c84SVladimir Oltean
23907d4b564dSXiaoliang Yang mutex_lock(&psfp->lock);
23917d4b564dSXiaoliang Yang
239225027c84SVladimir Oltean stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
239325027c84SVladimir Oltean if (!stream) {
23947d4b564dSXiaoliang Yang mutex_unlock(&psfp->lock);
239525027c84SVladimir Oltean return -ENOMEM;
23967d4b564dSXiaoliang Yang }
239723ae3a78SXiaoliang Yang
239825027c84SVladimir Oltean sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid);
239925027c84SVladimir Oltean if (!sfi) {
240023ae3a78SXiaoliang Yang mutex_unlock(&psfp->lock);
240125027c84SVladimir Oltean return -ENOMEM;
240223ae3a78SXiaoliang Yang }
240323ae3a78SXiaoliang Yang
240423ae3a78SXiaoliang Yang if (sfi->sg_valid)
240523ae3a78SXiaoliang Yang vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid);
240676c13edeSXiaoliang Yang
240776c13edeSXiaoliang Yang if (sfi->fm_valid)
240876c13edeSXiaoliang Yang ocelot_vcap_policer_del(ocelot, sfi->fmid);
24097d4b564dSXiaoliang Yang
24107d4b564dSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream->sfid);
2411a7e13edfSXiaoliang Yang
2412a7e13edfSXiaoliang Yang memcpy(&tmp, stream, sizeof(tmp));
24137d4b564dSXiaoliang Yang
24147d4b564dSXiaoliang Yang stream->sfid_valid = 0;
24157d4b564dSXiaoliang Yang vsc9959_stream_table_del(ocelot, stream);
2416a7e13edfSXiaoliang Yang
2417a7e13edfSXiaoliang Yang stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp);
2418a7e13edfSXiaoliang Yang if (stream_entry) {
2419a7e13edfSXiaoliang Yang stream_entry->ports = BIT(stream_entry->port);
2420a7e13edfSXiaoliang Yang if (stream_entry->dummy) {
2421a7e13edfSXiaoliang Yang stream_entry->dummy = false;
2422a7e13edfSXiaoliang Yang vsc9959_mact_stream_set(ocelot, stream_entry, NULL);
2423a7e13edfSXiaoliang Yang }
2424a7e13edfSXiaoliang Yang vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid,
2425a7e13edfSXiaoliang Yang stream_entry->ports);
2426a7e13edfSXiaoliang Yang }
242725027c84SVladimir Oltean
242825027c84SVladimir Oltean mutex_unlock(&psfp->lock);
24297d4b564dSXiaoliang Yang
24307d4b564dSXiaoliang Yang return 0;
24317d4b564dSXiaoliang Yang }
243225027c84SVladimir Oltean
vsc9959_update_sfid_stats(struct ocelot * ocelot,struct felix_stream_filter * sfi)243325027c84SVladimir Oltean static void vsc9959_update_sfid_stats(struct ocelot *ocelot,
243425027c84SVladimir Oltean struct felix_stream_filter *sfi)
243525027c84SVladimir Oltean {
243625027c84SVladimir Oltean struct felix_stream_filter_counters *s = &sfi->stats;
243725027c84SVladimir Oltean u32 match, not_pass_gate, not_pass_sdu, red;
243825027c84SVladimir Oltean u32 sfid = sfi->index;
243925027c84SVladimir Oltean
244025027c84SVladimir Oltean lockdep_assert_held(&ocelot->stat_view_lock);
244125027c84SVladimir Oltean
244225027c84SVladimir Oltean ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(sfid),
244325027c84SVladimir Oltean SYS_STAT_CFG_STAT_VIEW_M,
244425027c84SVladimir Oltean SYS_STAT_CFG);
244525027c84SVladimir Oltean
244625027c84SVladimir Oltean match = ocelot_read(ocelot, SYS_COUNT_SF_MATCHING_FRAMES);
244725027c84SVladimir Oltean not_pass_gate = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_FRAMES);
244825027c84SVladimir Oltean not_pass_sdu = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_SDU);
244925027c84SVladimir Oltean red = ocelot_read(ocelot, SYS_COUNT_SF_RED_FRAMES);
245025027c84SVladimir Oltean
245125027c84SVladimir Oltean /* Clear the PSFP counter. */
245225027c84SVladimir Oltean ocelot_write(ocelot,
245325027c84SVladimir Oltean SYS_STAT_CFG_STAT_VIEW(sfid) |
245425027c84SVladimir Oltean SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10),
245525027c84SVladimir Oltean SYS_STAT_CFG);
245625027c84SVladimir Oltean
245725027c84SVladimir Oltean s->match += match;
245825027c84SVladimir Oltean s->not_pass_gate += not_pass_gate;
245925027c84SVladimir Oltean s->not_pass_sdu += not_pass_sdu;
246025027c84SVladimir Oltean s->red += red;
246125027c84SVladimir Oltean }
246225027c84SVladimir Oltean
246325027c84SVladimir Oltean /* Caller must hold &ocelot->stat_view_lock */
vsc9959_update_stats(struct ocelot * ocelot)246425027c84SVladimir Oltean static void vsc9959_update_stats(struct ocelot *ocelot)
246525027c84SVladimir Oltean {
246625027c84SVladimir Oltean struct ocelot_psfp_list *psfp = &ocelot->psfp;
246725027c84SVladimir Oltean struct felix_stream_filter *sfi;
246825027c84SVladimir Oltean
246925027c84SVladimir Oltean mutex_lock(&psfp->lock);
247025027c84SVladimir Oltean
247125027c84SVladimir Oltean list_for_each_entry(sfi, &psfp->sfi_list, list)
247225027c84SVladimir Oltean vsc9959_update_sfid_stats(ocelot, sfi);
247325027c84SVladimir Oltean
247425027c84SVladimir Oltean mutex_unlock(&psfp->lock);
247525027c84SVladimir Oltean }
24767d4b564dSXiaoliang Yang
vsc9959_psfp_stats_get(struct ocelot * ocelot,struct flow_cls_offload * f,struct flow_stats * stats)24777d4b564dSXiaoliang Yang static int vsc9959_psfp_stats_get(struct ocelot *ocelot,
24787d4b564dSXiaoliang Yang struct flow_cls_offload *f,
24797d4b564dSXiaoliang Yang struct flow_stats *stats)
248025027c84SVladimir Oltean {
248125027c84SVladimir Oltean struct ocelot_psfp_list *psfp = &ocelot->psfp;
248225027c84SVladimir Oltean struct felix_stream_filter_counters *s;
24837d4b564dSXiaoliang Yang static struct felix_stream_filter *sfi;
24847d4b564dSXiaoliang Yang struct felix_stream *stream;
24857d4b564dSXiaoliang Yang
24867d4b564dSXiaoliang Yang stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
24877d4b564dSXiaoliang Yang if (!stream)
24887d4b564dSXiaoliang Yang return -ENOMEM;
248925027c84SVladimir Oltean
249025027c84SVladimir Oltean sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid);
249125027c84SVladimir Oltean if (!sfi)
24927d4b564dSXiaoliang Yang return -EINVAL;
249325027c84SVladimir Oltean
249425027c84SVladimir Oltean mutex_lock(&ocelot->stat_view_lock);
249525027c84SVladimir Oltean
249625027c84SVladimir Oltean vsc9959_update_sfid_stats(ocelot, sfi);
249725027c84SVladimir Oltean
249825027c84SVladimir Oltean s = &sfi->stats;
249925027c84SVladimir Oltean stats->pkts = s->match;
250025027c84SVladimir Oltean stats->drops = s->not_pass_gate + s->not_pass_sdu + s->red;
250125027c84SVladimir Oltean
250225027c84SVladimir Oltean memset(s, 0, sizeof(*s));
250325027c84SVladimir Oltean
25047d4b564dSXiaoliang Yang mutex_unlock(&ocelot->stat_view_lock);
25057d4b564dSXiaoliang Yang
25067d4b564dSXiaoliang Yang return 0;
25077d4b564dSXiaoliang Yang }
25087d4b564dSXiaoliang Yang
vsc9959_psfp_init(struct ocelot * ocelot)25097d4b564dSXiaoliang Yang static void vsc9959_psfp_init(struct ocelot *ocelot)
25107d4b564dSXiaoliang Yang {
25117d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp = &ocelot->psfp;
25127d4b564dSXiaoliang Yang
25137d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->stream_list);
25147d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->sfi_list);
251525027c84SVladimir Oltean INIT_LIST_HEAD(&psfp->sgi_list);
25167d4b564dSXiaoliang Yang mutex_init(&psfp->lock);
25177d4b564dSXiaoliang Yang }
25188abe1970SVladimir Oltean
25198abe1970SVladimir Oltean /* When using cut-through forwarding and the egress port runs at a higher data
25208abe1970SVladimir Oltean * rate than the ingress port, the packet currently under transmission would
25218abe1970SVladimir Oltean * suffer an underrun since it would be transmitted faster than it is received.
25228abe1970SVladimir Oltean * The Felix switch implementation of cut-through forwarding does not check in
25238abe1970SVladimir Oltean * hardware whether this condition is satisfied or not, so we must restrict the
25248abe1970SVladimir Oltean * list of ports that have cut-through forwarding enabled on egress to only be
25258abe1970SVladimir Oltean * the ports operating at the lowest link speed within their respective
25268abe1970SVladimir Oltean * forwarding domain.
25278abe1970SVladimir Oltean */
vsc9959_cut_through_fwd(struct ocelot * ocelot)25288abe1970SVladimir Oltean static void vsc9959_cut_through_fwd(struct ocelot *ocelot)
25298abe1970SVladimir Oltean {
25308abe1970SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot);
2531843794bbSVladimir Oltean struct dsa_switch *ds = felix->ds;
25328abe1970SVladimir Oltean int tc, port, other_port;
25338abe1970SVladimir Oltean
25348abe1970SVladimir Oltean lockdep_assert_held(&ocelot->fwd_domain_lock);
25358abe1970SVladimir Oltean
25368abe1970SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) {
2537403ffc2cSVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port];
25388abe1970SVladimir Oltean struct ocelot_mm_state *mm = &ocelot->mm[port];
25398abe1970SVladimir Oltean int min_speed = ocelot_port->speed;
25408abe1970SVladimir Oltean unsigned long mask = 0;
25418abe1970SVladimir Oltean u32 tmp, val = 0;
25428abe1970SVladimir Oltean
25438abe1970SVladimir Oltean /* Disable cut-through on ports that are down */
25448abe1970SVladimir Oltean if (ocelot_port->speed <= 0)
25458abe1970SVladimir Oltean goto set;
25468abe1970SVladimir Oltean
25478abe1970SVladimir Oltean if (dsa_is_cpu_port(ds, port)) {
25488abe1970SVladimir Oltean /* Ocelot switches forward from the NPI port towards
25498abe1970SVladimir Oltean * any port, regardless of it being in the NPI port's
25508abe1970SVladimir Oltean * forwarding domain or not.
25518abe1970SVladimir Oltean */
25528abe1970SVladimir Oltean mask = dsa_user_ports(ds);
25538abe1970SVladimir Oltean } else {
25548abe1970SVladimir Oltean mask = ocelot_get_bridge_fwd_mask(ocelot, port);
25558abe1970SVladimir Oltean mask &= ~BIT(port);
25568abe1970SVladimir Oltean if (ocelot->npi >= 0)
25578abe1970SVladimir Oltean mask |= BIT(ocelot->npi);
2558c295f983SVladimir Oltean else
2559c295f983SVladimir Oltean mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
25608abe1970SVladimir Oltean port);
25618abe1970SVladimir Oltean }
25628abe1970SVladimir Oltean
25638abe1970SVladimir Oltean /* Calculate the minimum link speed, among the ports that are
25648abe1970SVladimir Oltean * up, of this source port's forwarding domain.
25658abe1970SVladimir Oltean */
25668abe1970SVladimir Oltean for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) {
25678abe1970SVladimir Oltean struct ocelot_port *other_ocelot_port;
25688abe1970SVladimir Oltean
25698abe1970SVladimir Oltean other_ocelot_port = ocelot->ports[other_port];
25708abe1970SVladimir Oltean if (other_ocelot_port->speed <= 0)
25718abe1970SVladimir Oltean continue;
25728abe1970SVladimir Oltean
25738abe1970SVladimir Oltean if (min_speed > other_ocelot_port->speed)
25748abe1970SVladimir Oltean min_speed = other_ocelot_port->speed;
25758abe1970SVladimir Oltean }
2576843794bbSVladimir Oltean
2577843794bbSVladimir Oltean /* Enable cut-through forwarding for all traffic classes that
2578403ffc2cSVladimir Oltean * don't have oversized dropping enabled, since this check is
2579403ffc2cSVladimir Oltean * bypassed in cut-through mode. Also exclude preemptible
2580403ffc2cSVladimir Oltean * traffic classes, since these would hang the port for some
2581843794bbSVladimir Oltean * reason, if sent as cut-through.
2582843794bbSVladimir Oltean */
2583403ffc2cSVladimir Oltean if (ocelot_port->speed == min_speed) {
25848abe1970SVladimir Oltean val = GENMASK(7, 0) & ~mm->active_preemptible_tcs;
2585843794bbSVladimir Oltean
2586843794bbSVladimir Oltean for (tc = 0; tc < OCELOT_NUM_TC; tc++)
2587843794bbSVladimir Oltean if (vsc9959_port_qmaxsdu_get(ocelot, port, tc))
2588843794bbSVladimir Oltean val &= ~BIT(tc);
2589843794bbSVladimir Oltean }
25908abe1970SVladimir Oltean
25918abe1970SVladimir Oltean set:
25928abe1970SVladimir Oltean tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port);
25938abe1970SVladimir Oltean if (tmp == val)
25948abe1970SVladimir Oltean continue;
25958abe1970SVladimir Oltean
2596843794bbSVladimir Oltean dev_dbg(ocelot->dev,
25978abe1970SVladimir Oltean "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n",
2598843794bbSVladimir Oltean port, mask, ocelot_port->speed, min_speed,
25998abe1970SVladimir Oltean val ? "enabling" : "disabling", val);
26008abe1970SVladimir Oltean
26018abe1970SVladimir Oltean ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port);
26028abe1970SVladimir Oltean }
26038abe1970SVladimir Oltean }
26047d4b564dSXiaoliang Yang
26057d4b564dSXiaoliang Yang static const struct ocelot_ops vsc9959_ops = {
26067d4b564dSXiaoliang Yang .reset = vsc9959_reset,
26077d4b564dSXiaoliang Yang .wm_enc = vsc9959_wm_enc,
26087d4b564dSXiaoliang Yang .wm_dec = vsc9959_wm_dec,
26097d4b564dSXiaoliang Yang .wm_stat = vsc9959_wm_stat,
26107d4b564dSXiaoliang Yang .port_to_netdev = felix_port_to_netdev,
26117d4b564dSXiaoliang Yang .netdev_to_port = felix_netdev_to_port,
26127d4b564dSXiaoliang Yang .psfp_init = vsc9959_psfp_init,
26137d4b564dSXiaoliang Yang .psfp_filter_add = vsc9959_psfp_filter_add,
26147d4b564dSXiaoliang Yang .psfp_filter_del = vsc9959_psfp_filter_del,
26158abe1970SVladimir Oltean .psfp_stats_get = vsc9959_psfp_stats_get,
26168670dc33SXiaoliang Yang .cut_through_fwd = vsc9959_cut_through_fwd,
261725027c84SVladimir Oltean .tas_clock_adjust = vsc9959_tas_clock_adjust,
2618c6081914SVladimir Oltean .update_stats = vsc9959_update_stats,
26197d4b564dSXiaoliang Yang .tas_guard_bands_update = vsc9959_tas_guard_bands_update,
26207d4b564dSXiaoliang Yang };
2621375e1314SVladimir Oltean
26221109b97bSVladimir Oltean static const struct felix_info felix_info_vsc9959 = {
26231109b97bSVladimir Oltean .resources = vsc9959_resources,
26241109b97bSVladimir Oltean .num_resources = ARRAY_SIZE(vsc9959_resources),
262556051948SVladimir Oltean .resource_names = vsc9959_resource_names,
262656051948SVladimir Oltean .regfields = vsc9959_regfields,
262756051948SVladimir Oltean .map = vsc9959_regmap,
262807d985eeSVladimir Oltean .ops = &vsc9959_ops,
262977043c37SXiaoliang Yang .vcap = vsc9959_vcap_props,
263077043c37SXiaoliang Yang .vcap_pol_base = VSC9959_VCAP_POLICER_BASE,
263177043c37SXiaoliang Yang .vcap_pol_max = VSC9959_VCAP_POLICER_MAX,
263277043c37SXiaoliang Yang .vcap_pol_base2 = 0,
263321ce7f3eSVladimir Oltean .vcap_pol_max2 = 0,
2634acf242fcSColin Foster .num_mact_rows = 2048,
263570d39a6eSVladimir Oltean .num_ports = VSC9959_NUM_PORTS,
26361dc6a2a0SColin Foster .num_tx_queues = OCELOT_NUM_TC,
2637c8c0ba4fSVladimir Oltean .quirks = FELIX_MAC_QUIRKS,
26382ac7c6c5SVladimir Oltean .quirk_no_xtr_irq = true,
2639bdeced75SVladimir Oltean .ptp_caps = &vsc9959_ptp_caps,
2640bdeced75SVladimir Oltean .mdio_bus_alloc = vsc9959_mdio_bus_alloc,
2641acf242fcSColin Foster .mdio_bus_free = vsc9959_mdio_bus_free,
2642de143c0eSXiaoliang Yang .port_modes = vsc9959_port_modes,
2643de143c0eSXiaoliang Yang .port_setup_tc = vsc9959_port_setup_tc,
264456051948SVladimir Oltean .port_sched_speed_set = vsc9959_sched_speed_set,
2645375e1314SVladimir Oltean };
26466505b680SVladimir Oltean
26476505b680SVladimir Oltean /* The INTB interrupt is shared between for PTP TX timestamp availability
26486505b680SVladimir Oltean * notification and MAC Merge status change on each port.
2649375e1314SVladimir Oltean */
felix_irq_handler(int irq,void * data)2650375e1314SVladimir Oltean static irqreturn_t felix_irq_handler(int irq, void *data)
2651375e1314SVladimir Oltean {
2652375e1314SVladimir Oltean struct ocelot *ocelot = (struct ocelot *)data;
2653375e1314SVladimir Oltean
265415f93f46SVladimir Oltean ocelot_get_txtstamp(ocelot);
26556505b680SVladimir Oltean ocelot_mm_irq(ocelot);
2656375e1314SVladimir Oltean
2657375e1314SVladimir Oltean return IRQ_HANDLED;
2658375e1314SVladimir Oltean }
2659375e1314SVladimir Oltean
felix_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2660375e1314SVladimir Oltean static int felix_pci_probe(struct pci_dev *pdev,
2661375e1314SVladimir Oltean const struct pci_device_id *id)
2662375e1314SVladimir Oltean {
2663375e1314SVladimir Oltean struct dsa_switch *ds;
2664375e1314SVladimir Oltean struct ocelot *ocelot;
2665375e1314SVladimir Oltean struct felix *felix;
2666375e1314SVladimir Oltean int err;
2667375e1314SVladimir Oltean
2668375e1314SVladimir Oltean if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) {
2669375e1314SVladimir Oltean dev_info(&pdev->dev, "device is disabled, skipping\n");
2670375e1314SVladimir Oltean return -ENODEV;
2671375e1314SVladimir Oltean }
2672375e1314SVladimir Oltean
2673375e1314SVladimir Oltean err = pci_enable_device(pdev);
2674375e1314SVladimir Oltean if (err) {
2675375e1314SVladimir Oltean dev_err(&pdev->dev, "device enable failed\n");
2676375e1314SVladimir Oltean goto err_pci_enable;
2677375e1314SVladimir Oltean }
2678375e1314SVladimir Oltean
2679375e1314SVladimir Oltean felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
2680375e1314SVladimir Oltean if (!felix) {
2681375e1314SVladimir Oltean err = -ENOMEM;
2682375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate driver memory\n");
2683375e1314SVladimir Oltean goto err_alloc_felix;
2684375e1314SVladimir Oltean }
2685375e1314SVladimir Oltean
2686375e1314SVladimir Oltean pci_set_drvdata(pdev, felix);
2687375e1314SVladimir Oltean ocelot = &felix->ocelot;
268870d39a6eSVladimir Oltean ocelot->dev = &pdev->dev;
2689375e1314SVladimir Oltean ocelot->num_flooding_pgids = OCELOT_NUM_TC;
2690c9910484SColin Foster felix->info = &felix_info_vsc9959;
2691375e1314SVladimir Oltean felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR);
2692375e1314SVladimir Oltean
2693375e1314SVladimir Oltean pci_set_master(pdev);
2694375e1314SVladimir Oltean
2695375e1314SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL,
2696375e1314SVladimir Oltean &felix_irq_handler, IRQF_ONESHOT,
2697375e1314SVladimir Oltean "felix-intb", ocelot);
2698375e1314SVladimir Oltean if (err) {
2699375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to request irq\n");
2700375e1314SVladimir Oltean goto err_alloc_irq;
2701375e1314SVladimir Oltean }
2702375e1314SVladimir Oltean
2703ab3f97a9SVladimir Oltean ocelot->ptp = 1;
2704375e1314SVladimir Oltean ocelot->mm_supported = true;
2705375e1314SVladimir Oltean
2706375e1314SVladimir Oltean ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
2707375e1314SVladimir Oltean if (!ds) {
2708375e1314SVladimir Oltean err = -ENOMEM;
2709375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
2710375e1314SVladimir Oltean goto err_alloc_ds;
2711375e1314SVladimir Oltean }
2712375e1314SVladimir Oltean
2713375e1314SVladimir Oltean ds->dev = &pdev->dev;
2714375e1314SVladimir Oltean ds->num_ports = felix->info->num_ports;
2715375e1314SVladimir Oltean ds->num_tx_queues = felix->info->num_tx_queues;
2716375e1314SVladimir Oltean ds->ops = &felix_switch_ops;
2717375e1314SVladimir Oltean ds->priv = ocelot;
2718adb3dccfSVladimir Oltean felix->ds = ds;
2719375e1314SVladimir Oltean felix->tag_proto = DSA_TAG_PROTO_OCELOT;
2720375e1314SVladimir Oltean
2721375e1314SVladimir Oltean err = dsa_register_switch(ds);
2722e6934e40SMichael Walle if (err) {
2723375e1314SVladimir Oltean dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n");
2724375e1314SVladimir Oltean goto err_register_ds;
2725375e1314SVladimir Oltean }
2726375e1314SVladimir Oltean
2727375e1314SVladimir Oltean return 0;
2728375e1314SVladimir Oltean
2729375e1314SVladimir Oltean err_register_ds:
2730375e1314SVladimir Oltean kfree(ds);
2731375e1314SVladimir Oltean err_alloc_ds:
2732375e1314SVladimir Oltean err_alloc_irq:
2733537e2b88SVladimir Oltean kfree(felix);
2734375e1314SVladimir Oltean err_alloc_felix:
2735375e1314SVladimir Oltean pci_disable_device(pdev);
2736375e1314SVladimir Oltean err_pci_enable:
2737375e1314SVladimir Oltean return err;
2738375e1314SVladimir Oltean }
2739375e1314SVladimir Oltean
felix_pci_remove(struct pci_dev * pdev)2740375e1314SVladimir Oltean static void felix_pci_remove(struct pci_dev *pdev)
27410650bf52SVladimir Oltean {
2742375e1314SVladimir Oltean struct felix *felix = pci_get_drvdata(pdev);
27430650bf52SVladimir Oltean
27440650bf52SVladimir Oltean if (!felix)
2745375e1314SVladimir Oltean return;
2746375e1314SVladimir Oltean
2747375e1314SVladimir Oltean dsa_unregister_switch(felix->ds);
2748375e1314SVladimir Oltean
2749375e1314SVladimir Oltean kfree(felix->ds);
2750375e1314SVladimir Oltean kfree(felix);
2751375e1314SVladimir Oltean
27520650bf52SVladimir Oltean pci_disable_device(pdev);
27530650bf52SVladimir Oltean }
27540650bf52SVladimir Oltean
felix_pci_shutdown(struct pci_dev * pdev)27550650bf52SVladimir Oltean static void felix_pci_shutdown(struct pci_dev *pdev)
27560650bf52SVladimir Oltean {
27570650bf52SVladimir Oltean struct felix *felix = pci_get_drvdata(pdev);
27580650bf52SVladimir Oltean
27590650bf52SVladimir Oltean if (!felix)
27600650bf52SVladimir Oltean return;
27610650bf52SVladimir Oltean
27620650bf52SVladimir Oltean dsa_switch_shutdown(felix->ds);
27630650bf52SVladimir Oltean
2764375e1314SVladimir Oltean pci_set_drvdata(pdev, NULL);
2765375e1314SVladimir Oltean }
2766375e1314SVladimir Oltean
2767375e1314SVladimir Oltean static struct pci_device_id felix_ids[] = {
2768375e1314SVladimir Oltean {
2769375e1314SVladimir Oltean /* NXP LS1028A */
2770375e1314SVladimir Oltean PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
2771375e1314SVladimir Oltean },
2772375e1314SVladimir Oltean { 0, }
2773375e1314SVladimir Oltean };
2774375e1314SVladimir Oltean MODULE_DEVICE_TABLE(pci, felix_ids);
2775d60bc62dSVladimir Oltean
2776375e1314SVladimir Oltean static struct pci_driver felix_vsc9959_pci_driver = {
2777375e1314SVladimir Oltean .name = "mscc_felix",
2778375e1314SVladimir Oltean .id_table = felix_ids,
2779375e1314SVladimir Oltean .probe = felix_pci_probe,
27800650bf52SVladimir Oltean .remove = felix_pci_remove,
2781375e1314SVladimir Oltean .shutdown = felix_pci_shutdown,
2782d60bc62dSVladimir Oltean };
2783d60bc62dSVladimir Oltean module_pci_driver(felix_vsc9959_pci_driver);
2784d60bc62dSVladimir Oltean
2785d60bc62dSVladimir Oltean MODULE_DESCRIPTION("Felix Switch driver");
2786 MODULE_LICENSE("GPL v2");
2787