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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
15 clocks, resets and power domains.
18 '#clock-cells':
21 '#reset-cells':
24 '#power-domain-cells':
30 protected-clocks:
[all …]
H A Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm multimedia clock control module provides the clocks, resets and
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
[all …]
H A Dqcom,sa8775p-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sa8775p-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
13 Qualcomm global clock control module provides the clocks, resets and
16 See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h
20 const: qcom,sa8775p-gcc
22 clocks:
24 - description: XO reference clock
[all …]
H A Dqcom,gcc-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Qualcomm global clock control module provides the clocks, resets and
16 See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
20 const: qcom,gcc-sc8280xp
22 clocks:
24 - description: XO reference clock
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/reset-controller.h>
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
32 if (!f->freq) in qcom_find_freq()
35 for (; f->freq; f++) in qcom_find_freq()
36 if (rate <= f->freq) in qcom_find_freq()
40 return f - 1; in qcom_find_freq()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
24 clocks:
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/openbmc/u-boot/drivers/bootcount/
H A DKconfig40 This requires the RTC clocks, etc, to be enabled prior to use and
58 Store the bootcount in DRAM protected against against bit errors
74 bool "Boot counter in a device-model device"
76 Enables reading/writing the bootcount in a device-model based
77 backing store. If an entry in /chosen/u-boot,bootcount-device
85 menu "Backing stores for device-model backed bootcount"
92 'u-boot,bootcount-rtc' and the 'rtc'-property (a phandle pointing
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8953-xiaomi-daisy.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 /dts-v1/;
11 /delete-node/ &adsp_fw_mem;
12 /delete-node/ &qseecom_mem;
13 /delete-node/ &wcnss_fw_mem;
18 chassis-type = "handset";
19 qcom,msm-id = <293 0>;
20 qcom,board-id = <0x1000b 0x9>;
23 #address-cells = <2>;
24 #size-cells = <2>;
[all …]
H A Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
[all …]
H A Dqcs404-evb.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
19 stdout-path = "serial0";
22 vph_pwr: vph-pwr-regulator {
23 compatible = "regulator-fixed";
24 regulator-name = "vph_pwr";
25 regulator-always-on;
26 regulator-boot-on;
[all …]
H A Dsdm670-google-sargo.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
4 * xiaomi-lavender device tree, and oneplus-common device tree.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
19 /delete-node/ &mpss_region;
20 /delete-node/ &venus_mem;
[all …]
H A Dsdm845-samsung-starqltechn.dts1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 Samsung S9 (SM-G9600) (starqltechn / star2qltechn) common device tree source
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
15 chassis-type = "handset";
16 model = "Samsung Galaxy S9 SM-G9600";
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "simple-framebuffer";
[all …]
H A Dsdm845-mtp.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
17 compatible = "qcom,sdm845-mtp", "qcom,sdm845";
18 chassis-type = "handset";
25 stdout-path = "serial0:115200n8";
28 vph_pwr: vph-pwr-regulator {
29 compatible = "regulator-fixed";
30 regulator-name = "vph_pwr";
31 regulator-min-microvolt = <3700000>;
[all …]
H A Dsdm850-lenovo-yoga-c630.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/qcom,q6afe.h>
14 #include <dt-bindings/sound/qcom,q6asm.h>
16 #include "sdm845-wcd9340.dtsi"
24 /delete-node/ &ipa_fw_mem;
25 /delete-node/ &ipa_gsi_mem;
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dftsdc010_mci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Dante Su <dantesu@faraday-tech.com>
23 #include <dt-structs.h>
41 struct phandle_2_cell clocks[4]; member
65 struct ftsdc010_chip *chip = mmc->priv; in ftsdc010_send_cmd()
66 struct ftsdc010_mmc __iomem *regs = chip->regs; in ftsdc010_send_cmd()
67 int ret = -ETIMEDOUT; in ftsdc010_send_cmd()
69 uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx); in ftsdc010_send_cmd()
70 uint32_t arg = mmc_cmd->cmdarg; in ftsdc010_send_cmd()
71 uint32_t flags = mmc_cmd->resp_type; in ftsdc010_send_cmd()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
[all …]
/openbmc/linux/sound/pci/echoaudio/
H A Dechoaudio.h3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
34 +-----------+
35 record | |<-------------------- Inputs
36 <-------| | |
39 ------->| | +-------+
40 play | |--->|monitor|-------> Outputs
41 +-----------+ | mixer |
[all …]
/openbmc/linux/Documentation/driver-api/
H A Dclk.rst22 clk which unifies the framework-level accounting and infrastructure that
28 The second half of the interface is comprised of the hardware-specific
30 hardware-specific structures needed to model a particular clock. For
32 clk_ops, such as .enable or .set_rate, implies the hardware-specific
35 hardware-specific bits for the hypothetical "foo" hardware.
62 api itself defines several driver-facing functions which operate on
66 clk_ops pointer in struct clk_core to perform the hardware-specific parts of
67 the operations defined in clk-provider.h::
107 which abstract the details of struct clk from the hardware-specific bits, and
109 drivers/clk/clk-gate.c::
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dmvebu-uart.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Armada-3700 Serial Driver
11 #include <linux/clk-provider.h>
106 #define MVEBU_UART_TYPE "mvebu-uart"
165 return (struct mvebu_uart *)port->private_data; in to_mvuart()
168 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
170 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
171 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
172 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
[all …]
/openbmc/u-boot/common/
H A Dboard_f.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2002-2006
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
37 #include <asm/mach-types.h>
87 * global data for all modules, so that post-reloc we can avoid the massive
123 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); in init_baud_rate()
141 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", in display_text_info()
189 dev->name, ret); in print_cpuinfo()
214 size += gd->bd->bi_dram[i].size; in show_dram_config()
216 (unsigned long long)(gd->bd->bi_dram[i].start)); in show_dram_config()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
116 if (!core->rpm_enabled) in clk_pm_runtime_get()
119 return pm_runtime_resume_and_get(core->dev); in clk_pm_runtime_get()
124 if (!core->rpm_enabled) in clk_pm_runtime_put()
127 pm_runtime_put_sync(core->dev); in clk_pm_runtime_put()
[all …]
H A Dclk-stm32h7.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/stm32h7-clks.h>
139 /* Micro-controller output clock parent */
178 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_enable()
183 } while (bit_status && --timeout); in ready_gate_clk_enable()
201 bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_disable()
206 } while (bit_status && --timeout); in ready_gate_clk_disable()
227 return ERR_PTR(-ENOMEM); in clk_register_ready_gate()
235 rgate->bit_rdy = bit_rdy; in clk_register_ready_gate()
[all …]
/openbmc/linux/include/drm/
H A Ddrm_connector.h54 DRM_FORCE_ON_DIGITAL, /* for DVI-I use digital connector */
58 * enum drm_connector_status - status for a &drm_connector
73 * nothing there. It is driver-dependent whether a connector with this
80 * flicker (like load-detection when the connector is in use), or when a
81 * hardware resource isn't available (like when load-detection needs a
91 * enum drm_connector_registration_state - userspace registration status for
124 * - An unregistered connector may only have its DPMS changed from
125 * On->Off. Once DPMS is changed to Off, it may not be switched back
127 * - Modesets are not allowed on unregistered connectors, unless they
131 * - Removing a CRTC from an unregistered connector is OK, but new
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-b1x5pv2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 // Copyright 2018-2021 General Electric Company
7 // Copyright 2018-2021 Collabora
9 #include <dt-bindings/input/input.h>
10 #include "imx6dl-qmx6.dtsi"
14 stdout-path = &uart3;
20 operating-points = <
25 fsl,soc-operating-points = <
26 /* ARM kHz SOC-PU uV */
33 operating-points = <
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c1 // SPDX-License-Identifier: MIT
193 * the range value for them is (actual_value - 2).
263 * These are based on the data rate limits (measured in fast clocks)
279 * These are based on the data rate limits (measured in fast clocks)
305 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
306 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
310 * divided-down version of it.
315 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
316 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
317 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
[all …]

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