Lines Matching +full:protected +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Armada-3700 Serial Driver
11 #include <linux/clk-provider.h>
106 #define MVEBU_UART_TYPE "mvebu-uart"
165 return (struct mvebu_uart *)port->private_data; in to_mvuart()
168 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
170 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
171 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
172 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
175 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
176 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
177 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
178 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
190 spin_lock_irqsave(&port->lock, flags); in mvebu_uart_tx_empty()
191 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
192 spin_unlock_irqrestore(&port->lock, flags); in mvebu_uart_tx_empty()
213 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
222 struct circ_buf *xmit = &port->state->xmit; in mvebu_uart_start_tx()
225 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
229 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
231 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
238 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
240 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
242 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
244 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
252 spin_lock_irqsave(&port->lock, flags); in mvebu_uart_break_ctl()
253 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
254 if (brk == -1) in mvebu_uart_break_ctl()
258 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
259 spin_unlock_irqrestore(&port->lock, flags); in mvebu_uart_break_ctl()
264 struct tty_port *tport = &port->state->port; in mvebu_uart_rx_chars()
271 ch = readl(port->membase + UART_RBR(port)); in mvebu_uart_rx_chars()
274 port->icount.rx++; in mvebu_uart_rx_chars()
277 port->icount.parity++; in mvebu_uart_rx_chars()
285 ret = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
287 writel(ret, port->membase + UART_STAT); in mvebu_uart_rx_chars()
291 port->icount.brk++; in mvebu_uart_rx_chars()
298 port->icount.overrun++; in mvebu_uart_rx_chars()
301 port->icount.frame++; in mvebu_uart_rx_chars()
306 if (status & port->ignore_status_mask & STAT_PAR_ERR) in mvebu_uart_rx_chars()
309 status &= port->read_status_mask; in mvebu_uart_rx_chars()
314 status &= ~port->ignore_status_mask; in mvebu_uart_rx_chars()
329 status = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
339 uart_port_tx_limited(port, ch, port->fifosize, in mvebu_uart_tx_chars()
340 !(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL), in mvebu_uart_tx_chars()
341 writel(ch, port->membase + UART_TSH(port)), in mvebu_uart_tx_chars()
348 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_isr()
363 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_rx_isr()
375 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_tx_isr()
390 port->membase + UART_CTRL(port)); in mvebu_uart_startup()
394 ret = readl(port->membase + UART_STAT); in mvebu_uart_startup()
396 writel(ret, port->membase + UART_STAT); in mvebu_uart_startup()
398 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); in mvebu_uart_startup()
400 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
402 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
404 if (!mvuart->irq[UART_TX_IRQ]) { in mvebu_uart_startup()
406 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM], in mvebu_uart_startup()
407 mvebu_uart_isr, port->irqflags, in mvebu_uart_startup()
408 dev_name(port->dev), port); in mvebu_uart_startup()
410 dev_err(port->dev, "unable to request IRQ %d\n", in mvebu_uart_startup()
411 mvuart->irq[UART_IRQ_SUM]); in mvebu_uart_startup()
416 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ], in mvebu_uart_startup()
417 mvebu_uart_rx_isr, port->irqflags, in mvebu_uart_startup()
418 dev_name(port->dev), port); in mvebu_uart_startup()
420 dev_err(port->dev, "unable to request IRQ %d\n", in mvebu_uart_startup()
421 mvuart->irq[UART_RX_IRQ]); in mvebu_uart_startup()
425 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ], in mvebu_uart_startup()
426 mvebu_uart_tx_isr, port->irqflags, in mvebu_uart_startup()
427 dev_name(port->dev), in mvebu_uart_startup()
430 dev_err(port->dev, "unable to request IRQ %d\n", in mvebu_uart_startup()
431 mvuart->irq[UART_TX_IRQ]); in mvebu_uart_startup()
432 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], in mvebu_uart_startup()
445 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
447 if (!mvuart->irq[UART_TX_IRQ]) { in mvebu_uart_shutdown()
448 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port); in mvebu_uart_shutdown()
450 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port); in mvebu_uart_shutdown()
451 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port); in mvebu_uart_shutdown()
461 if (!port->uartclk) in mvebu_uart_baud_rate_set()
496 * Member port->uartclk is either xtal clock rate or TBG clock rate in mvebu_uart_baud_rate_set()
503 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); in mvebu_uart_baud_rate_set()
511 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); in mvebu_uart_baud_rate_set()
520 brdv = readl(port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
523 writel(brdv, port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
526 osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
531 writel(osamp, port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
533 return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor); in mvebu_uart_baud_rate_set()
543 spin_lock_irqsave(&port->lock, flags); in mvebu_uart_set_termios()
545 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR | in mvebu_uart_set_termios()
548 if (termios->c_iflag & INPCK) in mvebu_uart_set_termios()
549 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR; in mvebu_uart_set_termios()
551 port->ignore_status_mask = 0; in mvebu_uart_set_termios()
552 if (termios->c_iflag & IGNPAR) in mvebu_uart_set_termios()
553 port->ignore_status_mask |= in mvebu_uart_set_termios()
556 if ((termios->c_cflag & CREAD) == 0) in mvebu_uart_set_termios()
557 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; in mvebu_uart_set_termios()
563 * rate. If port->uartclk is not available, then in mvebu_uart_set_termios()
567 min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX * in mvebu_uart_set_termios()
569 max_baud = port->uartclk / 80; in mvebu_uart_set_termios()
580 termios->c_iflag &= INPCK | IGNPAR; in mvebu_uart_set_termios()
581 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR); in mvebu_uart_set_termios()
582 termios->c_cflag &= CREAD | CBAUD; in mvebu_uart_set_termios()
583 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD); in mvebu_uart_set_termios()
584 termios->c_cflag |= CS8; in mvebu_uart_set_termios()
589 uart_update_timeout(port, termios->c_cflag, baud); in mvebu_uart_set_termios()
592 spin_unlock_irqrestore(&port->lock, flags); in mvebu_uart_set_termios()
613 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_get_poll_char()
618 return readl(port->membase + UART_RBR(port)); in mvebu_uart_get_poll_char()
626 st = readl(port->membase + UART_STAT); in mvebu_uart_put_poll_char()
634 writel(c, port->membase + UART_TSH(port)); in mvebu_uart_put_poll_char()
667 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
673 writel(c, port->membase + UART_STD_TSH); in mvebu_uart_putc()
676 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
686 struct earlycon_device *dev = con->data; in mvebu_uart_putc_early_write()
688 uart_console_write(&dev->port, s, n, mvebu_uart_putc); in mvebu_uart_putc_early_write()
695 if (!device->port.membase) in mvebu_uart_early_console_setup()
696 return -ENODEV; in mvebu_uart_early_console_setup()
698 device->con->write = mvebu_uart_putc_early_write; in mvebu_uart_early_console_setup()
704 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
711 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmitr()
719 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmite()
726 writel(ch, port->membase + UART_TSH(port)); in mvebu_uart_console_putchar()
732 struct uart_port *port = &mvebu_uart_ports[co->index]; in mvebu_uart_console_write()
738 locked = spin_trylock_irqsave(&port->lock, flags); in mvebu_uart_console_write()
740 spin_lock_irqsave(&port->lock, flags); in mvebu_uart_console_write()
742 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; in mvebu_uart_console_write()
743 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
745 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
746 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
753 writel(ier, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
756 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
757 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
761 spin_unlock_irqrestore(&port->lock, flags); in mvebu_uart_console_write()
772 if (co->index < 0 || co->index >= MVEBU_NR_UARTS) in mvebu_uart_console_setup()
773 return -EINVAL; in mvebu_uart_console_setup()
775 port = &mvebu_uart_ports[co->index]; in mvebu_uart_console_setup()
777 if (!port->mapbase || !port->membase) { in mvebu_uart_console_setup()
778 pr_debug("console on ttyMV%i not present\n", co->index); in mvebu_uart_console_setup()
779 return -ENODEV; in mvebu_uart_console_setup()
796 .index = -1,
825 struct uart_port *port = mvuart->port; in mvebu_uart_suspend()
830 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
831 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
832 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_suspend()
833 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
834 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
836 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
838 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
848 struct uart_port *port = mvuart->port; in mvebu_uart_resume()
851 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
852 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
853 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); in mvebu_uart_resume()
854 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()
855 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
857 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
859 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); in mvebu_uart_resume()
880 &pdev->dev); in mvebu_uart_probe()
887 id = of_alias_get_id(pdev->dev.of_node, "serial"); in mvebu_uart_probe()
888 if (!pdev->dev.of_node || id < 0) in mvebu_uart_probe()
889 pdev->id = uart_num_counter++; in mvebu_uart_probe()
891 pdev->id = id; in mvebu_uart_probe()
893 if (pdev->id >= MVEBU_NR_UARTS) { in mvebu_uart_probe()
894 dev_err(&pdev->dev, "cannot have more than %d UART ports\n", in mvebu_uart_probe()
896 return -EINVAL; in mvebu_uart_probe()
899 port = &mvebu_uart_ports[pdev->id]; in mvebu_uart_probe()
901 spin_lock_init(&port->lock); in mvebu_uart_probe()
903 port->dev = &pdev->dev; in mvebu_uart_probe()
904 port->type = PORT_MVEBU; in mvebu_uart_probe()
905 port->ops = &mvebu_uart_ops; in mvebu_uart_probe()
906 port->regshift = 0; in mvebu_uart_probe()
908 port->fifosize = 32; in mvebu_uart_probe()
909 port->iotype = UPIO_MEM32; in mvebu_uart_probe()
910 port->flags = UPF_FIXED_PORT; in mvebu_uart_probe()
911 port->line = pdev->id; in mvebu_uart_probe()
916 * array so called ->irq[]. in mvebu_uart_probe()
918 port->irq = 0; in mvebu_uart_probe()
919 port->irqflags = 0; in mvebu_uart_probe()
921 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, ®); in mvebu_uart_probe()
922 if (IS_ERR(port->membase)) in mvebu_uart_probe()
923 return PTR_ERR(port->membase); in mvebu_uart_probe()
924 port->mapbase = reg->start; in mvebu_uart_probe()
926 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart), in mvebu_uart_probe()
929 return -ENOMEM; in mvebu_uart_probe()
932 mvuart->data = (struct mvebu_uart_driver_data *)match->data; in mvebu_uart_probe()
933 mvuart->port = port; in mvebu_uart_probe()
935 port->private_data = mvuart; in mvebu_uart_probe()
939 mvuart->clk = devm_clk_get(&pdev->dev, NULL); in mvebu_uart_probe()
940 if (IS_ERR(mvuart->clk)) { in mvebu_uart_probe()
941 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER) in mvebu_uart_probe()
942 return PTR_ERR(mvuart->clk); in mvebu_uart_probe()
945 dev_err(&pdev->dev, "unable to get UART clock\n"); in mvebu_uart_probe()
946 return PTR_ERR(mvuart->clk); in mvebu_uart_probe()
949 if (!clk_prepare_enable(mvuart->clk)) in mvebu_uart_probe()
950 port->uartclk = clk_get_rate(mvuart->clk); in mvebu_uart_probe()
960 mvuart->irq[UART_IRQ_SUM] = irq; in mvebu_uart_probe()
964 * only make use of uart-rx and uart-tx interrupts, do not use in mvebu_uart_probe()
965 * uart-sum of UART0 port. in mvebu_uart_probe()
967 irq = platform_get_irq_byname(pdev, "uart-rx"); in mvebu_uart_probe()
971 mvuart->irq[UART_RX_IRQ] = irq; in mvebu_uart_probe()
973 irq = platform_get_irq_byname(pdev, "uart-tx"); in mvebu_uart_probe()
977 mvuart->irq[UART_TX_IRQ] = irq; in mvebu_uart_probe()
981 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
983 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
1015 .compatible = "marvell,armada-3700-uart",
1019 .compatible = "marvell,armada-3700-uart-ext",
1028 .name = "mvebu-uart",
1037 /* This code is based on clk-fixed-factor.c driver and modified. */
1047 struct mvebu_uart_clock clocks[2]; member
1060 struct mvebu_uart_clock_base, clocks[uart_clock->clock_idx])
1080 * otherwise kernel's boot log stops working - we need to ensure that in mvebu_uart_clock_prepare()
1086 * UART_BRDV (reg1) needs to be protected by a lock. in mvebu_uart_clock_prepare()
1091 if (uart_clock_base->configured) { in mvebu_uart_clock_prepare()
1096 parent_clock_idx = uart_clock_base->parent_idx; in mvebu_uart_clock_prepare()
1097 parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx]; in mvebu_uart_clock_prepare()
1099 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_prepare()
1101 if (uart_clock_base->div > CLK_TBG_DIV1_MAX) { in mvebu_uart_clock_prepare()
1103 d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX; in mvebu_uart_clock_prepare()
1105 d1 = uart_clock_base->div; in mvebu_uart_clock_prepare()
1118 /* Note that uart_clock_base->parent_rates[i] may not be available */ in mvebu_uart_clock_prepare()
1119 prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx]; in mvebu_uart_clock_prepare()
1147 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_prepare()
1151 val = readl(uart_clock_base->reg2); in mvebu_uart_clock_prepare()
1160 writel(val, uart_clock_base->reg2); in mvebu_uart_clock_prepare()
1163 uart_clock_base->configured = true; in mvebu_uart_clock_prepare()
1180 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_enable()
1182 if (uart_clock->clock_idx == 0) in mvebu_uart_clock_enable()
1187 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_enable()
1204 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_disable()
1206 if (uart_clock->clock_idx == 0) in mvebu_uart_clock_disable()
1211 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_disable()
1223 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_is_enabled()
1225 if (uart_clock->clock_idx == 0) in mvebu_uart_clock_is_enabled()
1239 uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1); in mvebu_uart_clock_save_context()
1240 uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2); in mvebu_uart_clock_save_context()
1254 writel(uart_clock->pm_context_reg1, uart_clock_base->reg1); in mvebu_uart_clock_restore_context()
1255 writel(uart_clock->pm_context_reg2, uart_clock_base->reg2); in mvebu_uart_clock_restore_context()
1266 return parent_rate / uart_clock_base->div; in mvebu_uart_clock_recalc_rate()
1276 return *parent_rate / uart_clock_base->div; in mvebu_uart_clock_round_rate()
1310 uart_clock->clk_hw.init = &init; in mvebu_uart_clock_register()
1318 return devm_clk_hw_register(dev, &uart_clock->clk_hw); in mvebu_uart_clock_register()
1324 static const char *const parent_clk_names[] = { "TBG-A-P", "TBG-B-P", in mvebu_uart_clock_probe()
1325 "TBG-A-S", "TBG-B-S", in mvebu_uart_clock_probe()
1330 struct device *dev = &pdev->dev; in mvebu_uart_clock_probe()
1337 ARRAY_SIZE(uart_clock_base->clocks)); in mvebu_uart_clock_probe()
1339 ARRAY_SIZE(uart_clock_base->parent_rates)); in mvebu_uart_clock_probe()
1345 return -ENOMEM; in mvebu_uart_clock_probe()
1350 return -ENOENT; in mvebu_uart_clock_probe()
1358 * avoid conflicts with UART1 driver. Access to UART_BRDV is protected in mvebu_uart_clock_probe()
1361 uart_clock_base->reg1 = devm_ioremap(dev, res->start, in mvebu_uart_clock_probe()
1363 if (!uart_clock_base->reg1) in mvebu_uart_clock_probe()
1364 return -ENOMEM; in mvebu_uart_clock_probe()
1369 return -ENOENT; in mvebu_uart_clock_probe()
1377 * conflicts with UART2 driver. Access to UART_BRDV is protected by a in mvebu_uart_clock_probe()
1380 uart_clock_base->reg2 = devm_ioremap(dev, res->start, in mvebu_uart_clock_probe()
1382 if (!uart_clock_base->reg2) in mvebu_uart_clock_probe()
1383 return -ENOMEM; in mvebu_uart_clock_probe()
1390 return -ENOMEM; in mvebu_uart_clock_probe()
1392 hw_clk_data->num = ARRAY_SIZE(uart_clk_names); in mvebu_uart_clock_probe()
1394 hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw; in mvebu_uart_clock_probe()
1395 uart_clock_base->clocks[i].clock_idx = i; in mvebu_uart_clock_probe()
1398 parent_clk_idx = -1; in mvebu_uart_clock_probe()
1403 if (PTR_ERR(parent_clks[i]) == -EPROBE_DEFER) in mvebu_uart_clock_probe()
1404 return -EPROBE_DEFER; in mvebu_uart_clock_probe()
1417 uart_clock_base->parent_rates[i] = rate; in mvebu_uart_clock_probe()
1454 if (parent_clk_idx == -1 || in mvebu_uart_clock_probe()
1468 if (parent_clk_idx == -1) { in mvebu_uart_clock_probe()
1470 return -ENOENT; in mvebu_uart_clock_probe()
1473 uart_clock_base->parent_idx = parent_clk_idx; in mvebu_uart_clock_probe()
1474 uart_clock_base->div = div; in mvebu_uart_clock_probe()
1481 &uart_clock_base->clocks[i], in mvebu_uart_clock_probe()
1496 { .compatible = "marvell,armada-3700-uart-clock", },
1503 .name = "mvebu-uart-clock",