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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll3-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
20 const: allwinner,sun4i-a10-pll3-clk
44 compatible = "allwinner,sun4i-a10-pll3-clk";
47 clock-output-names = "pll3";
H A Dallwinner,sun4i-a10-tcon-ch0-clk.yaml64 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
73 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
H A Dallwinner,sun9i-a80-cpus-clk.yaml48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
H A Dallwinner,sun4i-a10-display-clk.yaml53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
/openbmc/linux/sound/soc/codecs/
H A Dak4642.c113 #define PLL3 (1 << 7) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
363 pll = PLL3; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h21 u32 pll3_cfg; /* 0x10 pll3 video0 control */
97 u32 pll3_bias_cfg; /* 0x228 PLL3 video Bias config */
111 u32 pll3_pattern_cfg0; /* 0x288 PLL3 Pattern register 0 */
116 u32 pll3_pattern_cfg1; /* 0x2a8 PLL3 Pattern register 1 */
H A Dclock_sun50i_h6.h23 u32 pll3_cfg; /* 0x040 pll3 (video0) control */
42 u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */
43 u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */
67 u32 pll3_bias; /* 0x340 pll3 (video0) bias */
/openbmc/u-boot/drivers/clk/renesas/
H A Dr8a77970-cpg-mssr.c66 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
153 * MD EXTAL PLL0 PLL1 PLL3
170 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a77995-cpg-mssr.c58 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
182 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
190 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a77990-cpg-mssr.c59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
244 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
252 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a7795-cpg-mssr.c62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
272 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
298 /* EXTAL div PLL1 mult/div PLL3 mult/div */
/openbmc/linux/drivers/clk/renesas/
H A Dr8a77470-cpg-mssr.c46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
173 * MD EXTAL PLL0 PLL1 PLL3
188 /* EXTAL div PLL1 mult x2 PLL3 mult */
H A Dr8a77995-cpg-mssr.c60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
211 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
219 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a779f0-cpg-mssr.c63 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
191 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
H A Dr8a77970-cpg-mssr.c73 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
178 * MD EXTAL PLL0 PLL1 PLL3
195 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a7745-cpg-mssr.c46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
190 * MD EXTAL PLL0 PLL1 PLL3
205 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
H A Dr8a77980-cpg-mssr.c60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
211 * MD EXTAL PLL2 PLL1 PLL3 OSC
223 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
H A Dr8a7742-cpg-mssr.c46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
212 * MD EXTAL PLL0 PLL1 PLL3
231 /* EXTAL div PLL1 mult PLL3 mult */
H A Dr8a7743-cpg-mssr.c47 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
206 * MD EXTAL PLL0 PLL1 PLL3
225 /* EXTAL div PLL1 mult PLL3 mult */
H A Dr8a774c0-cpg-mssr.c62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
261 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
269 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a779g0-cpg-mssr.c72 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
247 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
259 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
H A Dr8a77990-cpg-mssr.c62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
275 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
283 /* EXTAL div PLL1 mult/div PLL3 mult/div */
H A Dr8a774b1-cpg-mssr.c59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
259 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
285 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
H A Dr8a774a1-cpg-mssr.c61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
263 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
289 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
/openbmc/linux/drivers/clk/sunxi/
H A DMakefile18 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-pll3.o

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