|
Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14 |
|
| #
427322dc |
| 25-Jan-2024 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
[ Upstream commit d1b32a83a02d9433dbd8c5f4d6fc44aa597755bd ]
According to the R-Car S4 Series Hardware User’s Manual Rev.0.81, the
parent clock
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
[ Upstream commit d1b32a83a02d9433dbd8c5f4d6fc44aa597755bd ]
According to the R-Car S4 Series Hardware User’s Manual Rev.0.81, the
parent clock of the Pin Function (PFC/GPIO) module clock is the CP
clock.
As this clock is not documented to exist on R-Car S4, use the CPEX clock
instead.
Fixes: 73421f2a48e6bd1d ("clk: renesas: r8a779f0: Add PFC clock")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f88ec4aede0eaf0107c8bb7b28ba719ac6cd418f.1706197415.git.geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>
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|
Revision tags: v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79 |
|
| #
777bcc85 |
| 15-Nov-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Fix Ethernet Switch clocks
The RSwitch2 and EtherTSN-IF clocks were accidentally mixed up.
While at it, rename them to better match the (future) documentation.
Fixes: a3b413
clk: renesas: r8a779f0: Fix Ethernet Switch clocks
The RSwitch2 and EtherTSN-IF clocks were accidentally mixed up.
While at it, rename them to better match the (future) documentation.
Fixes: a3b4137a4d4023e6 ("clk: renesas: r8a779f0: Add Ethernet Switch clocks")
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/99b8b41bd2c5043c9e457862ef4bc144869eca58.1668501212.git.geert+renesas@glider.be
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|
Revision tags: v6.0.8, v5.15.78, v6.0.7, v5.15.77 |
|
| #
2e0d7d3e |
| 03-Nov-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: r8a779f0: Fix SCIF parent clocks
As serial communication requires a clean clock signal, the Serial
Communication Interfaces with FIFO (SCIF) are clocked by a clock that is
not affected
clk: renesas: r8a779f0: Fix SCIF parent clocks
As serial communication requires a clean clock signal, the Serial
Communication Interfaces with FIFO (SCIF) are clocked by a clock that is
not affected by Spread Spectrum or Fractional Multiplication.
Hence change the parent clocks for the SCIF modules from the S0D12_PER
clock to the SASYNCPERD4 clock (which has the same clock rate), cfr.
R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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|
| #
c258e3ab |
| 03-Nov-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: r8a779f0: Fix HSCIF parent clocks
As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock
that is
clk: renesas: r8a779f0: Fix HSCIF parent clocks
As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the parent clocks for the HSCIF modules from the S0D3_PER
clock to the SASYNCPERD1 clock (which has the same clock rate), cfr.
R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: 080bcd8d5997 ("clk: renesas: r8a779f0: Add HSCIF clocks")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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|
Revision tags: v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1 |
|
| #
0a5a00f0 |
| 12-Oct-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Add SASYNCPER internal clock
Add the SASYNCPER internal clock, which is the clock source of the
various SASYNCPERD[124] clocks, to match the clock tree diagram in the
documen
clk: renesas: r8a779f0: Add SASYNCPER internal clock
Add the SASYNCPER internal clock, which is the clock source of the
various SASYNCPERD[124] clocks, to match the clock tree diagram in the
documentation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/18e6765bfc3bf7c3ee5ce93a370d377c1d17728e.1665558014.git.geert+renesas@glider.be
show more ...
|
| #
99c05a2b |
| 12-Oct-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Fix SD0H clock name
Correct the misspelled textual name of the SD0H clock.
Fixes: 9b5dd1ff705c6854 ("clk: renesas: r8a779f0: Add SDH0 clock")
Signed-off-by: Geert Uytterhoev
clk: renesas: r8a779f0: Fix SD0H clock name
Correct the misspelled textual name of the SD0H clock.
Fixes: 9b5dd1ff705c6854 ("clk: renesas: r8a779f0: Add SDH0 clock")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/1f682d338f133608f138ae87323707436ad8c748.1665558014.git.geert+renesas@glider.be
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|
Revision tags: v5.15.72, v6.0, v5.15.71, v5.15.70 |
|
| #
a3b4137a |
| 22-Sep-2022 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: r8a779f0: Add Ethernet Switch clocks
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220922051358.3442191-1-yoshihiro.shimoda.uh@r
clk: renesas: r8a779f0: Add Ethernet Switch clocks
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220922051358.3442191-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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|
Revision tags: v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63 |
|
| #
644814c1 |
| 24-Aug-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: r8a779f0: Add MSIOF clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220824103515.54931-2-wsa+renesas@sang-engineering.com
Signed
clk: renesas: r8a779f0: Add MSIOF clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220824103515.54931-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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|
Revision tags: v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58 |
|
| #
1e56ebc9 |
| 26-Jul-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220726210110.1444-2-wsa+renesas@sang-enginee
clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220726210110.1444-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
|
|
Revision tags: v5.15.57, v5.15.56, v5.15.55 |
|
| #
32fb5425 |
| 13-Jul-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: r8a779f0: Add CMT clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220713101447.3804-2-wsa+renesas@sang-engineering.com
Signed-of
clk: renesas: r8a779f0: Add CMT clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220713101447.3804-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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|
Revision tags: v5.15.54 |
|
| #
9b5dd1ff |
| 11-Jul-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: r8a779f0: Add SDH0 clock
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <
clk: renesas: r8a779f0: Add SDH0 clock
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220711134656.277730-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
|
|
Revision tags: v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47 |
|
| #
080bcd8d |
| 14-Jun-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: r8a779f0: Add HSCIF clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220614094937.8104-1-wsa+renesas@sang-engineering.com
Signed-
clk: renesas: r8a779f0: Add HSCIF clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220614094937.8104-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
|
| #
b7f64eae |
| 13-Jun-2022 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: r8a779f0: Add PCIe clocks
Add the module clocks used by the PCIe controllers on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.c
clk: renesas: r8a779f0: Add PCIe clocks
Add the module clocks used by the PCIe controllers on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220613115627.2831257-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
|
|
Revision tags: v5.15.46 |
|
| #
d5c10876 |
| 08-Jun-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Add Z0 and Z1 clock support
Add support for the Z0 and Z1 (Cortex-A55 Sub-System 0 (CPU 0-3) and
Sub-System 1 (CPU 4-7)) clocks on R-Car S4-8, based on the existing
support f
clk: renesas: r8a779f0: Add Z0 and Z1 clock support
Add support for the Z0 and Z1 (Cortex-A55 Sub-System 0 (CPU 0-3) and
Sub-System 1 (CPU 4-7)) clocks on R-Car S4-8, based on the existing
support for Z clocks on R-Car Gen4.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/43009e25be1223a717e00c392cb2d416f5d47032.1654695893.git.geert+renesas@glider.be
show more ...
|
|
Revision tags: v5.15.45 |
|
| #
75fe45a0 |
| 03-Jun-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: r8a779f0: Add SDHI0 clock
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com
Signed-
clk: renesas: r8a779f0: Add SDHI0 clock
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
|
|
Revision tags: v5.15.44 |
|
| #
61a6737f |
| 25-May-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: r8a779f0: Add thermal clock
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220525151130.24103-1-wsa+renesas@sang-engineering.com
Signe
clk: renesas: r8a779f0: Add thermal clock
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220525151130.24103-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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|
Revision tags: v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36 |
|
| #
7f906eaa |
| 25-Apr-2022 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.
clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
|
|
Revision tags: v5.15.35, v5.15.34 |
|
| #
b243a358 |
| 11-Apr-2022 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: r8a779f0: Add UFS clock
Add the module clock used by the UFS host controller on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.c
clk: renesas: r8a779f0: Add UFS clock
Add the module clock used by the UFS host controller on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220411124932.3765571-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
|
| #
880c3fa3 |
| 11-Apr-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: Move RPC core clocks
The RPC and RPCD2 core clocks were added to the sections for internal
core clocks, while they are core clock outputs, visible from DT.
Move them to the correct se
clk: renesas: Move RPC core clocks
The RPC and RPCD2 core clocks were added to the sections for internal
core clocks, while they are core clock outputs, visible from DT.
Move them to the correct sections.
Rename the ".rpc" clock on R-Car S4 to "rpc".
Fixup nearby whitespace to increase uniformity.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be
show more ...
|
|
Revision tags: v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25 |
|
| #
73421f2a |
| 21-Feb-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Add PFC clock
Add the module clock used by the Pin Function (PFC/GPIO) controller
on the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU H
clk: renesas: r8a779f0: Add PFC clock
Add the module clock used by the Pin Function (PFC/GPIO) controller
on the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/4ef3d3dfe714ad75112e4886efea0b66e40a33bc.1645457502.git.geert+renesas@glider.be
show more ...
|
|
Revision tags: v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20 |
|
| #
5447d32c |
| 03-Feb-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Add I2C clocks
Add the module clocks used by the I2C Bus Interfaces on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-o
clk: renesas: r8a779f0: Add I2C clocks
Add the module clocks used by the I2C Bus Interfaces on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/e4dcee5f6f521dccd7ac7f2fb6c86cfe4a24d032.1643898820.git.geert+renesas@glider.be
show more ...
|
|
Revision tags: v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16 |
|
| #
78789705 |
| 18-Jan-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Add WDT clock
Add the module clock used by the RCLK Watchdog Timer (RWDT) on the
Renesas R-Car S4-8 (r8a779f0) SoC. Mark it as a critical clock, to
ensure uninterrupted watc
clk: renesas: r8a779f0: Add WDT clock
Add the module clock used by the RCLK Watchdog Timer (RWDT) on the
Renesas R-Car S4-8 (r8a779f0) SoC. Mark it as a critical clock, to
ensure uninterrupted watchdog operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/8d9b280065a663f2cf31db7b21a010aa781a0af1.1642525158.git.geert+renesas@glider.be
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Revision tags: v5.15.15, v5.16 |
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691419f9 |
| 07-Jan-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Fix RSW2 clock divider
According to Section 8.1.2 Figure 8.1.1 ("Block Diagram of CPG"), Note
22 ("RSW2 divider"), and Table 8.1.4d ("Lists of CPG clocks generated
from CPGMA
clk: renesas: r8a779f0: Fix RSW2 clock divider
According to Section 8.1.2 Figure 8.1.1 ("Block Diagram of CPG"), Note
22 ("RSW2 divider"), and Table 8.1.4d ("Lists of CPG clocks generated
from CPGMA1"), the RSwitch2 and PCI Express clock is generated from PLL5
by dividing by two, followed by the RSW2 divider. As PLL5 runs at 3200
MHz, and RSW2 is fixed to 320 MHz, the RSW2 divider must be 5.
Correct the parent and the fixed divider.
Fixes: 24aaff6a6ce4c4de ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d6a406f31e6f02f892e0253f4e8a9a2f68fd652e.1641566003.git.geert+renesas@glider.be
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59a43fa2 |
| 20-Dec-2021 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: r8a779f0: Add SYS-DMAC clocks
Add SYS-DMAC clocks on r8a779f0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20211221052423.59728
clk: renesas: r8a779f0: Add SYS-DMAC clocks
Add SYS-DMAC clocks on r8a779f0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20211221052423.597283-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Revision tags: v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6 |
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24aaff6a |
| 01-Dec-2021 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: cpg-mssr: Add support for R-Car S4-8
Initial CPG support for R-Car S4-8 (r8a779f0).
Inspired by patches in the BSP by LUU HOAI.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh
clk: renesas: cpg-mssr: Add support for R-Car S4-8
Initial CPG support for R-Car S4-8 (r8a779f0).
Inspired by patches in the BSP by LUU HOAI.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20211201073308.1003945-10-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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