clk: renesas: rcar-gen3: Add ADG clocks

R-Car Sound needs to enable "ADG" on RMSTPCR9/SMSTPCR9 bit 22 to use
clk_i which came from the internal S0D4 or ZA2 clock.

Signed-off-by: Kuninori Morimoto <

clk: renesas: rcar-gen3: Add ADG clocks

R-Car Sound needs to enable "ADG" on RMSTPCR9/SMSTPCR9 bit 22 to use
clk_i which came from the internal S0D4 or ZA2 clock.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> # R-Car M3-N
Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> # R-Car M3-N
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/87pm47prox.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87o7jrpros.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87mszbpron.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87leevproh.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87jzufprod.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87il9zpro8.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87h6pjpro4.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87fs53prny.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87edknprnt.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: Move RPC core clocks

The RPC and RPCD2 core clocks were added to the sections for internal
core clocks, while they are core clock outputs, visible from DT.

Move them to the correct se

clk: renesas: Move RPC core clocks

The RPC and RPCD2 core clocks were added to the sections for internal
core clocks, while they are core clock outputs, visible from DT.

Move them to the correct sections.
Rename the ".rpc" clock on R-Car S4 to "rpc".
Fixup nearby whitespace to increase uniformity.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be

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clk: renesas: r8a77990: Add RPC clocks

Describe the various clocks used by the SPI Multi I/O Bus Controller
(RPC-IF) on the R-Car E3 SoC: RPCSRC internal clock, RPC{,D2} clocks
derived from it, and

clk: renesas: r8a77990: Add RPC clocks

Describe the various clocks used by the SPI Multi I/O Bus Controller
(RPC-IF) on the R-Car E3 SoC: RPCSRC internal clock, RPC{,D2} clocks
derived from it, and RPC-IF module clock.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/3295013f27f1e4b8fbf3f79b950d65157ea95ef2.1648546700.git.geert+renesas@glider.be

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clk: renesas: r8a7799[05]: Add MLP clocks

Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.

Similar to other R-Car Gen3 SoC, exact information on the parents of MLP
clocks on E3 and D3 is

clk: renesas: r8a7799[05]: Add MLP clocks

Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.

Similar to other R-Car Gen3 SoC, exact information on the parents of MLP
clocks on E3 and D3 is not available. However, since the parents of
these clocks are not anyhow software-controllable, the only harm from
this is inexact information exported via debugfs. So just keep the
parent set in the same way as with other Gen3 SoCs.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20211225193957.2195012-1-nikita.yoush@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Add SDnH clock

Currently a pass-through clock but we will make it a real divider clock
in the next patches.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
L

clk: renesas: rcar-gen3: Add SDnH clock

Currently a pass-through clock but we will make it a real divider clock
in the next patches.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: r8a77990: Add DAB clock

This patch adds the DAB clock to the R8A77990 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/202102252251

clk: renesas: r8a77990: Add DAB clock

This patch adds the DAB clock to the R8A77990 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20210225225147.29920-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: r8a77990: Add TMU clocks

This patch adds TMU{0,1,2,3,4} clocks.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20201209195343.

clk: renesas: r8a77990: Add TMU clocks

This patch adds TMU{0,1,2,3,4} clocks.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20201209195343.803120-5-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Mark RWDT clocks as critical

Ensures RWDT remains alert throughout the boot process if enabled.

This patch applies the change to the following SoCs: r8a77950, r8a77951,
r8a

clk: renesas: rcar-gen3: Mark RWDT clocks as critical

Ensures RWDT remains alert throughout the boot process if enabled.

This patch applies the change to the following SoCs: r8a77950, r8a77951,
r8a77960, r8a77961, r8a77965, r8a77970, r8a77980, r8a77990 and r8a77995.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200616162626.27944-3-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Add CCREE clocks

Add the CryptoCell module clocks and their parents for the CryptoCell
instances in the various Renesas R-Car Gen3 SoCs that do not have
support for them yet

clk: renesas: rcar-gen3: Add CCREE clocks

Add the CryptoCell module clocks and their parents for the CryptoCell
instances in the various Renesas R-Car Gen3 SoCs that do not have
support for them yet in their clock drivers (M3-W/W+, M3-N, E3, D3).

The R-Car H3 clock driver already supports these clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200124133137.15921-1-geert+renesas@glider.be

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clk: renesas: r8a77990: Add CMM clocks

Add clock definitions for CMM units on Renesas R-Car E3.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pincha

clk: renesas: r8a77990: Add CMM clocks

Add clock definitions for CMM units on Renesas R-Car E3.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Rename DRIF clocks

According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
12, 2019, the DRIF clocks have been renamed as follows:

DRIF0 to DRIF00
D

clk: renesas: rcar-gen3: Rename DRIF clocks

According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
12, 2019, the DRIF clocks have been renamed as follows:

DRIF0 to DRIF00
DRIF1 to DRIF01
DRIF2 to DRIF10
DRIF3 to DRIF11
DRIF4 to DRIF20
DRIF5 to DRIF21
DRIF6 to DRIF30
DRIF7 to DRIF31

Therefore, this patch renames the DRIF clocks from DRIFn to DRIFmm.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC

The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
DMA transfers are:

Channel R-Car H3 R-Car M3-W R

clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC

The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
DMA transfers are:

Channel R-Car H3 R-Car M3-W R-Car M3-N R-Car E3
---------------------------------------------------------------
Audio-DMAC0 S1D2 S1D2 S1D2 S1D2
Audio-DMAC1 S1D2 S1D2 S1D2 -

As a result, change the parent clocks of the Audio-DMAC{0,1} module
clocks on R-Car H3, R-Car M3-W, and R-Car M3-N to S1D2, and change the
parent clock of the Audio-DMAC0 module on R-Car E3 to S1D2.

NOTE: This information will be reflected in a future revision of the
R-Car Gen3 Hardware Manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car D3, RZ/G2M, and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: rcar-gen3: Correct parent clock of HS-USB

According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the HS-USB module
clocks o

clk: renesas: rcar-gen3: Correct parent clock of HS-USB

According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the HS-USB module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI

According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
cl

clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI

According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: r8a77990: Add Z2 clock

Adds support for R-Car E3 (r8a77990) Z2 clock.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: reworked changelog; rebased]
Signed-off-by:

clk: renesas: r8a77990: Add Z2 clock

Adds support for R-Car E3 (r8a77990) Z2 clock.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: reworked changelog; rebased]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: r8a77990: Correct parent clock of DU

According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car E3 is S1D1.

Signed-off-by: Takeshi Kihara

clk: renesas: r8a77990: Correct parent clock of DU

According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car E3 is S1D1.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 3570a2af473789c5 ("clk: renesas: cpg-mssr: Add support for R-Car E3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

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clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment

PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+re

clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment

PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: r8a77990: Add missing I2C7 clock

When trying to use I2C7 on R-Car E3:

renesas-cpg-mssr e6150000.clock-controller: Cannot get module clock 1003: -2
i2c-rcar e6690000.i2c: faile

clk: renesas: r8a77990: Add missing I2C7 clock

When trying to use I2C7 on R-Car E3:

renesas-cpg-mssr e6150000.clock-controller: Cannot get module clock 1003: -2
i2c-rcar e6690000.i2c: failed to add to PM domain always-on: -2
i2c-rcar: probe of e6690000.i2c failed with error -2

Unlike other R-Car Gen3 SoCs, R-Car E3 has more than 7 I2C bus
interfaces. Add the forgotten module clock for the 8th instance to fix
this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>

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clk: renesas: r8a77990: Correct RCLK handling

According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car E3 has the
RCLK Frequency Control Register (RCKCR), which determines the OSC and
RINT predivider

clk: renesas: r8a77990: Correct RCLK handling

According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car E3 has the
RCLK Frequency Control Register (RCKCR), which determines the OSC and
RINT predivider values, and selection of the RCLK clock source between
RINT and the On-Chip Oscillator.

Hence change the OSC and RINT clock definitions to use the RCKCR
divider, and add the missing On-Chip Oscillator and RCLK clock source
switching logic.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: cpg-mssr: Add support for R-Car E3

Initial support for R-Car E3 (r8a77990), including core and module
clocks.

Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual:
H

clk: renesas: cpg-mssr: Add support for R-Car E3

Initial support for R-Car E3 (r8a77990), including core and module
clocks.

Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual:
Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018".

Inspried by patches by Takeshi Kihara in the BSP.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Mark RWDT clocks as critical

Ensures RWDT remains alert throughout the boot process if enabled.

This patch applies the change to the following SoCs: r8a7795

clk: renesas: rcar-gen3: Mark RWDT clocks as critical

Ensures RWDT remains alert throughout the boot process if enabled.

This patch applies the change to the following SoCs: r8a77950, r8a77951,
r8a77960, r8a77961, r8a77965, r8a77970, r8a77980, r8a77990 and r8a77995.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200616162626.27944-3-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Add CCREE clocks

Add the CryptoCell module clocks and their parents for the CryptoCell
instances in the various Renesas R-Car Gen3 SoCs that do not have
supp

clk: renesas: rcar-gen3: Add CCREE clocks

Add the CryptoCell module clocks and their parents for the CryptoCell
instances in the various Renesas R-Car Gen3 SoCs that do not have
support for them yet in their clock drivers (M3-W/W+, M3-N, E3, D3).

The R-Car H3 clock driver already supports these clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200124133137.15921-1-geert+renesas@glider.be

show more ...

clk: renesas: r8a77990: Add CMM clocks

Add clock definitions for CMM units on Renesas R-Car E3.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinc

clk: renesas: r8a77990: Add CMM clocks

Add clock definitions for CMM units on Renesas R-Car E3.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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clk: renesas: rcar-gen3: Rename DRIF clocks

According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
12, 2019, the DRIF clocks have been renamed as follows:

D

clk: renesas: rcar-gen3: Rename DRIF clocks

According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
12, 2019, the DRIF clocks have been renamed as follows:

DRIF0 to DRIF00
DRIF1 to DRIF01
DRIF2 to DRIF10
DRIF3 to DRIF11
DRIF4 to DRIF20
DRIF5 to DRIF21
DRIF6 to DRIF30
DRIF7 to DRIF31

Therefore, this patch renames the DRIF clocks from DRIFn to DRIFmm.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC

The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
DMA transfers are:

Channel R-Car H

clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC

The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
DMA transfers are:

Channel R-Car H3 R-Car M3-W R-Car M3-N R-Car E3
---------------------------------------------------------------
Audio-DMAC0 S1D2 S1D2 S1D2 S1D2
Audio-DMAC1 S1D2 S1D2 S1D2 -

As a result, change the parent clocks of the Audio-DMAC{0,1} module
clocks on R-Car H3, R-Car M3-W, and R-Car M3-N to S1D2, and change the
parent clock of the Audio-DMAC0 module on R-Car E3 to S1D2.

NOTE: This information will be reflected in a future revision of the
R-Car Gen3 Hardware Manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car D3, RZ/G2M, and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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