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/openbmc/linux/drivers/clk/socfpga/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \
3 clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
4 obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \
5 clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \
6 clk-agilex.o
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3188.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
19 #include <dt-bindings/clock/rk3188-cru.h>
20 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
52 /* PLL CON0 */
55 /* PLL CON1 */
58 /* PLL CON2 */
61 /* PLL CON3 */
[all …]
H A Dclk_rk3036.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
16 #include <dt-bindings/clock/rk3036-cru.h>
27 ((input_rate) / (output_rate) - 1);
37 #hz "Hz cannot be hit with PLL "\
48 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
54 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ in rkclk_set_pll()
56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
[all …]
H A Dclk_rk3288.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
50 /* PLL CON0 */
53 /* PLL CON1 */
56 /* PLL CON2 */
59 /* PLL CON3 */
[all …]
H A Dclk_rk322x.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
16 #include <dt-bindings/clock/rk3228-cru.h>
34 #hz "Hz cannot be hit with PLL "\
45 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
51 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", in rkclk_set_pll()
52 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
53 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
[all …]
H A Dclk_rk3128.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3128-cru.h>
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
48 debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n", in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
55 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
[all …]
/openbmc/qemu/include/hw/misc/
H A Dbcm2835_cprman_internals.h6 * SPDX-License-Identifier: GPL-2.0-or-later
15 #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
16 #define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
17 #define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
18 #define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
112 /* PLL channels */
239 /* PLL init info */
286 CprmanPllState *pll, in set_pll_init_info() argument
289 pll->id = id; in set_pll_init_info()
290 pll->reg_cm = &s->regs[PLL_INIT_INFO[id].cm_offset]; in set_pll_init_info()
[all …]
/openbmc/linux/drivers/clk/tegra/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += clk.o
3 obj-y += clk-audio-sync.o
4 obj-y += clk-device.o
5 obj-y += clk-dfll.o
6 obj-y += clk-divider.o
7 obj-y += clk-periph.o
8 obj-y += clk-periph-fixed.o
9 obj-y += clk-periph-gate.o
10 obj-y += clk-pll.o
[all …]
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9263.dtsi2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
18 interrupt-parent = <&aic>;
40 compatible = "arm,arm926ej-s";
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
[all …]
H A Dat91sam9260.dtsi2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
20 interrupt-parent = <&aic>;
41 compatible = "arm,arm926ej-s";
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
[all …]
H A Dat91sam9n12.dtsi2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
20 interrupt-parent = <&aic>;
42 compatible = "arm,arm926ej-s";
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_arria10.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Intel Corporation
11 #include <dm/device-internal.h>
80 { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
81 { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
82 { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
83 { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
84 { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
85 { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
86 { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) },
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
28 #include "ccu-sun4i-a10.h"
38 .hw.init = CLK_HW_INIT("pll-core",
46 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
48 * pll audio).
50 * With sigma-delta modulation for fractional-N on the audio PLL,
73 .hw.init = CLK_HW_INIT("pll-audio-base",
91 .hw.init = CLK_HW_INIT("pll-video0",
106 .hw.init = CLK_HW_INIT("pll-ve",
[all …]
H A Dccu-sun8i-a23.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
25 #include "ccu-sun8i-a23-a33.h"
39 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
46 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
48 * pll audio).
50 * With sigma-delta modulation for fractional-N on the audio PLL,
64 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
74 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
86 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
[all …]
H A Dccu-sun8i-a33.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
37 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
46 * pll audio).
48 * With sigma-delta modulation for fractional-N on the audio PLL,
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
84 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
[all …]
H A Dccu-sun8i-a83t.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
22 #include "ccu-sun8i-a83t.h"
29 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
44 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
65 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
66 * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
92 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
[all …]
H A Dccu-sun5i.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
34 .hw.init = CLK_HW_INIT("pll-core",
42 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * pll audio).
46 * With sigma-delta modulation for fractional-N on the audio PLL,
74 .hw.init = CLK_HW_INIT("pll-audio-base",
91 .hw.init = CLK_HW_INIT("pll-video0",
106 .hw.init = CLK_HW_INIT("pll-ve",
[all …]
H A Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
30 #include "ccu-sun6i-a31.h"
32 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
42 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * pll audio).
46 * With sigma-delta modulation for fractional-N on the audio PLL,
[all …]
H A Dccu-suniv-f1c100s.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include "ccu-suniv-f1c100s.h"
39 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
46 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
48 * pll audio).
55 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
63 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
75 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
87 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
29 * memory clock PLL.
47 CLOCK_TYPE_NONE = -1, /* invalid clock type */
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
67 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
73 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_pic32.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
15 #include <dt-bindings/clock/microchip,clock.h>
70 /* Memory PLL */
96 v = readl(priv->iobase + SPLLCON); in pic32_get_pll_rate()
122 v = readl(priv->iobase + OSCCON); in pic32_get_sysclk()
149 static ulong pic32_get_pbclk(struct pic32_clk_priv *priv, int periph) in pic32_get_pbclk() argument
154 WARN_ON((periph < PB1CLK) || (periph > PB7CLK)); in pic32_get_pbclk()
158 reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10; in pic32_get_pbclk()
169 static ulong pic32_set_refclk(struct pic32_clk_priv *priv, int periph, in pic32_set_refclk() argument
[all …]
/openbmc/u-boot/include/
H A Dstm32_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
61 u32 pllcfgr; /* RCC PLL configuration */
78 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
79 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
80 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
82 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
83 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
29 * memory clock PLL.
47 CLOCK_TYPE_NONE = -1, /* invalid clock type */
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
67 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
73 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-ccu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#clock-cells":
17 "#reset-cells":
22 - allwinner,sun4i-a10-ccu
23 - allwinner,sun5i-a10s-ccu
[all …]

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