Lines Matching +full:pll +full:- +full:periph
1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
19 #include <dt-bindings/clock/rk3188-cru.h>
20 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
52 /* PLL CON0 */
55 /* PLL CON1 */
58 /* PLL CON2 */
61 /* PLL CON3 */
76 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
89 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
91 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
92 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
94 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", in rkclk_set_pll()
95 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
98 (div->no == 1 || !(div->no % 2))); in rkclk_set_pll()
101 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
103 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
105 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); in rkclk_set_pll()
106 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
109 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
114 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
145 return -EINVAL; in rkclk_configure_ddr()
148 /* pll enter slow-mode */ in rkclk_configure_ddr()
149 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
154 /* wait for pll lock */ in rkclk_configure_ddr()
155 while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) in rkclk_configure_ddr()
158 /* PLL enter normal-mode */ in rkclk_configure_ddr()
159 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
194 return -EINVAL; in rkclk_configure_cpu()
197 /* pll enter slow-mode */ in rkclk_configure_cpu()
198 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
203 /* waiting for pll lock */ in rkclk_configure_cpu()
204 while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK)) in rkclk_configure_cpu()
208 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
213 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_configure_cpu()
217 /* PLL enter normal-mode */ in rkclk_configure_cpu()
218 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
224 /* Get pll rate by id */
231 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate() local
238 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
245 con = readl(&pll->con0); in rkclk_pll_get_rate()
248 con = readl(&pll->con1); in rkclk_pll_get_rate()
259 int periph) in rockchip_mmc_get_clk() argument
264 switch (periph) { in rockchip_mmc_get_clk()
267 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
272 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
277 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
281 return -EINVAL; in rockchip_mmc_get_clk()
288 int periph, uint freq) in rockchip_mmc_set_clk() argument
294 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1; in rockchip_mmc_set_clk()
297 switch (periph) { in rockchip_mmc_set_clk()
300 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
306 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
312 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
317 return -EINVAL; in rockchip_mmc_set_clk()
320 return rockchip_mmc_get_clk(cru, gclk_rate, periph); in rockchip_mmc_set_clk()
324 int periph) in rockchip_spi_get_clk() argument
329 switch (periph) { in rockchip_spi_get_clk()
331 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
335 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
339 return -EINVAL; in rockchip_spi_get_clk()
346 int periph, uint freq) in rockchip_spi_set_clk() argument
348 int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; in rockchip_spi_set_clk()
351 switch (periph) { in rockchip_spi_set_clk()
354 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
360 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
365 return -EINVAL; in rockchip_spi_set_clk()
368 return rockchip_spi_get_clk(cru, gclk_rate, periph); in rockchip_spi_set_clk()
377 /* pll enter slow-mode */ in rkclk_init()
378 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
384 /* init pll */ in rkclk_init()
388 /* waiting for pll lock */ in rkclk_init()
389 while ((readl(&grf->soc_status0) & in rkclk_init()
395 * cpu clock pll source selection and in rkclk_init()
399 aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1; in rkclk_init()
402 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
415 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
424 * peri clock pll source selection and in rkclk_init()
427 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
438 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
447 /* PLL enter normal-mode */ in rkclk_init()
448 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
460 struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); in rk3188_clk_get_rate()
463 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3188_clk_get_rate()
464 switch (clk->id) { in rk3188_clk_get_rate()
466 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3188_clk_get_rate()
474 new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, in rk3188_clk_get_rate()
475 clk->id); in rk3188_clk_get_rate()
479 new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, in rk3188_clk_get_rate()
480 clk->id); in rk3188_clk_get_rate()
489 return -ENOENT; in rk3188_clk_get_rate()
497 struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); in rk3188_clk_set_rate()
498 struct rk3188_cru *cru = priv->cru; in rk3188_clk_set_rate()
501 switch (clk->id) { in rk3188_clk_set_rate()
503 new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, in rk3188_clk_set_rate()
504 priv->has_bwadj); in rk3188_clk_set_rate()
507 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, in rk3188_clk_set_rate()
508 priv->has_bwadj); in rk3188_clk_set_rate()
517 clk->id, rate); in rk3188_clk_set_rate()
522 clk->id, rate); in rk3188_clk_set_rate()
525 return -ENOENT; in rk3188_clk_set_rate()
541 priv->cru = dev_read_addr_ptr(dev); in rk3188_clk_ofdata_to_platdata()
552 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3188_clk_probe()
553 if (IS_ERR(priv->grf)) in rk3188_clk_probe()
554 return PTR_ERR(priv->grf); in rk3188_clk_probe()
555 priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0; in rk3188_clk_probe()
561 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); in rk3188_clk_probe()
564 rkclk_init(priv->cru, priv->grf, priv->has_bwadj); in rk3188_clk_probe()
583 priv->glb_srst_fst_value = offsetof(struct rk3188_cru, in rk3188_clk_bind()
585 priv->glb_srst_snd_value = offsetof(struct rk3188_cru, in rk3188_clk_bind()
587 sys_child->priv = priv; in rk3188_clk_bind()
601 { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
602 { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },