6  * SPDX-License-Identifier: GPL-2.0-or-later
15 #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
16 #define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
17 #define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
18 #define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
112 /* PLL channels */
239 /* PLL init info */
286                                      CprmanPllState *pll,  in set_pll_init_info()  argument
289     pll->id = id;  in set_pll_init_info()
290     pll->reg_cm = &s->regs[PLL_INIT_INFO[id].cm_offset];  in set_pll_init_info()
291     pll->reg_a2w_ctrl = &s->regs[PLL_INIT_INFO[id].a2w_ctrl_offset];  in set_pll_init_info()
292     pll->reg_a2w_ana = &s->regs[PLL_INIT_INFO[id].a2w_ana_offset];  in set_pll_init_info()
293     pll->prediv_mask = PLL_INIT_INFO[id].prediv_mask;  in set_pll_init_info()
294     pll->reg_a2w_frac = &s->regs[PLL_INIT_INFO[id].a2w_frac_offset];  in set_pll_init_info()
298 /* PLL channel init info */
326         .name = "plla-dsi0",
330         .name = "plla-core",
334         .name = "plla-per",
338         .name = "plla-ccp2",
343         .name = "pllc-core2",
347         .name = "pllc-core1",
351         .name = "pllc-per",
355         .name = "pllc-core0",
360         .name = "plld-dsi0",
364         .name = "plld-core",
368         .name = "plld-per",
372         .name = "plld-dsi1",
377         .name = "pllh-aux",
382         .name = "pllh-rcal",
387         .name = "pllh-pix",
393         .name = "pllb-arm",
406     channel->id = id;  in set_pll_channel_init_info()
407     channel->parent = PLL_CHANNEL_INIT_INFO[id].parent;  in set_pll_channel_init_info()
408     channel->reg_cm = &s->regs[PLL_CHANNEL_INIT_INFO[id].cm_offset];  in set_pll_channel_init_info()
409     channel->hold_mask = PLL_CHANNEL_INIT_INFO[id].cm_hold_mask;  in set_pll_channel_init_info()
410     channel->load_mask = PLL_CHANNEL_INIT_INFO[id].cm_load_mask;  in set_pll_channel_init_info()
411     channel->reg_a2w_ctrl = &s->regs[PLL_CHANNEL_INIT_INFO[id].a2w_ctrl_offset];  in set_pll_channel_init_info()
412     channel->fixed_divider = PLL_CHANNEL_INIT_INFO[id].fixed_divider;  in set_pll_channel_init_info()
418     size_t cm_offset; /* cm_offset[0]->CM_CTL, cm_offset[1]->CM_DIV */
438         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll a */        \
439         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c */        \
440         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll d */        \
441         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll h */        \
442         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core1 */ \
443         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core2 */ \
461 /* All the PLL "core" channels */
476 /* All the PLL "per" channels */
492  * The DSI0 channels. This one got an intermediate mux between the PLL channels
574         FILL_CLOCK_MUX_INIT_INFO(CAM0, periph),
580         FILL_CLOCK_MUX_INIT_INFO(CAM1, periph),
602         FILL_CLOCK_MUX_INIT_INFO(DPI, periph),
608         FILL_CLOCK_MUX_INIT_INFO(GP0, periph),
614         FILL_CLOCK_MUX_INIT_INFO(GP1, periph),
620         FILL_CLOCK_MUX_INIT_INFO(GP2, periph),
626         FILL_CLOCK_MUX_INIT_INFO(HSM, periph),
638         FILL_CLOCK_MUX_INIT_INFO(PCM, periph),
644         FILL_CLOCK_MUX_INIT_INFO(PWM, periph),
650         FILL_CLOCK_MUX_INIT_INFO(SLIM, periph),
656         FILL_CLOCK_MUX_INIT_INFO(SMI, periph),
688         FILL_CLOCK_MUX_INIT_INFO(UART, periph),
694         FILL_CLOCK_MUX_INIT_INFO(VEC, periph),
714         FILL_CLOCK_MUX_INIT_INFO(AVEO, periph),
720         FILL_CLOCK_MUX_INIT_INFO(EMMC, periph),
743     mux->id = id;  in set_clock_mux_init_info()
744     mux->reg_ctl = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset];  in set_clock_mux_init_info()
745     mux->reg_div = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset + 1];  in set_clock_mux_init_info()
746     mux->int_bits = CLOCK_MUX_INIT_INFO[id].int_bits;  in set_clock_mux_init_info()
747     mux->frac_bits = CLOCK_MUX_INIT_INFO[id].frac_bits;  in set_clock_mux_init_info()
803      * Even though a PLL channel has a CM register, it shares it with its
804      * parent PLL. The parent already takes care of the reset value.