1 // SPDX-License-Identifier: GPL-2.0+
3  * (C) Copyright 2010-2015
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
29  * memory clock PLL.
47 	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
64 	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC),
67 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO),
70 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
73 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE),
76 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
79 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
82 	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC),
85 	{ CLK(AUDIO),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
88 	{ CLK(AUDIO),	CLK(SFROM32KHZ),	CLK(PERIPH),	CLK(OSC),
91 	{ CLK(PERIPH),	CLK(MEMORY),	CLK(DISPLAY),	CLK(AUDIO),
94 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
141 	TYPE(PERIPHC_MIPI,	CLOCK_TYPE_PCMT),	/* MIPI base-band HSI */
220  *	SPDIF - which is both 0x08 and 0x0c
223 #define NONE(name) (-1)
428  * PLL divider shift/mask tables for all PLL IDs.
433 	 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
434 	 *       If lock_ena or lock_det are >31, they're not used in that PLL.
468 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
486 		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];  in get_periph_source_reg()
490 	assert(internal_id != -1);  in get_periph_source_reg()
492 		internal_id -= PERIPHC_VW_FIRST;  in get_periph_source_reg()
493 		return &clkrst->crc_clk_src_vw[internal_id];  in get_periph_source_reg()
495 		return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
504 		return -1;  in get_periph_clock_info()
508 		return -1;  in get_periph_clock_info()
512 		return -1;  in get_periph_clock_info()
550  * @param source	PLL id of required parent clock
553  * @return mux value (0-4, or -1 if not found)
569 	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,  in get_periph_clock_source()
571 	return -1;  in get_periph_clock_source()
584 		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
586 		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];  in clock_set_enable()
605 		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
607 		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];  in reset_set_enable()
665 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);  in clock_early_init()
698 	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);  in clock_early_init()
702 	setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));  in clock_early_init()
707 	data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);  in clock_early_init()
708 	data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);  in clock_early_init()
709 	writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);  in clock_early_init()
726 	writel(freq, &sysctr->cntfid0);  in arch_timer_init()
728 	val = readl(&sysctr->cntcr);  in arch_timer_init()
730 	writel(val, &sysctr->cntcr);  in arch_timer_init()
754 	{ -1, },