1 // SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
15 #include <dt-bindings/clock/microchip,clock.h>
70 /* Memory PLL */
96 	v = readl(priv->iobase + SPLLCON);  in pic32_get_pll_rate()
122 	v = readl(priv->iobase + OSCCON);  in pic32_get_sysclk()
149 static ulong pic32_get_pbclk(struct pic32_clk_priv *priv, int periph)  in pic32_get_pbclk()  argument
154 	WARN_ON((periph < PB1CLK) || (periph > PB7CLK));  in pic32_get_pbclk()
158 	reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10;  in pic32_get_pbclk()
169 static ulong pic32_set_refclk(struct pic32_clk_priv *priv, int periph,  in pic32_set_refclk()  argument
176 	WARN_ON((periph < REF1CLK) || (periph > REF5CLK));  in pic32_set_refclk()
189 		frac -= (u64)(div << 9);  in pic32_set_refclk()
193 	reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;  in pic32_set_refclk()
229 static ulong pic32_get_refclk(struct pic32_clk_priv *priv, int periph)  in pic32_get_refclk()  argument
235 	WARN_ON((periph < REF1CLK) || (periph > REF5CLK));  in pic32_get_refclk()
237 	reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;  in pic32_get_refclk()
286 	v = readl(priv->syscfg_base + CFGMPLL);  in pic32_get_mpll_rate()
309 	writel(v, priv->syscfg_base + CFGMPLL);  in pic32_mpll_init()
313 	return wait_for_bit_le32(priv->syscfg_base + CFGMPLL, mask,  in pic32_mpll_init()
319 	const void *blob = gd->fdt_blob;  in pic32_clk_init()
331 			 "microchip,refo%d-frequency", i - REF1CLK + 1);  in pic32_clk_init()
337 	/* Memory PLL */  in pic32_clk_init()
343 	struct pic32_clk_priv *priv = dev_get_priv(clk->dev);  in pic32_get_rate()
346 	switch (clk->id) {  in pic32_get_rate()
348 		rate = pic32_get_pbclk(priv, clk->id);  in pic32_get_rate()
351 		rate = pic32_get_refclk(priv, clk->id);  in pic32_get_rate()
369 	struct pic32_clk_priv *priv = dev_get_priv(clk->dev);  in pic32_set_rate()
372 	switch (clk->id) {  in pic32_set_rate()
375 		pic32_set_refclk(priv, clk->id, pll_hz, rate, ROCLK_SRC_SPLL);  in pic32_set_rate()
395 	addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",  in pic32_clk_probe()
398 		return -EINVAL;  in pic32_clk_probe()
400 	priv->iobase = ioremap(addr, size);  in pic32_clk_probe()
401 	if (!priv->iobase)  in pic32_clk_probe()
402 		return -EINVAL;  in pic32_clk_probe()
404 	priv->syscfg_base = pic32_get_syscfg_base();  in pic32_clk_probe()
413 	{ .compatible = "microchip,pic32mzda-clk"},