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/openbmc/linux/drivers/ata/
H A Dpata_artop.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_artop.c - ARTOP ATA controller driver
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
11 * driver by Thibaut VARENE <varenet@parisc-linux.org>
43 * artop62x0_pre_reset - probe begin
57 struct ata_port *ap = link->ap; in artop62x0_pre_reset()
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in artop62x0_pre_reset()
61 if ((pdev->device & 1) && in artop62x0_pre_reset()
62 !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) in artop62x0_pre_reset()
63 return -ENOENT; in artop62x0_pre_reset()
[all …]
H A Dpata_atiixp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_atiixp.c - ATI PATA for new ATA layer
5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
9 * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
39 /* Board has onboard PATA<->SATA converters */
40 .ident = "MSI E350DM-E33",
43 DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"),
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in atiixp_cable_detect()
58 raw detection not play follow the bios mode guess */ in atiixp_cable_detect()
59 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); in atiixp_cable_detect()
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H A Dpata_cs5520.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * PIO mode and smarter silicon.
11 * drive for the right PIO mode. We must also ignore all the blacklists
13 * further we can do DMA on PIO only drives.
52 * cs5520_set_timings - program PIO timings
55 * @pio: PIO ID
57 * Program the PIO mode timings for the controller according to the pio
61 static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio) in cs5520_set_timings() argument
63 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cs5520_set_timings()
64 int slave = adev->devno; in cs5520_set_timings()
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H A Dpata_optidma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_optidma.c - Opti DMA PATA for new ATA layer
6 * The Opti DMA controllers are related to the older PIO PCI controllers
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
48 * optidma_pre_reset - probe begin
57 struct ata_port *ap = link->ap; in optidma_pre_reset()
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in optidma_pre_reset()
63 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) in optidma_pre_reset()
64 return -ENOENT; in optidma_pre_reset()
70 * optidma_unlock - unlock control registers
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H A Dpata_it821x.c2 * pata_it821x.c - IT821x PATA for new ATA layer
23 * modes. In pass through mode then it is an IDE controller. In its smart
24 * mode its actually quite a capable hardware raid controller disguised
25 * as an IDE controller. Smart mode only understands DMA read/write and
27 * in other respects but lacks the raid mode.
35 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
37 * o Smart mode without RAID doesn't clear all the necessary identify
41 * - In pass through mode we do all the work you would expect
42 * - In smart mode the clocking set up is done by the controller generally
44 * - There are a few extra vendor commands that actually talk to the
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H A Dpata_pdc2027x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
15 * as Documentation/driver-api/libata.rst
75 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
76 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
77 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
78 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
79 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
85 { 0xdf, 0x5f }, /* MDMA mode 0 */
86 { 0x6b, 0x27 }, /* MDMA mode 1 */
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H A Dpata_efar.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_efar.c - EFAR PIIX clone controller driver
6 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
11 * Intel ICH controllers the EFAR widened the UDMA mode register bits
29 * efar_pre_reset - Enable bits
43 struct ata_port *ap = link->ap; in efar_pre_reset()
44 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in efar_pre_reset()
46 if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no])) in efar_pre_reset()
47 return -ENOENT; in efar_pre_reset()
53 * efar_cable_detect - check for 40/80 pin
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H A Dpata_sch.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sch.c - Intel SCH PATA controllers
10 * Intel SCH (AF82US15W, AF82US15L, AF82UL11L) chipsets -- see spec at:
31 PM = 0x07, /* PIO Mode Bit Mask */
32 MDM = (0x03 << 8), /* Multi-word DMA Mode Bit Mask */
33 UDM = (0x07 << 16), /* Ultra DMA Mode Bit Mask */
80 MODULE_DESCRIPTION("SCSI low-level driver for Intel SCH PATA controllers");
86 * sch_set_piomode - Initialize host controller PATA PIO timings
90 * Set PIO mode for device, in host controller PCI config space.
98 unsigned int pio = adev->pio_mode - XFER_PIO_0; in sch_set_piomode() local
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H A Dpata_sl82c105.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sl82c105.c - SL82C105 PATA for new ATA layer
14 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
16 * method as the PIO method is always called and will set the right PIO
45 * sl82c105_pre_reset - probe begin
58 struct ata_port *ap = link->ap; in sl82c105_pre_reset()
59 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in sl82c105_pre_reset()
61 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) in sl82c105_pre_reset()
62 return -ENOENT; in sl82c105_pre_reset()
68 * sl82c105_configure_piomode - set chip PIO timing
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H A Dpata_rdc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pata_rdc - Driver for later RDC PATA controllers
6 * INCITS 370-2004 (1510D): ATA Host Adapter Standards
30 * rdc_pata_cable_detect - Probe host controller cable detect info
42 struct rdc_host_priv *hpriv = ap->host->private_data; in rdc_pata_cable_detect()
46 mask = 0x30 << (2 * ap->port_no); in rdc_pata_cable_detect()
47 if ((hpriv->saved_iocfg & mask) == 0) in rdc_pata_cable_detect()
53 * rdc_pata_prereset - prereset for PATA host controller
62 struct ata_port *ap = link->ap; in rdc_pata_prereset()
63 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in rdc_pata_prereset()
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H A Dpata_pdc202xx_old.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc2026x_cable_detect()
33 if (cis & (1 << (10 + ap->port_no))) in pdc2026x_cable_detect()
41 iowrite8(tf->command, ap->ioaddr.command_addr); in pdc202xx_exec_command()
47 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_irq_check()
51 if (ap->port_no) { in pdc202xx_irq_check()
67 * pdc202xx_configure_piomode - set chip PIO timing
70 * @pio: PIO mode
72 * Called to do the PIO mode setup. Our timing registers are shared
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H A Dpata_hpt366.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
35 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
37 * 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
44 * 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
45 * 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
49 * 30 PIO_MST enable. If set, the chip is in bus master mode during
50 * PIO xfer.
112 * hpt36x_find_mode - find the hpt36x timing
114 * @speed: transfer mode
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H A Dpata_oldpiix.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_oldpiix.c - Intel PATA/SATA controllers
31 * oldpiix_pre_reset - probe begin
40 struct ata_port *ap = link->ap; in oldpiix_pre_reset()
41 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in oldpiix_pre_reset()
47 if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no])) in oldpiix_pre_reset()
48 return -ENOENT; in oldpiix_pre_reset()
54 * oldpiix_set_piomode - Initialize host controller PATA PIO timings
58 * Set PIO mode for device, in host controller PCI config space.
66 unsigned int pio = adev->pio_mode - XFER_PIO_0; in oldpiix_set_piomode() local
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H A Dpata_radisys.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_radisys.c - Intel PATA/SATA controllers
30 * radisys_set_piomode - Initialize host controller PATA PIO timings
34 * Set PIO mode for device, in host controller PCI config space.
42 unsigned int pio = adev->pio_mode - XFER_PIO_0; in radisys_set_piomode() local
43 struct pci_dev *dev = to_pci_dev(ap->host->dev); in radisys_set_piomode()
48 * See Intel Document 298600-004 for the timing programing rules in radisys_set_piomode()
61 if (pio > 0) in radisys_set_piomode()
71 idetm_data |= (control << (4 * adev->devno)); in radisys_set_piomode()
72 idetm_data |= (timings[pio][0] << 12) | in radisys_set_piomode()
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H A Dpata_it8213.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_it8213.c - iTE Tech. Inc. IT8213 PATA driver
25 * it8213_pre_reset - probe begin
38 struct ata_port *ap = link->ap; in it8213_pre_reset()
39 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in it8213_pre_reset()
40 if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no])) in it8213_pre_reset()
41 return -ENOENT; in it8213_pre_reset()
47 * it8213_cable_detect - check for 40/80 pin
56 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in it8213_cable_detect()
65 * it8213_set_piomode - Initialize host controller PATA PIO timings
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/openbmc/linux/arch/mips/sgi-ip27/
H A Dip27-hubio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc.
6 * Support functions for the HUB ASIC - mostly PIO mapping related.
22 * hub_pio_map - establish a HUB PIO mapping
24 * @hub: hub to perform PIO mapping on
25 * @widget: widget ID to perform PIO mapping for
27 * @size: size of the PIO mapping
35 /* use small-window mapping if possible */ in hub_pio_map()
40 printk(KERN_WARNING "PIO mapping at hub %d widget %d addr 0x%lx" in hub_pio_map()
46 xtalk_addr &= ~(BWIN_SIZE-1); in hub_pio_map()
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/openbmc/linux/drivers/net/wireless/broadcom/b43legacy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Broadcom 43xx-legacy wireless support (mac80211 stack)"
18 b43-fwcutter.
23 # Auto-select SSB PCI-HOST support, if possible
31 # Auto-select SSB PCICORE driver, if possible
46 # This config option automatically enables b43 HW-RNG support,
47 # if the HW-RNG core is enabled.
54 bool "Broadcom 43xx-legacy debugging"
70 prompt "Broadcom 43xx-legacy data transfer mode"
75 bool "DMA + PIO"
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/openbmc/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h40 u32 _unused0[0x1000/4 - 2]; /* padding */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
73 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
77 #define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
84 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
95 volatile u32 pconfig; /* PIO configuration register */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
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/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a-bananapi-bpi-r3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
18 model = "Bananapi BPI-R3";
19 chassis-type = "embedded";
20 compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
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/openbmc/linux/Documentation/spi/
H A Dpxa2xx.rst7 (see Documentation/spi/spi-summary.rst). The driver has the following features
9 - Support for any PXA2xx and compatible SSP.
10 - SSP PIO and SSP DMA data transfers.
11 - External and Internal (SSPFRM) chip selects.
12 - Per slave device (chip) configuration.
13 - Full suspend, freeze, resume support.
21 -----------------------------------
23 arch/.../mach-*/board-*.c as a "platform device". The master configuration
44 ------------------
66 .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
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/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n-bananapi-bpi-r2.dts2 * Copyright 2017-2018 Sean Wang <sean.wang@mediatek.com>
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 model = "Bananapi BPI-R2";
14 compatible = "bananapi,bpi-r2", "mediatek,mt7623";
21 stdout-path = "serial2:115200n8";
25 compatible = "hdmi-connector";
28 ddc-i2c-bus = <&hdmiddc0>;
32 remote-endpoint = <&hdmi0_out>;
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/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Dhubni.h8 * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
35 #define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */
36 #define NI_VECTOR 0x600208 /* Vector PIO route */
37 #define NI_VECTOR_DATA 0x600210 /* Vector PIO data */
38 #define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */
39 #define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */
40 #define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */
41 #define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */
43 #define NI_IO_PROTECT 0x600400 /* PIO protection bits */
44 #define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */
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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-at91.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include "pinctrl-at91.h"
42 * @pioc_hwirq: PIO bank interrupt identifier on AIC
43 * @pioc_virq: PIO bank Linux virtual interrupt
44 * @regbase: PIO bank virtual address
114 * struct at91_pmx_func - describes AT91 pinmux functions
134 * struct at91_pmx_pin - describes an At91 pin mux
137 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
148 * struct at91_pin_group - describes an At91 pin group
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
9 Pull Up (PU) are driven by the related PIO block.
11 ST pinctrl driver controls PIO multiplexing block and also interacts with
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsmsc,usb3503.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SMSC USB3503 High-Speed Hub Controller
10 - Dongjin Kim <tobetter@gmail.com>
15 - smsc,usb3503
16 - smsc,usb3503a
17 - smsc,usb3803
22 connect-gpios:
27 intn-gpios:
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