Lines Matching +full:pio +full:- +full:mode

1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
15 * as Documentation/driver-api/libata.rst
75 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
76 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
77 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
78 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
79 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
85 { 0xdf, 0x5f }, /* MDMA mode 0 */
86 { 0x6b, 0x27 }, /* MDMA mode 1 */
87 { 0x69, 0x25 }, /* MDMA mode 2 */
93 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
94 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
95 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
96 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
97 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
98 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
99 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
170 * port_mmio - Get the MMIO address of PDC2027x extended registers
176 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset; in port_mmio()
180 * dev_mmio - Get the MMIO address of PDC2027x extended registers
187 u8 adj = (adev->devno) ? 0x08 : 0x00; in dev_mmio()
192 * pdc2027x_cable_detect - Probe host controller cable detect info
210 ata_port_dbg(ap, "No cable or 80-conductor cable\n"); in pdc2027x_cable_detect()
214 ata_port_info(ap, DRV_NAME ":40-conductor cable detected\n"); in pdc2027x_cable_detect()
219 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
228 * pdc2027x_prereset - prereset for PATA host controller
241 if (!pdc2027x_port_enabled(link->ap)) in pdc2027x_prereset()
242 return -ENOENT; in pdc2027x_prereset()
247 * pdc2027x_mode_filter - mode selection filter
259 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL) in pdc2027x_mode_filter()
263 ata_id_c_string(pair->id, model_num, ATA_ID_PROD, in pdc2027x_mode_filter()
266 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6) in pdc2027x_mode_filter()
273 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
277 * Set PIO mode for device.
285 unsigned int pio = adev->pio_mode - XFER_PIO_0; in pdc2027x_set_piomode() local
288 ata_port_dbg(ap, "adev->pio_mode[%X]\n", adev->pio_mode); in pdc2027x_set_piomode()
291 if (pio > 4) { in pdc2027x_set_piomode()
292 ata_port_err(ap, "Unknown pio mode [%d] ignored\n", pio); in pdc2027x_set_piomode()
297 /* Set the PIO timing registers using value table for 133MHz */ in pdc2027x_set_piomode()
298 ata_port_dbg(ap, "Set pio regs... \n"); in pdc2027x_set_piomode()
302 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | in pdc2027x_set_piomode()
303 (pdc2027x_pio_timing_tbl[pio].value1 << 8); in pdc2027x_set_piomode()
308 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); in pdc2027x_set_piomode()
311 ata_port_dbg(ap, "Set to pio mode[%u] \n", pio); in pdc2027x_set_piomode()
315 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
319 * Set UDMA mode for device.
326 unsigned int dma_mode = adev->dma_mode; in pdc2027x_set_dmamode()
353 ata_port_dbg(ap, "Set to udma mode[%u] \n", udma_mode); in pdc2027x_set_dmamode()
369 ata_port_dbg(ap, "Set to mdma mode[%u] \n", mdma_mode); in pdc2027x_set_dmamode()
371 ata_port_err(ap, "Unknown dma mode [%u] ignored\n", dma_mode); in pdc2027x_set_dmamode()
376 * pdc2027x_set_mode - Set the timing registers back to correct values.
386 struct ata_port *ap = link->ap; in pdc2027x_set_mode()
398 * Enable prefetch if the device support PIO only. in pdc2027x_set_mode()
400 if (dev->xfer_shift == ATA_SHIFT_PIO) { in pdc2027x_set_mode()
414 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
425 struct scsi_cmnd *cmd = qc->scsicmd; in pdc2027x_check_atapi_dma()
426 u8 *scsicmd = cmd->cmnd; in pdc2027x_check_atapi_dma()
455 * pdc_read_counter - Read the ctr counter
461 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_read_counter()
476 dev_dbg(host->dev, "bccrh [%X] bccrl [%X]\n", bccrh, bccrl); in pdc_read_counter()
477 dev_dbg(host->dev, "bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv); in pdc_read_counter()
480 * The 30-bit decreasing counter are read by 2 pieces. in pdc_read_counter()
485 retry--; in pdc_read_counter()
486 dev_dbg(host->dev, "rereading counter\n"); in pdc_read_counter()
494 * pdc_adjust_pll - Adjust the PLL input clock in Hz.
502 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_adjust_pll()
511 dev_err(host->dev, "Invalid PLL input clock %ldkHz, give up!\n", in pdc_adjust_pll()
516 dev_dbg(host->dev, "pout_required is %ld\n", pout_required); in pdc_adjust_pll()
523 dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl); in pdc_adjust_pll()
542 dev_err(host->dev, "Invalid ratio %ld, give up!\n", ratio); in pdc_adjust_pll()
546 F = (ratio * (R+2)) / 1000 - 2; in pdc_adjust_pll()
550 dev_err(host->dev, "F[%d] invalid!\n", F); in pdc_adjust_pll()
554 dev_dbg(host->dev, "F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); in pdc_adjust_pll()
558 dev_dbg(host->dev, "Writing pll_ctl[%X]\n", pll_ctl); in pdc_adjust_pll()
572 dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl); in pdc_adjust_pll()
578 * pdc_detect_pll_input_clock - Detect the PLL input clock in Hz.
585 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_detect_pll_input_clock()
591 /* Start the test mode */ in pdc_detect_pll_input_clock()
593 dev_dbg(host->dev, "scr[%X]\n", scr); in pdc_detect_pll_input_clock()
608 /* Stop the test mode */ in pdc_detect_pll_input_clock()
610 dev_dbg(host->dev, "scr[%X]\n", scr); in pdc_detect_pll_input_clock()
617 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 * in pdc_detect_pll_input_clock()
620 dev_dbg(host->dev, "start[%ld] end[%ld] PLL input clock[%ld]HZ\n", in pdc_detect_pll_input_clock()
627 * pdc_hardware_init - Initialize the hardware.
637 * On some system, where PCI bus is running at non-standard clock rate. in pdc_hardware_init()
643 dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000); in pdc_hardware_init()
650 * pdc_ata_setup_port - setup the mmio address
656 port->cmd_addr = in pdc_ata_setup_port()
657 port->data_addr = base; in pdc_ata_setup_port()
658 port->feature_addr = in pdc_ata_setup_port()
659 port->error_addr = base + 0x05; in pdc_ata_setup_port()
660 port->nsect_addr = base + 0x0a; in pdc_ata_setup_port()
661 port->lbal_addr = base + 0x0f; in pdc_ata_setup_port()
662 port->lbam_addr = base + 0x10; in pdc_ata_setup_port()
663 port->lbah_addr = base + 0x15; in pdc_ata_setup_port()
664 port->device_addr = base + 0x1a; in pdc_ata_setup_port()
665 port->command_addr = in pdc_ata_setup_port()
666 port->status_addr = base + 0x1f; in pdc_ata_setup_port()
667 port->altstatus_addr = in pdc_ata_setup_port()
668 port->ctl_addr = base + 0x81a; in pdc_ata_setup_port()
672 * pdc2027x_init_one - PCI probe function
686 unsigned int board_idx = (unsigned int) ent->driver_data; in pdc2027x_init_one()
693 ata_print_version_once(&pdev->dev, DRV_VERSION); in pdc2027x_init_one()
696 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); in pdc2027x_init_one()
698 return -ENOMEM; in pdc2027x_init_one()
708 host->iomap = pcim_iomap_table(pdev); in pdc2027x_init_one()
710 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); in pdc2027x_init_one()
714 mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc2027x_init_one()
717 struct ata_port *ap = host->ports[i]; in pdc2027x_init_one()
719 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]); in pdc2027x_init_one()
720 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i]; in pdc2027x_init_one()
722 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); in pdc2027x_init_one()
732 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, in pdc2027x_init_one()
747 if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 || in pdc2027x_reinit_one()
748 pdev->device == PCI_DEVICE_ID_PROMISE_20270) in pdc2027x_reinit_one()