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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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H A Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
22 - ingenic,x2000-mac
30 interrupt-names:
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H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
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H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
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/openbmc/linux/drivers/memory/
H A Djedec_ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
64 /* Refresh rate in nano-seconds */
144 * All parameters are in pico seconds(ps) unless explicitly indicated
207 * -ENOENT if info unavailable.
222 * All parameters are in pico seconds(ps) excluding max_freq, min_freq which
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
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/openbmc/linux/arch/powerpc/platforms/85xx/
H A Dt1042rdb_diu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
74 * @pixclock: pixel clock in ps (pico seconds)
84 scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg"); in t1042rdb_set_pixel_clock()
107 * range of values is 2-255. in t1042rdb_set_pixel_clock()
112 /* Disable the pixel clock, and set it to non-inverted and no delay */ in t1042rdb_set_pixel_clock()
133 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */ in t1042rdb_valid_monitor_port()
139 cpld_node = of_find_compatible_node(NULL, NULL, "fsl,t1042rdb-cpld"); in t1042rdb_diu_init()
/openbmc/u-boot/drivers/video/
H A Dvideomodes.h1 /* SPDX-License-Identifier: GPL-2.0+ */
40 int pixclock; /* pixel clock in ps (pico seconds) */
H A Dmx3fb.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
19 /* this might need panel specific set-up as-well */
22 /* -------------- controller specific stuff -------------- */
100 /* IPU_CONF and its bits already defined in imx-regs.h */
352 * sdc_init_panel() - initialize a synchronous LCD panel.
371 return -EACCES; in sdc_init_panel()
374 reg = width + mode->left_margin + mode->right_margin - 1; in sdc_init_panel()
379 reg = ((mode->hsync_len - 1) << 26) | (reg << 16); in sdc_init_panel()
382 reg = height + mode->upper_margin + mode->lower_margin - 1; in sdc_init_panel()
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/openbmc/linux/Documentation/fb/
H A Dep93xx-fb.rst24 Note that the pixel clock value is in pico-seconds. You can use the
98 struct ep93xxfb_mach_info *mach_info = pdev->dev.platform_data;
110 video=XRESxYRES[-BPP][@REFRESH]
112 If the EP93xx video driver is built-in then the video mode is set on
115 video=ep93xx-fb:800x600-16@60
120 modprobe ep93xx-fb video=320x240
130 https://marc.info/?l=linux-arm-kernel&m=110061245502000&w=2
137 ep93xx-fb.check_screenpage_bug=0
H A Dapi.rst9 ---------------
12 with frame buffer devices. In-kernel APIs between device drivers and the frame
22 ---------------
36 - FB_CAP_FOURCC
44 --------------------
46 Pixels are stored in memory in hardware-dependent formats. Applications need
58 - FB_TYPE_PACKED_PIXELS
67 - FB_TYPE_PLANES
75 - FB_TYPE_INTERLEAVED_PLANES
86 - FB_TYPE_FOURCC
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H A Dframebuffer.rst9 ---------------
13 software to access the graphics hardware through a well-defined interface, so
14 the software doesn't need to know anything about the low-level (hardware
22 --------------------------
39 /dev/fb0current -> fb0
40 /dev/fb1current -> fb1
50 graphics card in addition to the built-in hardware. The corresponding frame
69 --------------------------------
82 - You can request unchangeable information about the hardware, like name,
86 - You can request and change variable information about the hardware, like
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/openbmc/linux/arch/powerpc/platforms/512x/
H A Dmpc512x_shared.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/fsl-diu-fb.h>
36 out_be32(&reset_module_base->rpr, 0x52535445); in mpc512x_restart()
38 out_be32(&reset_module_base->rcr, 0x2); in mpc512x_restart()
47 u8 gamma[0x300]; /* 32-bit aligned! */
48 struct diu_ad ad0; /* 32-bit aligned! */
54 /* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
63 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); in mpc512x_set_pixel_clock()
71 clk_diu = clk_get_sys(np->name, "ipg"); in mpc512x_set_pixel_clock()
85 * determine the acceptable clock range for the monitor (+/- 5%), in mpc512x_set_pixel_clock()
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/openbmc/linux/include/uapi/linux/
H A Dfb.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
23 /* 0x4607-0x460B are defined below */
51 #define FB_AUX_TEXT_SVGA_GROUP 8 /* 8-15: SVGA tileblit compatible modes */
139 #define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */
141 #define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */
143 #define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */
151 #define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */
153 #define FB_ACCEL_PUV3_UNIGFX 0xa0 /* PKUnity-v3 Unigfx */
155 #define FB_CAP_FOURCC 1 /* Device supports FOURCC-based formats */
195 #define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
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/openbmc/u-boot/include/linux/
H A Dfb.h60 #define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
130 __u32 pixclock; /* pixel clock in ps (pico seconds) */
213 __u32 dx; /* screen-relative */
316 __u32 serial; /* Serial Number - Integer */
323 __u16 input; /* display type - see FB_DISP_* */
324 __u16 dpms; /* DPMS support - see FB_DPMS_ */
325 __u16 signal; /* Signal Type - see FB_SIGNAL_* */
328 __u16 gamma; /* Gamma - in fractions of 100 */
330 __u16 misc; /* Misc flags - see FB_MISC_* */
387 /* CONSOLE-SPECIFIC: get console to framebuffer mapping */
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/openbmc/linux/drivers/net/phy/
H A Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
119 * The value is calculated as following: (1/1000000)/((2^-32)/4)
304 u32 seconds; member
331 s64 seconds; member
332 /* Lock for accessing seconds */
429 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
433 if (type && type->interrupt_level_mask) in kszphy_config_intr()
434 mask = type->interrupt_level_mask; in kszphy_config_intr()
446 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in kszphy_config_intr()
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/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/mx6-ddr.h>
22 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); in reset_read_data_fifos()
23 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
25 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); in reset_read_data_fifos()
26 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
34 * Issue the Precharge-All command to the DDR device for both in precharge_all()
40 writel(0x04008050, &mmdc0->mdscr); in precharge_all()
41 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
45 writel(0x04008058, &mmdc0->mdscr); in precharge_all()
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/openbmc/bmcweb/redfish-core/include/utils/extern/
H A Ddate.h3 // clang-format off
80 # pragma GCC diagnostic ignored "-Wpedantic"
81 # pragma GCC diagnostic ignored "-Wconversion"
82 # pragma GCC diagnostic ignored "-Wold-style-cast"
85 // GCC 4.9 Bug 61489 Wrong warning with -Wmissing-field-initializers
86 # pragma GCC diagnostic ignored "-Wmissing-field-initializers"
91 # pragma GCC diagnostic ignored "-Wunsafe-buffer-usage"
92 # pragma GCC diagnostic ignored "-Wzero-as-null-pointer-constant"
93 # pragma GCC diagnostic ignored "-Wold-style-cast"
105 //---------------+
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/openbmc/linux/drivers/video/fbdev/
H A Damba-clcd.c2 * linux/drivers/video/amba-clcd.c
18 #include <linux/dma-mapping.h>
40 unsigned long ustart = fb->fb.fix.smem_start; in clcdfb_set_start()
43 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length; in clcdfb_set_start()
44 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2; in clcdfb_set_start()
46 writel(ustart, fb->regs + CLCD_UBAS); in clcdfb_set_start()
47 writel(lstart, fb->regs + CLCD_LBAS); in clcdfb_set_start()
54 if (fb->board->disable) in clcdfb_disable()
55 fb->board->disable(fb); in clcdfb_disable()
57 if (fb->panel->backlight) { in clcdfb_disable()
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/openbmc/linux/drivers/mtd/nand/raw/
H A Dpl35x-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
31 #define PL35X_NANDC_DRIVER_NAME "pl35x-nand-controller"
126 * struct pl35x_nandc - NAND flash controller driver structure
162 if (section >= chip->ecc.steps) in pl35x_ecc_ooblayout16_ecc()
163 return -ERANGE; in pl35x_ecc_ooblayout16_ecc()
165 oobregion->offset = (section * chip->ecc.bytes); in pl35x_ecc_ooblayout16_ecc()
166 oobregion->length = chip->ecc.bytes; in pl35x_ecc_ooblayout16_ecc()
176 if (section >= chip->ecc.steps) in pl35x_ecc_ooblayout16_free()
177 return -ERANGE; in pl35x_ecc_ooblayout16_free()
179 oobregion->offset = (section * chip->ecc.bytes) + 8; in pl35x_ecc_ooblayout16_free()
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H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
47 * --------------------------------------------+
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