193db446aSBoris Brezillon // SPDX-License-Identifier: GPL-2.0
293db446aSBoris Brezillon /*
393db446aSBoris Brezillon * Marvell NAND flash controller driver
493db446aSBoris Brezillon *
593db446aSBoris Brezillon * Copyright (C) 2017 Marvell
693db446aSBoris Brezillon * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
793db446aSBoris Brezillon *
833c1c5feSMiquel Raynal *
933c1c5feSMiquel Raynal * This NAND controller driver handles two versions of the hardware,
1033c1c5feSMiquel Raynal * one is called NFCv1 and is available on PXA SoCs and the other is
1133c1c5feSMiquel Raynal * called NFCv2 and is available on Armada SoCs.
1233c1c5feSMiquel Raynal *
1333c1c5feSMiquel Raynal * The main visible difference is that NFCv1 only has Hamming ECC
1433c1c5feSMiquel Raynal * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
1533c1c5feSMiquel Raynal * is not used with NFCv2.
1633c1c5feSMiquel Raynal *
1733c1c5feSMiquel Raynal * The ECC layouts are depicted in details in Marvell AN-379, but here
1833c1c5feSMiquel Raynal * is a brief description.
1933c1c5feSMiquel Raynal *
2033c1c5feSMiquel Raynal * When using Hamming, the data is split in 512B chunks (either 1, 2
2133c1c5feSMiquel Raynal * or 4) and each chunk will have its own ECC "digest" of 6B at the
2233c1c5feSMiquel Raynal * beginning of the OOB area and eventually the remaining free OOB
2333c1c5feSMiquel Raynal * bytes (also called "spare" bytes in the driver). This engine
2433c1c5feSMiquel Raynal * corrects up to 1 bit per chunk and detects reliably an error if
2533c1c5feSMiquel Raynal * there are at most 2 bitflips. Here is the page layout used by the
2633c1c5feSMiquel Raynal * controller when Hamming is chosen:
2733c1c5feSMiquel Raynal *
2833c1c5feSMiquel Raynal * +-------------------------------------------------------------+
2933c1c5feSMiquel Raynal * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
3033c1c5feSMiquel Raynal * +-------------------------------------------------------------+
3133c1c5feSMiquel Raynal *
3233c1c5feSMiquel Raynal * When using the BCH engine, there are N identical (data + free OOB +
3333c1c5feSMiquel Raynal * ECC) sections and potentially an extra one to deal with
3433c1c5feSMiquel Raynal * configurations where the chosen (data + free OOB + ECC) sizes do
3533c1c5feSMiquel Raynal * not align with the page (data + OOB) size. ECC bytes are always
3633c1c5feSMiquel Raynal * 30B per ECC chunk. Here is the page layout used by the controller
3733c1c5feSMiquel Raynal * when BCH is chosen:
3833c1c5feSMiquel Raynal *
3933c1c5feSMiquel Raynal * +-----------------------------------------
4033c1c5feSMiquel Raynal * | Data 1 | Free OOB bytes 1 | ECC 1 | ...
4133c1c5feSMiquel Raynal * +-----------------------------------------
4233c1c5feSMiquel Raynal *
4333c1c5feSMiquel Raynal * -------------------------------------------
4433c1c5feSMiquel Raynal * ... | Data N | Free OOB bytes N | ECC N |
4533c1c5feSMiquel Raynal * -------------------------------------------
4633c1c5feSMiquel Raynal *
4733c1c5feSMiquel Raynal * --------------------------------------------+
4833c1c5feSMiquel Raynal * Last Data | Last Free OOB bytes | Last ECC |
4933c1c5feSMiquel Raynal * --------------------------------------------+
5033c1c5feSMiquel Raynal *
5133c1c5feSMiquel Raynal * In both cases, the layout seen by the user is always: all data
5233c1c5feSMiquel Raynal * first, then all free OOB bytes and finally all ECC bytes. With BCH,
5333c1c5feSMiquel Raynal * ECC bytes are 30B long and are padded with 0xFF to align on 32
5433c1c5feSMiquel Raynal * bytes.
5533c1c5feSMiquel Raynal *
5633c1c5feSMiquel Raynal * The controller has certain limitations that are handled by the
5733c1c5feSMiquel Raynal * driver:
5833c1c5feSMiquel Raynal * - It can only read 2k at a time. To overcome this limitation, the
5933c1c5feSMiquel Raynal * driver issues data cycles on the bus, without issuing new
6033c1c5feSMiquel Raynal * CMD + ADDR cycles. The Marvell term is "naked" operations.
6133c1c5feSMiquel Raynal * - The ECC strength in BCH mode cannot be tuned. It is fixed 16
6233c1c5feSMiquel Raynal * bits. What can be tuned is the ECC block size as long as it
6333c1c5feSMiquel Raynal * stays between 512B and 2kiB. It's usually chosen based on the
6433c1c5feSMiquel Raynal * chip ECC requirements. For instance, using 2kiB ECC chunks
6533c1c5feSMiquel Raynal * provides 4b/512B correctability.
6633c1c5feSMiquel Raynal * - The controller will always treat data bytes, free OOB bytes
6733c1c5feSMiquel Raynal * and ECC bytes in that order, no matter what the real layout is
6833c1c5feSMiquel Raynal * (which is usually all data then all OOB bytes). The
6933c1c5feSMiquel Raynal * marvell_nfc_layouts array below contains the currently
7033c1c5feSMiquel Raynal * supported layouts.
7133c1c5feSMiquel Raynal * - Because of these weird layouts, the Bad Block Markers can be
7233c1c5feSMiquel Raynal * located in data section. In this case, the NAND_BBT_NO_OOB_BBM
7333c1c5feSMiquel Raynal * option must be set to prevent scanning/writing bad block
7433c1c5feSMiquel Raynal * markers.
7593db446aSBoris Brezillon */
7693db446aSBoris Brezillon
7793db446aSBoris Brezillon #include <linux/module.h>
7893db446aSBoris Brezillon #include <linux/clk.h>
7993db446aSBoris Brezillon #include <linux/mtd/rawnand.h>
80c2fc6b69SRob Herring #include <linux/of.h>
8193db446aSBoris Brezillon #include <linux/iopoll.h>
8293db446aSBoris Brezillon #include <linux/interrupt.h>
83c2fc6b69SRob Herring #include <linux/platform_device.h>
8493db446aSBoris Brezillon #include <linux/slab.h>
8593db446aSBoris Brezillon #include <linux/mfd/syscon.h>
8693db446aSBoris Brezillon #include <linux/regmap.h>
8793db446aSBoris Brezillon #include <asm/unaligned.h>
8893db446aSBoris Brezillon
8993db446aSBoris Brezillon #include <linux/dmaengine.h>
9093db446aSBoris Brezillon #include <linux/dma-mapping.h>
9193db446aSBoris Brezillon #include <linux/dma/pxa-dma.h>
9293db446aSBoris Brezillon #include <linux/platform_data/mtd-nand-pxa3xx.h>
9393db446aSBoris Brezillon
9493db446aSBoris Brezillon /* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */
9593db446aSBoris Brezillon #define FIFO_DEPTH 8
9693db446aSBoris Brezillon #define FIFO_REP(x) (x / sizeof(u32))
9793db446aSBoris Brezillon #define BCH_SEQ_READS (32 / FIFO_DEPTH)
9893db446aSBoris Brezillon /* NFC does not support transfers of larger chunks at a time */
9993db446aSBoris Brezillon #define MAX_CHUNK_SIZE 2112
10093db446aSBoris Brezillon /* NFCv1 cannot read more that 7 bytes of ID */
10193db446aSBoris Brezillon #define NFCV1_READID_LEN 7
10293db446aSBoris Brezillon /* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */
10393db446aSBoris Brezillon #define POLL_PERIOD 0
10493db446aSBoris Brezillon #define POLL_TIMEOUT 100000
10593db446aSBoris Brezillon /* Interrupt maximum wait period in ms */
10693db446aSBoris Brezillon #define IRQ_TIMEOUT 1000
10793db446aSBoris Brezillon /* Latency in clock cycles between SoC pins and NFC logic */
10893db446aSBoris Brezillon #define MIN_RD_DEL_CNT 3
10993db446aSBoris Brezillon /* Maximum number of contiguous address cycles */
11093db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV1 5
11193db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV2 7
11293db446aSBoris Brezillon /* System control registers/bits to enable the NAND controller on some SoCs */
11393db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX 0x208
11493db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
11593db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20)
11693db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21)
11793db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25)
118c13bf589SHamish Martin #define GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN BIT(27)
11993db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL 0x220
12093db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2)
12193db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL 0x700
12293db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL_EN BIT(0)
12393db446aSBoris Brezillon
12493db446aSBoris Brezillon /* NAND controller data flash control register */
12593db446aSBoris Brezillon #define NDCR 0x00
12693db446aSBoris Brezillon #define NDCR_ALL_INT GENMASK(11, 0)
12793db446aSBoris Brezillon #define NDCR_CS1_CMDDM BIT(7)
12893db446aSBoris Brezillon #define NDCR_CS0_CMDDM BIT(8)
12993db446aSBoris Brezillon #define NDCR_RDYM BIT(11)
13093db446aSBoris Brezillon #define NDCR_ND_ARB_EN BIT(12)
13193db446aSBoris Brezillon #define NDCR_RA_START BIT(15)
13293db446aSBoris Brezillon #define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16)
13393db446aSBoris Brezillon #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0)
13493db446aSBoris Brezillon #define NDCR_DWIDTH_M BIT(26)
13593db446aSBoris Brezillon #define NDCR_DWIDTH_C BIT(27)
13693db446aSBoris Brezillon #define NDCR_ND_RUN BIT(28)
13793db446aSBoris Brezillon #define NDCR_DMA_EN BIT(29)
13893db446aSBoris Brezillon #define NDCR_ECC_EN BIT(30)
13993db446aSBoris Brezillon #define NDCR_SPARE_EN BIT(31)
14093db446aSBoris Brezillon #define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \
14193db446aSBoris Brezillon NDCR_DWIDTH_M | NDCR_DWIDTH_C))
14293db446aSBoris Brezillon
14393db446aSBoris Brezillon /* NAND interface timing parameter 0 register */
14493db446aSBoris Brezillon #define NDTR0 0x04
14593db446aSBoris Brezillon #define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0)
14693db446aSBoris Brezillon #define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3)
14793db446aSBoris Brezillon #define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3)
14893db446aSBoris Brezillon #define NDTR0_SEL_NRE_EDGE BIT(7)
14993db446aSBoris Brezillon #define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8)
15093db446aSBoris Brezillon #define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11)
15193db446aSBoris Brezillon #define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16)
15293db446aSBoris Brezillon #define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19)
15393db446aSBoris Brezillon #define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22)
15493db446aSBoris Brezillon #define NDTR0_SELCNTR BIT(26)
15593db446aSBoris Brezillon #define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27)
15693db446aSBoris Brezillon
15793db446aSBoris Brezillon /* NAND interface timing parameter 1 register */
15893db446aSBoris Brezillon #define NDTR1 0x0C
15993db446aSBoris Brezillon #define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0)
16093db446aSBoris Brezillon #define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4)
16193db446aSBoris Brezillon #define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8)
16293db446aSBoris Brezillon #define NDTR1_PRESCALE BIT(14)
16393db446aSBoris Brezillon #define NDTR1_WAIT_MODE BIT(15)
16493db446aSBoris Brezillon #define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16)
16593db446aSBoris Brezillon
16693db446aSBoris Brezillon /* NAND controller status register */
16793db446aSBoris Brezillon #define NDSR 0x14
16893db446aSBoris Brezillon #define NDSR_WRCMDREQ BIT(0)
16993db446aSBoris Brezillon #define NDSR_RDDREQ BIT(1)
17093db446aSBoris Brezillon #define NDSR_WRDREQ BIT(2)
17193db446aSBoris Brezillon #define NDSR_CORERR BIT(3)
17293db446aSBoris Brezillon #define NDSR_UNCERR BIT(4)
17393db446aSBoris Brezillon #define NDSR_CMDD(cs) BIT(8 - cs)
17493db446aSBoris Brezillon #define NDSR_RDY(rb) BIT(11 + rb)
17593db446aSBoris Brezillon #define NDSR_ERRCNT(x) ((x >> 16) & 0x1F)
17693db446aSBoris Brezillon
17793db446aSBoris Brezillon /* NAND ECC control register */
17893db446aSBoris Brezillon #define NDECCCTRL 0x28
17993db446aSBoris Brezillon #define NDECCCTRL_BCH_EN BIT(0)
18093db446aSBoris Brezillon
18193db446aSBoris Brezillon /* NAND controller data buffer register */
18293db446aSBoris Brezillon #define NDDB 0x40
18393db446aSBoris Brezillon
18493db446aSBoris Brezillon /* NAND controller command buffer 0 register */
18593db446aSBoris Brezillon #define NDCB0 0x48
18693db446aSBoris Brezillon #define NDCB0_CMD1(x) ((x & 0xFF) << 0)
18793db446aSBoris Brezillon #define NDCB0_CMD2(x) ((x & 0xFF) << 8)
18893db446aSBoris Brezillon #define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16)
18993db446aSBoris Brezillon #define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7)
19093db446aSBoris Brezillon #define NDCB0_DBC BIT(19)
19193db446aSBoris Brezillon #define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21)
19293db446aSBoris Brezillon #define NDCB0_CSEL BIT(24)
19393db446aSBoris Brezillon #define NDCB0_RDY_BYP BIT(27)
19493db446aSBoris Brezillon #define NDCB0_LEN_OVRD BIT(28)
19593db446aSBoris Brezillon #define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29)
19693db446aSBoris Brezillon
19793db446aSBoris Brezillon /* NAND controller command buffer 1 register */
19893db446aSBoris Brezillon #define NDCB1 0x4C
19993db446aSBoris Brezillon #define NDCB1_COLS(x) ((x & 0xFFFF) << 0)
20093db446aSBoris Brezillon #define NDCB1_ADDRS_PAGE(x) (x << 16)
20193db446aSBoris Brezillon
20293db446aSBoris Brezillon /* NAND controller command buffer 2 register */
20393db446aSBoris Brezillon #define NDCB2 0x50
20493db446aSBoris Brezillon #define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0)
20593db446aSBoris Brezillon #define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0)
20693db446aSBoris Brezillon
20793db446aSBoris Brezillon /* NAND controller command buffer 3 register */
20893db446aSBoris Brezillon #define NDCB3 0x54
20993db446aSBoris Brezillon #define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16)
21093db446aSBoris Brezillon #define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24)
21193db446aSBoris Brezillon
21293db446aSBoris Brezillon /* NAND controller command buffer 0 register 'type' and 'xtype' fields */
21393db446aSBoris Brezillon #define TYPE_READ 0
21493db446aSBoris Brezillon #define TYPE_WRITE 1
21593db446aSBoris Brezillon #define TYPE_ERASE 2
21693db446aSBoris Brezillon #define TYPE_READ_ID 3
21793db446aSBoris Brezillon #define TYPE_STATUS 4
21893db446aSBoris Brezillon #define TYPE_RESET 5
21993db446aSBoris Brezillon #define TYPE_NAKED_CMD 6
22093db446aSBoris Brezillon #define TYPE_NAKED_ADDR 7
22193db446aSBoris Brezillon #define TYPE_MASK 7
22293db446aSBoris Brezillon #define XTYPE_MONOLITHIC_RW 0
22393db446aSBoris Brezillon #define XTYPE_LAST_NAKED_RW 1
22493db446aSBoris Brezillon #define XTYPE_FINAL_COMMAND 3
22593db446aSBoris Brezillon #define XTYPE_READ 4
22693db446aSBoris Brezillon #define XTYPE_WRITE_DISPATCH 4
22793db446aSBoris Brezillon #define XTYPE_NAKED_RW 5
22893db446aSBoris Brezillon #define XTYPE_COMMAND_DISPATCH 6
22993db446aSBoris Brezillon #define XTYPE_MASK 7
23093db446aSBoris Brezillon
23193db446aSBoris Brezillon /**
232c4bc1ec9SKrzysztof Kozlowski * struct marvell_hw_ecc_layout - layout of Marvell ECC
233c4bc1ec9SKrzysztof Kozlowski *
23493db446aSBoris Brezillon * Marvell ECC engine works differently than the others, in order to limit the
23593db446aSBoris Brezillon * size of the IP, hardware engineers chose to set a fixed strength at 16 bits
23693db446aSBoris Brezillon * per subpage, and depending on a the desired strength needed by the NAND chip,
23793db446aSBoris Brezillon * a particular layout mixing data/spare/ecc is defined, with a possible last
23893db446aSBoris Brezillon * chunk smaller that the others.
23993db446aSBoris Brezillon *
24093db446aSBoris Brezillon * @writesize: Full page size on which the layout applies
24193db446aSBoris Brezillon * @chunk: Desired ECC chunk size on which the layout applies
24293db446aSBoris Brezillon * @strength: Desired ECC strength (per chunk size bytes) on which the
24393db446aSBoris Brezillon * layout applies
24493db446aSBoris Brezillon * @nchunks: Total number of chunks
24593db446aSBoris Brezillon * @full_chunk_cnt: Number of full-sized chunks, which is the number of
24693db446aSBoris Brezillon * repetitions of the pattern:
24793db446aSBoris Brezillon * (data_bytes + spare_bytes + ecc_bytes).
24893db446aSBoris Brezillon * @data_bytes: Number of data bytes per chunk
24993db446aSBoris Brezillon * @spare_bytes: Number of spare bytes per chunk
25093db446aSBoris Brezillon * @ecc_bytes: Number of ecc bytes per chunk
25193db446aSBoris Brezillon * @last_data_bytes: Number of data bytes in the last chunk
25293db446aSBoris Brezillon * @last_spare_bytes: Number of spare bytes in the last chunk
25393db446aSBoris Brezillon * @last_ecc_bytes: Number of ecc bytes in the last chunk
25493db446aSBoris Brezillon */
25593db446aSBoris Brezillon struct marvell_hw_ecc_layout {
25693db446aSBoris Brezillon /* Constraints */
25793db446aSBoris Brezillon int writesize;
25893db446aSBoris Brezillon int chunk;
25993db446aSBoris Brezillon int strength;
26093db446aSBoris Brezillon /* Corresponding layout */
26193db446aSBoris Brezillon int nchunks;
26293db446aSBoris Brezillon int full_chunk_cnt;
26393db446aSBoris Brezillon int data_bytes;
26493db446aSBoris Brezillon int spare_bytes;
26593db446aSBoris Brezillon int ecc_bytes;
26693db446aSBoris Brezillon int last_data_bytes;
26793db446aSBoris Brezillon int last_spare_bytes;
26893db446aSBoris Brezillon int last_ecc_bytes;
26993db446aSBoris Brezillon };
27093db446aSBoris Brezillon
27193db446aSBoris Brezillon #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \
27293db446aSBoris Brezillon { \
27393db446aSBoris Brezillon .writesize = ws, \
27493db446aSBoris Brezillon .chunk = dc, \
27593db446aSBoris Brezillon .strength = ds, \
27693db446aSBoris Brezillon .nchunks = nc, \
27793db446aSBoris Brezillon .full_chunk_cnt = fcc, \
27893db446aSBoris Brezillon .data_bytes = db, \
27993db446aSBoris Brezillon .spare_bytes = sb, \
28093db446aSBoris Brezillon .ecc_bytes = eb, \
28193db446aSBoris Brezillon .last_data_bytes = ldb, \
28293db446aSBoris Brezillon .last_spare_bytes = lsb, \
28393db446aSBoris Brezillon .last_ecc_bytes = leb, \
28493db446aSBoris Brezillon }
28593db446aSBoris Brezillon
28693db446aSBoris Brezillon /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
28793db446aSBoris Brezillon static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = {
28893db446aSBoris Brezillon MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0),
28993db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0),
29093db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0),
2917fd130f7SMiquel Raynal MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,32, 30),
29268c18daeSAviram Dali MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,64, 30),
293*ad8ff8cfSElad Nachman MARVELL_LAYOUT( 2048, 512, 16, 4, 4, 512, 0, 30, 0, 32, 30),
29493db446aSBoris Brezillon MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0),
295*ad8ff8cfSElad Nachman MARVELL_LAYOUT( 4096, 512, 8, 4, 4, 1024, 0, 30, 0, 64, 30),
296*ad8ff8cfSElad Nachman MARVELL_LAYOUT( 4096, 512, 16, 8, 8, 512, 0, 30, 0, 32, 30),
297e8237bfaSKonstantin Porotchkin MARVELL_LAYOUT( 8192, 512, 4, 4, 4, 2048, 0, 30, 0, 0, 0),
298*ad8ff8cfSElad Nachman MARVELL_LAYOUT( 8192, 512, 8, 8, 8, 1024, 0, 30, 0, 160, 30),
299*ad8ff8cfSElad Nachman MARVELL_LAYOUT( 8192, 512, 16, 16, 16, 512, 0, 30, 0, 32, 30),
30093db446aSBoris Brezillon };
30193db446aSBoris Brezillon
30293db446aSBoris Brezillon /**
303c4bc1ec9SKrzysztof Kozlowski * struct marvell_nand_chip_sel - CS line description
304c4bc1ec9SKrzysztof Kozlowski *
30593db446aSBoris Brezillon * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
30693db446aSBoris Brezillon * is made by a field in NDCB0 register, and in another field in NDCB2 register.
30793db446aSBoris Brezillon * The datasheet describes the logic with an error: ADDR5 field is once
30893db446aSBoris Brezillon * declared at the beginning of NDCB2, and another time at its end. Because the
30993db446aSBoris Brezillon * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical
31093db446aSBoris Brezillon * to use the last bit of this field instead of the first ones.
31193db446aSBoris Brezillon *
31293db446aSBoris Brezillon * @cs: Wanted CE lane.
31393db446aSBoris Brezillon * @ndcb0_csel: Value of the NDCB0 register with or without the flag
31493db446aSBoris Brezillon * selecting the wanted CE lane. This is set once when
31593db446aSBoris Brezillon * the Device Tree is probed.
31693db446aSBoris Brezillon * @rb: Ready/Busy pin for the flash chip
31793db446aSBoris Brezillon */
31893db446aSBoris Brezillon struct marvell_nand_chip_sel {
31993db446aSBoris Brezillon unsigned int cs;
32093db446aSBoris Brezillon u32 ndcb0_csel;
32193db446aSBoris Brezillon unsigned int rb;
32293db446aSBoris Brezillon };
32393db446aSBoris Brezillon
32493db446aSBoris Brezillon /**
325c4bc1ec9SKrzysztof Kozlowski * struct marvell_nand_chip - stores NAND chip device related information
32693db446aSBoris Brezillon *
32793db446aSBoris Brezillon * @chip: Base NAND chip structure
32893db446aSBoris Brezillon * @node: Used to store NAND chips into a list
329c4bc1ec9SKrzysztof Kozlowski * @layout: NAND layout when using hardware ECC
33093db446aSBoris Brezillon * @ndcr: Controller register value for this NAND chip
33193db446aSBoris Brezillon * @ndtr0: Timing registers 0 value for this NAND chip
33293db446aSBoris Brezillon * @ndtr1: Timing registers 1 value for this NAND chip
333c4bc1ec9SKrzysztof Kozlowski * @addr_cyc: Amount of cycles needed to pass column address
33493db446aSBoris Brezillon * @selected_die: Current active CS
33593db446aSBoris Brezillon * @nsels: Number of CS lines required by the NAND chip
33693db446aSBoris Brezillon * @sels: Array of CS lines descriptions
33793db446aSBoris Brezillon */
33893db446aSBoris Brezillon struct marvell_nand_chip {
33993db446aSBoris Brezillon struct nand_chip chip;
34093db446aSBoris Brezillon struct list_head node;
34193db446aSBoris Brezillon const struct marvell_hw_ecc_layout *layout;
34293db446aSBoris Brezillon u32 ndcr;
34393db446aSBoris Brezillon u32 ndtr0;
34493db446aSBoris Brezillon u32 ndtr1;
34593db446aSBoris Brezillon int addr_cyc;
34693db446aSBoris Brezillon int selected_die;
34793db446aSBoris Brezillon unsigned int nsels;
34849f1c330SGustavo A. R. Silva struct marvell_nand_chip_sel sels[];
34993db446aSBoris Brezillon };
35093db446aSBoris Brezillon
to_marvell_nand(struct nand_chip * chip)35193db446aSBoris Brezillon static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip)
35293db446aSBoris Brezillon {
35393db446aSBoris Brezillon return container_of(chip, struct marvell_nand_chip, chip);
35493db446aSBoris Brezillon }
35593db446aSBoris Brezillon
to_nand_sel(struct marvell_nand_chip * nand)35693db446aSBoris Brezillon static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip
35793db446aSBoris Brezillon *nand)
35893db446aSBoris Brezillon {
35993db446aSBoris Brezillon return &nand->sels[nand->selected_die];
36093db446aSBoris Brezillon }
36193db446aSBoris Brezillon
36293db446aSBoris Brezillon /**
363c4bc1ec9SKrzysztof Kozlowski * struct marvell_nfc_caps - NAND controller capabilities for distinction
364c4bc1ec9SKrzysztof Kozlowski * between compatible strings
36593db446aSBoris Brezillon *
36693db446aSBoris Brezillon * @max_cs_nb: Number of Chip Select lines available
36793db446aSBoris Brezillon * @max_rb_nb: Number of Ready/Busy lines available
36893db446aSBoris Brezillon * @need_system_controller: Indicates if the SoC needs to have access to the
36993db446aSBoris Brezillon * system controller (ie. to enable the NAND controller)
37093db446aSBoris Brezillon * @legacy_of_bindings: Indicates if DT parsing must be done using the old
37193db446aSBoris Brezillon * fashion way
37293db446aSBoris Brezillon * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie.
37393db446aSBoris Brezillon * BCH error detection and correction algorithm,
37493db446aSBoris Brezillon * NDCB3 register has been added
37593db446aSBoris Brezillon * @use_dma: Use dma for data transfers
37672b9a3fcSChris Packham * @max_mode_number: Maximum timing mode supported by the controller
37793db446aSBoris Brezillon */
37893db446aSBoris Brezillon struct marvell_nfc_caps {
37993db446aSBoris Brezillon unsigned int max_cs_nb;
38093db446aSBoris Brezillon unsigned int max_rb_nb;
38193db446aSBoris Brezillon bool need_system_controller;
38293db446aSBoris Brezillon bool legacy_of_bindings;
38393db446aSBoris Brezillon bool is_nfcv2;
38493db446aSBoris Brezillon bool use_dma;
38572b9a3fcSChris Packham unsigned int max_mode_number;
38693db446aSBoris Brezillon };
38793db446aSBoris Brezillon
38893db446aSBoris Brezillon /**
389c4bc1ec9SKrzysztof Kozlowski * struct marvell_nfc - stores Marvell NAND controller information
39093db446aSBoris Brezillon *
39193db446aSBoris Brezillon * @controller: Base controller structure
39293db446aSBoris Brezillon * @dev: Parent device (used to print error messages)
39393db446aSBoris Brezillon * @regs: NAND controller registers
3946b6de654SBoris Brezillon * @core_clk: Core clock
3951b489effSMiquel Raynal * @reg_clk: Registers clock
39693db446aSBoris Brezillon * @complete: Completion object to wait for NAND controller events
39793db446aSBoris Brezillon * @assigned_cs: Bitmask describing already assigned CS lines
39893db446aSBoris Brezillon * @chips: List containing all the NAND chips attached to
39993db446aSBoris Brezillon * this NAND controller
400c4bc1ec9SKrzysztof Kozlowski * @selected_chip: Currently selected target chip
40193db446aSBoris Brezillon * @caps: NAND controller capabilities for each compatible string
402c4bc1ec9SKrzysztof Kozlowski * @use_dma: Whetner DMA is used
40393db446aSBoris Brezillon * @dma_chan: DMA channel (NFCv1 only)
40493db446aSBoris Brezillon * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only)
40593db446aSBoris Brezillon */
40693db446aSBoris Brezillon struct marvell_nfc {
4077da45139SMiquel Raynal struct nand_controller controller;
40893db446aSBoris Brezillon struct device *dev;
40993db446aSBoris Brezillon void __iomem *regs;
4106b6de654SBoris Brezillon struct clk *core_clk;
411961ba15cSGregory CLEMENT struct clk *reg_clk;
41293db446aSBoris Brezillon struct completion complete;
41393db446aSBoris Brezillon unsigned long assigned_cs;
41493db446aSBoris Brezillon struct list_head chips;
41593db446aSBoris Brezillon struct nand_chip *selected_chip;
41693db446aSBoris Brezillon const struct marvell_nfc_caps *caps;
41793db446aSBoris Brezillon
41893db446aSBoris Brezillon /* DMA (NFCv1 only) */
41993db446aSBoris Brezillon bool use_dma;
42093db446aSBoris Brezillon struct dma_chan *dma_chan;
42193db446aSBoris Brezillon u8 *dma_buf;
42293db446aSBoris Brezillon };
42393db446aSBoris Brezillon
to_marvell_nfc(struct nand_controller * ctrl)4247da45139SMiquel Raynal static inline struct marvell_nfc *to_marvell_nfc(struct nand_controller *ctrl)
42593db446aSBoris Brezillon {
42693db446aSBoris Brezillon return container_of(ctrl, struct marvell_nfc, controller);
42793db446aSBoris Brezillon }
42893db446aSBoris Brezillon
42993db446aSBoris Brezillon /**
430c4bc1ec9SKrzysztof Kozlowski * struct marvell_nfc_timings - NAND controller timings expressed in NAND
431c4bc1ec9SKrzysztof Kozlowski * Controller clock cycles
43293db446aSBoris Brezillon *
43393db446aSBoris Brezillon * @tRP: ND_nRE pulse width
43493db446aSBoris Brezillon * @tRH: ND_nRE high duration
43593db446aSBoris Brezillon * @tWP: ND_nWE pulse time
43693db446aSBoris Brezillon * @tWH: ND_nWE high duration
43793db446aSBoris Brezillon * @tCS: Enable signal setup time
43893db446aSBoris Brezillon * @tCH: Enable signal hold time
43993db446aSBoris Brezillon * @tADL: Address to write data delay
44093db446aSBoris Brezillon * @tAR: ND_ALE low to ND_nRE low delay
44193db446aSBoris Brezillon * @tWHR: ND_nWE high to ND_nRE low for status read
44293db446aSBoris Brezillon * @tRHW: ND_nRE high duration, read to write delay
44393db446aSBoris Brezillon * @tR: ND_nWE high to ND_nRE low for read
44493db446aSBoris Brezillon */
44593db446aSBoris Brezillon struct marvell_nfc_timings {
44693db446aSBoris Brezillon /* NDTR0 fields */
44793db446aSBoris Brezillon unsigned int tRP;
44893db446aSBoris Brezillon unsigned int tRH;
44993db446aSBoris Brezillon unsigned int tWP;
45093db446aSBoris Brezillon unsigned int tWH;
45193db446aSBoris Brezillon unsigned int tCS;
45293db446aSBoris Brezillon unsigned int tCH;
45393db446aSBoris Brezillon unsigned int tADL;
45493db446aSBoris Brezillon /* NDTR1 fields */
45593db446aSBoris Brezillon unsigned int tAR;
45693db446aSBoris Brezillon unsigned int tWHR;
45793db446aSBoris Brezillon unsigned int tRHW;
45893db446aSBoris Brezillon unsigned int tR;
45993db446aSBoris Brezillon };
46093db446aSBoris Brezillon
46193db446aSBoris Brezillon /**
462f856c4e9SSouptick Joarder * TO_CYCLES() - Derives a duration in numbers of clock cycles.
46393db446aSBoris Brezillon *
46493db446aSBoris Brezillon * @ps: Duration in pico-seconds
46593db446aSBoris Brezillon * @period_ns: Clock period in nano-seconds
46693db446aSBoris Brezillon *
46793db446aSBoris Brezillon * Convert the duration in nano-seconds, then divide by the period and
46893db446aSBoris Brezillon * return the number of clock periods.
46993db446aSBoris Brezillon */
47093db446aSBoris Brezillon #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns))
47193db446aSBoris Brezillon #define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \
47293db446aSBoris Brezillon period_ns))
47393db446aSBoris Brezillon
47493db446aSBoris Brezillon /**
475c4bc1ec9SKrzysztof Kozlowski * struct marvell_nfc_op - filled during the parsing of the ->exec_op()
476c4bc1ec9SKrzysztof Kozlowski * subop subset of instructions.
47793db446aSBoris Brezillon *
47893db446aSBoris Brezillon * @ndcb: Array of values written to NDCBx registers
47993db446aSBoris Brezillon * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle
48093db446aSBoris Brezillon * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin
48193db446aSBoris Brezillon * @rdy_delay_ns: Optional delay after waiting for the RB pin
48293db446aSBoris Brezillon * @data_delay_ns: Optional delay after the data xfer
48393db446aSBoris Brezillon * @data_instr_idx: Index of the data instruction in the subop
48493db446aSBoris Brezillon * @data_instr: Pointer to the data instruction in the subop
48593db446aSBoris Brezillon */
48693db446aSBoris Brezillon struct marvell_nfc_op {
48793db446aSBoris Brezillon u32 ndcb[4];
48893db446aSBoris Brezillon unsigned int cle_ale_delay_ns;
48993db446aSBoris Brezillon unsigned int rdy_timeout_ms;
49093db446aSBoris Brezillon unsigned int rdy_delay_ns;
49193db446aSBoris Brezillon unsigned int data_delay_ns;
49293db446aSBoris Brezillon unsigned int data_instr_idx;
49393db446aSBoris Brezillon const struct nand_op_instr *data_instr;
49493db446aSBoris Brezillon };
49593db446aSBoris Brezillon
49693db446aSBoris Brezillon /*
49793db446aSBoris Brezillon * Internal helper to conditionnally apply a delay (from the above structure,
49893db446aSBoris Brezillon * most of the time).
49993db446aSBoris Brezillon */
cond_delay(unsigned int ns)50093db446aSBoris Brezillon static void cond_delay(unsigned int ns)
50193db446aSBoris Brezillon {
50293db446aSBoris Brezillon if (!ns)
50393db446aSBoris Brezillon return;
50493db446aSBoris Brezillon
50593db446aSBoris Brezillon if (ns < 10000)
50693db446aSBoris Brezillon ndelay(ns);
50793db446aSBoris Brezillon else
50893db446aSBoris Brezillon udelay(DIV_ROUND_UP(ns, 1000));
50993db446aSBoris Brezillon }
51093db446aSBoris Brezillon
51193db446aSBoris Brezillon /*
51293db446aSBoris Brezillon * The controller has many flags that could generate interrupts, most of them
51393db446aSBoris Brezillon * are disabled and polling is used. For the very slow signals, using interrupts
51493db446aSBoris Brezillon * may relax the CPU charge.
51593db446aSBoris Brezillon */
marvell_nfc_disable_int(struct marvell_nfc * nfc,u32 int_mask)51693db446aSBoris Brezillon static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask)
51793db446aSBoris Brezillon {
51893db446aSBoris Brezillon u32 reg;
51993db446aSBoris Brezillon
52093db446aSBoris Brezillon /* Writing 1 disables the interrupt */
52193db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR);
52293db446aSBoris Brezillon writel_relaxed(reg | int_mask, nfc->regs + NDCR);
52393db446aSBoris Brezillon }
52493db446aSBoris Brezillon
marvell_nfc_enable_int(struct marvell_nfc * nfc,u32 int_mask)52593db446aSBoris Brezillon static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask)
52693db446aSBoris Brezillon {
52793db446aSBoris Brezillon u32 reg;
52893db446aSBoris Brezillon
52993db446aSBoris Brezillon /* Writing 0 enables the interrupt */
53093db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR);
53193db446aSBoris Brezillon writel_relaxed(reg & ~int_mask, nfc->regs + NDCR);
53293db446aSBoris Brezillon }
53393db446aSBoris Brezillon
marvell_nfc_clear_int(struct marvell_nfc * nfc,u32 int_mask)534cafb56ddSMiquel Raynal static u32 marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask)
53593db446aSBoris Brezillon {
536cafb56ddSMiquel Raynal u32 reg;
537cafb56ddSMiquel Raynal
538cafb56ddSMiquel Raynal reg = readl_relaxed(nfc->regs + NDSR);
53993db446aSBoris Brezillon writel_relaxed(int_mask, nfc->regs + NDSR);
540cafb56ddSMiquel Raynal
541cafb56ddSMiquel Raynal return reg & int_mask;
54293db446aSBoris Brezillon }
54393db446aSBoris Brezillon
marvell_nfc_force_byte_access(struct nand_chip * chip,bool force_8bit)54493db446aSBoris Brezillon static void marvell_nfc_force_byte_access(struct nand_chip *chip,
54593db446aSBoris Brezillon bool force_8bit)
54693db446aSBoris Brezillon {
54793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
54893db446aSBoris Brezillon u32 ndcr;
54993db446aSBoris Brezillon
55093db446aSBoris Brezillon /*
55193db446aSBoris Brezillon * Callers of this function do not verify if the NAND is using a 16-bit
55293db446aSBoris Brezillon * an 8-bit bus for normal operations, so we need to take care of that
55393db446aSBoris Brezillon * here by leaving the configuration unchanged if the NAND does not have
55493db446aSBoris Brezillon * the NAND_BUSWIDTH_16 flag set.
55593db446aSBoris Brezillon */
55693db446aSBoris Brezillon if (!(chip->options & NAND_BUSWIDTH_16))
55793db446aSBoris Brezillon return;
55893db446aSBoris Brezillon
55993db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR);
56093db446aSBoris Brezillon
56193db446aSBoris Brezillon if (force_8bit)
56293db446aSBoris Brezillon ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C);
56393db446aSBoris Brezillon else
56493db446aSBoris Brezillon ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
56593db446aSBoris Brezillon
56693db446aSBoris Brezillon writel_relaxed(ndcr, nfc->regs + NDCR);
56793db446aSBoris Brezillon }
56893db446aSBoris Brezillon
marvell_nfc_wait_ndrun(struct nand_chip * chip)56993db446aSBoris Brezillon static int marvell_nfc_wait_ndrun(struct nand_chip *chip)
57093db446aSBoris Brezillon {
57193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
57293db446aSBoris Brezillon u32 val;
57393db446aSBoris Brezillon int ret;
57493db446aSBoris Brezillon
57593db446aSBoris Brezillon /*
57693db446aSBoris Brezillon * The command is being processed, wait for the ND_RUN bit to be
57793db446aSBoris Brezillon * cleared by the NFC. If not, we must clear it by hand.
57893db446aSBoris Brezillon */
57993db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val,
58093db446aSBoris Brezillon (val & NDCR_ND_RUN) == 0,
58193db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT);
58293db446aSBoris Brezillon if (ret) {
58393db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on NAND controller run mode\n");
58493db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
58593db446aSBoris Brezillon nfc->regs + NDCR);
58693db446aSBoris Brezillon return ret;
58793db446aSBoris Brezillon }
58893db446aSBoris Brezillon
58993db446aSBoris Brezillon return 0;
59093db446aSBoris Brezillon }
59193db446aSBoris Brezillon
59293db446aSBoris Brezillon /*
59393db446aSBoris Brezillon * Any time a command has to be sent to the controller, the following sequence
59493db446aSBoris Brezillon * has to be followed:
59593db446aSBoris Brezillon * - call marvell_nfc_prepare_cmd()
59693db446aSBoris Brezillon * -> activate the ND_RUN bit that will kind of 'start a job'
59793db446aSBoris Brezillon * -> wait the signal indicating the NFC is waiting for a command
59893db446aSBoris Brezillon * - send the command (cmd and address cycles)
59993db446aSBoris Brezillon * - enventually send or receive the data
60093db446aSBoris Brezillon * - call marvell_nfc_end_cmd() with the corresponding flag
60193db446aSBoris Brezillon * -> wait the flag to be triggered or cancel the job with a timeout
60293db446aSBoris Brezillon *
60393db446aSBoris Brezillon * The following helpers are here to factorize the code a bit so that
60493db446aSBoris Brezillon * specialized functions responsible for executing the actual NAND
60593db446aSBoris Brezillon * operations do not have to replicate the same code blocks.
60693db446aSBoris Brezillon */
marvell_nfc_prepare_cmd(struct nand_chip * chip)60793db446aSBoris Brezillon static int marvell_nfc_prepare_cmd(struct nand_chip *chip)
60893db446aSBoris Brezillon {
60993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
61093db446aSBoris Brezillon u32 ndcr, val;
61193db446aSBoris Brezillon int ret;
61293db446aSBoris Brezillon
61393db446aSBoris Brezillon /* Poll ND_RUN and clear NDSR before issuing any command */
61493db446aSBoris Brezillon ret = marvell_nfc_wait_ndrun(chip);
61593db446aSBoris Brezillon if (ret) {
61693db446aSBoris Brezillon dev_err(nfc->dev, "Last operation did not succeed\n");
61793db446aSBoris Brezillon return ret;
61893db446aSBoris Brezillon }
61993db446aSBoris Brezillon
62093db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR);
62193db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR);
62293db446aSBoris Brezillon
62393db446aSBoris Brezillon /* Assert ND_RUN bit and wait the NFC to be ready */
62493db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR);
62593db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
62693db446aSBoris Brezillon val & NDSR_WRCMDREQ,
62793db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT);
62893db446aSBoris Brezillon if (ret) {
62993db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on WRCMDRE\n");
63093db446aSBoris Brezillon return -ETIMEDOUT;
63193db446aSBoris Brezillon }
63293db446aSBoris Brezillon
63393db446aSBoris Brezillon /* Command may be written, clear WRCMDREQ status bit */
63493db446aSBoris Brezillon writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR);
63593db446aSBoris Brezillon
63693db446aSBoris Brezillon return 0;
63793db446aSBoris Brezillon }
63893db446aSBoris Brezillon
marvell_nfc_send_cmd(struct nand_chip * chip,struct marvell_nfc_op * nfc_op)63993db446aSBoris Brezillon static void marvell_nfc_send_cmd(struct nand_chip *chip,
64093db446aSBoris Brezillon struct marvell_nfc_op *nfc_op)
64193db446aSBoris Brezillon {
64293db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
64393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
64493db446aSBoris Brezillon
64593db446aSBoris Brezillon dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n"
64693db446aSBoris Brezillon "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n",
64793db446aSBoris Brezillon (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0],
64893db446aSBoris Brezillon nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]);
64993db446aSBoris Brezillon
65093db446aSBoris Brezillon writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0],
65193db446aSBoris Brezillon nfc->regs + NDCB0);
65293db446aSBoris Brezillon writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0);
65393db446aSBoris Brezillon writel(nfc_op->ndcb[2], nfc->regs + NDCB0);
65493db446aSBoris Brezillon
65593db446aSBoris Brezillon /*
65693db446aSBoris Brezillon * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7
65793db446aSBoris Brezillon * fields are used (only available on NFCv2).
65893db446aSBoris Brezillon */
65993db446aSBoris Brezillon if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD ||
66093db446aSBoris Brezillon NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) {
66193db446aSBoris Brezillon if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2))
66293db446aSBoris Brezillon writel(nfc_op->ndcb[3], nfc->regs + NDCB0);
66393db446aSBoris Brezillon }
66493db446aSBoris Brezillon }
66593db446aSBoris Brezillon
marvell_nfc_end_cmd(struct nand_chip * chip,int flag,const char * label)66693db446aSBoris Brezillon static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag,
66793db446aSBoris Brezillon const char *label)
66893db446aSBoris Brezillon {
66993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
67093db446aSBoris Brezillon u32 val;
67193db446aSBoris Brezillon int ret;
67293db446aSBoris Brezillon
67393db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
67493db446aSBoris Brezillon val & flag,
67593db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT);
67693db446aSBoris Brezillon
67793db446aSBoris Brezillon if (ret) {
67893db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n",
67993db446aSBoris Brezillon label, val);
68093db446aSBoris Brezillon if (nfc->dma_chan)
68193db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan);
68293db446aSBoris Brezillon return ret;
68393db446aSBoris Brezillon }
68493db446aSBoris Brezillon
68593db446aSBoris Brezillon /*
68693db446aSBoris Brezillon * DMA function uses this helper to poll on CMDD bits without wanting
68793db446aSBoris Brezillon * them to be cleared.
68893db446aSBoris Brezillon */
68993db446aSBoris Brezillon if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN))
69093db446aSBoris Brezillon return 0;
69193db446aSBoris Brezillon
69293db446aSBoris Brezillon writel_relaxed(flag, nfc->regs + NDSR);
69393db446aSBoris Brezillon
69493db446aSBoris Brezillon return 0;
69593db446aSBoris Brezillon }
69693db446aSBoris Brezillon
marvell_nfc_wait_cmdd(struct nand_chip * chip)69793db446aSBoris Brezillon static int marvell_nfc_wait_cmdd(struct nand_chip *chip)
69893db446aSBoris Brezillon {
69993db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
70093db446aSBoris Brezillon int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel);
70193db446aSBoris Brezillon
70293db446aSBoris Brezillon return marvell_nfc_end_cmd(chip, cs_flag, "CMDD");
70393db446aSBoris Brezillon }
70493db446aSBoris Brezillon
marvell_nfc_poll_status(struct marvell_nfc * nfc,u32 mask,u32 expected_val,unsigned long timeout_ms)70585a3ebbbSChris Packham static int marvell_nfc_poll_status(struct marvell_nfc *nfc, u32 mask,
70685a3ebbbSChris Packham u32 expected_val, unsigned long timeout_ms)
70785a3ebbbSChris Packham {
70885a3ebbbSChris Packham unsigned long limit;
70985a3ebbbSChris Packham u32 st;
71085a3ebbbSChris Packham
71185a3ebbbSChris Packham limit = jiffies + msecs_to_jiffies(timeout_ms);
71285a3ebbbSChris Packham do {
71385a3ebbbSChris Packham st = readl_relaxed(nfc->regs + NDSR);
71485a3ebbbSChris Packham if (st & NDSR_RDY(1))
71585a3ebbbSChris Packham st |= NDSR_RDY(0);
71685a3ebbbSChris Packham
71785a3ebbbSChris Packham if ((st & mask) == expected_val)
71885a3ebbbSChris Packham return 0;
71985a3ebbbSChris Packham
72085a3ebbbSChris Packham cpu_relax();
72185a3ebbbSChris Packham } while (time_after(limit, jiffies));
72285a3ebbbSChris Packham
72385a3ebbbSChris Packham return -ETIMEDOUT;
72485a3ebbbSChris Packham }
72585a3ebbbSChris Packham
marvell_nfc_wait_op(struct nand_chip * chip,unsigned int timeout_ms)72693db446aSBoris Brezillon static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms)
72793db446aSBoris Brezillon {
72893db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
72985a3ebbbSChris Packham struct mtd_info *mtd = nand_to_mtd(chip);
730cafb56ddSMiquel Raynal u32 pending;
73193db446aSBoris Brezillon int ret;
73293db446aSBoris Brezillon
73393db446aSBoris Brezillon /* Timeout is expressed in ms */
73493db446aSBoris Brezillon if (!timeout_ms)
73593db446aSBoris Brezillon timeout_ms = IRQ_TIMEOUT;
73693db446aSBoris Brezillon
73785a3ebbbSChris Packham if (mtd->oops_panic_write) {
73885a3ebbbSChris Packham ret = marvell_nfc_poll_status(nfc, NDSR_RDY(0),
73985a3ebbbSChris Packham NDSR_RDY(0),
74085a3ebbbSChris Packham timeout_ms);
74185a3ebbbSChris Packham } else {
74293db446aSBoris Brezillon init_completion(&nfc->complete);
74393db446aSBoris Brezillon
74493db446aSBoris Brezillon marvell_nfc_enable_int(nfc, NDCR_RDYM);
74593db446aSBoris Brezillon ret = wait_for_completion_timeout(&nfc->complete,
74693db446aSBoris Brezillon msecs_to_jiffies(timeout_ms));
74793db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_RDYM);
74885a3ebbbSChris Packham }
749cafb56ddSMiquel Raynal pending = marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1));
750cafb56ddSMiquel Raynal
751cafb56ddSMiquel Raynal /*
752cafb56ddSMiquel Raynal * In case the interrupt was not served in the required time frame,
753cafb56ddSMiquel Raynal * check if the ISR was not served or if something went actually wrong.
754cafb56ddSMiquel Raynal */
755c2707577SMiquel Raynal if (!ret && !pending) {
75693db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for RB signal\n");
75793db446aSBoris Brezillon return -ETIMEDOUT;
75893db446aSBoris Brezillon }
75993db446aSBoris Brezillon
76093db446aSBoris Brezillon return 0;
76193db446aSBoris Brezillon }
76293db446aSBoris Brezillon
marvell_nfc_select_target(struct nand_chip * chip,unsigned int die_nr)763b2525141SBoris Brezillon static void marvell_nfc_select_target(struct nand_chip *chip,
764b2525141SBoris Brezillon unsigned int die_nr)
76593db446aSBoris Brezillon {
76693db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
76793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
76893db446aSBoris Brezillon u32 ndcr_generic;
76993db446aSBoris Brezillon
77093db446aSBoris Brezillon /*
77193db446aSBoris Brezillon * Reset the NDCR register to a clean state for this particular chip,
77293db446aSBoris Brezillon * also clear ND_RUN bit.
77393db446aSBoris Brezillon */
77493db446aSBoris Brezillon ndcr_generic = readl_relaxed(nfc->regs + NDCR) &
77593db446aSBoris Brezillon NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN;
77693db446aSBoris Brezillon writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR);
77793db446aSBoris Brezillon
77893db446aSBoris Brezillon /* Also reset the interrupt status register */
77993db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
78093db446aSBoris Brezillon
7819a8f612cSMiquel Raynal if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die)
7829a8f612cSMiquel Raynal return;
7839a8f612cSMiquel Raynal
7849a8f612cSMiquel Raynal writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0);
7859a8f612cSMiquel Raynal writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1);
7869a8f612cSMiquel Raynal
78793db446aSBoris Brezillon nfc->selected_chip = chip;
78893db446aSBoris Brezillon marvell_nand->selected_die = die_nr;
78993db446aSBoris Brezillon }
79093db446aSBoris Brezillon
marvell_nfc_isr(int irq,void * dev_id)79193db446aSBoris Brezillon static irqreturn_t marvell_nfc_isr(int irq, void *dev_id)
79293db446aSBoris Brezillon {
79393db446aSBoris Brezillon struct marvell_nfc *nfc = dev_id;
79493db446aSBoris Brezillon u32 st = readl_relaxed(nfc->regs + NDSR);
79593db446aSBoris Brezillon u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT;
79693db446aSBoris Brezillon
79793db446aSBoris Brezillon /*
79893db446aSBoris Brezillon * RDY interrupt mask is one bit in NDCR while there are two status
79993db446aSBoris Brezillon * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]).
80093db446aSBoris Brezillon */
80193db446aSBoris Brezillon if (st & NDSR_RDY(1))
80293db446aSBoris Brezillon st |= NDSR_RDY(0);
80393db446aSBoris Brezillon
80493db446aSBoris Brezillon if (!(st & ien))
80593db446aSBoris Brezillon return IRQ_NONE;
80693db446aSBoris Brezillon
80793db446aSBoris Brezillon marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT);
80893db446aSBoris Brezillon
80953c83b59SMiquel Raynal if (st & (NDSR_RDY(0) | NDSR_RDY(1)))
81093db446aSBoris Brezillon complete(&nfc->complete);
81193db446aSBoris Brezillon
81293db446aSBoris Brezillon return IRQ_HANDLED;
81393db446aSBoris Brezillon }
81493db446aSBoris Brezillon
81593db446aSBoris Brezillon /* HW ECC related functions */
marvell_nfc_enable_hw_ecc(struct nand_chip * chip)81693db446aSBoris Brezillon static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip)
81793db446aSBoris Brezillon {
81893db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
81993db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR);
82093db446aSBoris Brezillon
82193db446aSBoris Brezillon if (!(ndcr & NDCR_ECC_EN)) {
82293db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR);
82393db446aSBoris Brezillon
82493db446aSBoris Brezillon /*
82593db446aSBoris Brezillon * When enabling BCH, set threshold to 0 to always know the
82693db446aSBoris Brezillon * number of corrected bitflips.
82793db446aSBoris Brezillon */
828e0a564aeSMiquel Raynal if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
82993db446aSBoris Brezillon writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL);
83093db446aSBoris Brezillon }
83193db446aSBoris Brezillon }
83293db446aSBoris Brezillon
marvell_nfc_disable_hw_ecc(struct nand_chip * chip)83393db446aSBoris Brezillon static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip)
83493db446aSBoris Brezillon {
83593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
83693db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR);
83793db446aSBoris Brezillon
83893db446aSBoris Brezillon if (ndcr & NDCR_ECC_EN) {
83993db446aSBoris Brezillon writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
840e0a564aeSMiquel Raynal if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
84193db446aSBoris Brezillon writel_relaxed(0, nfc->regs + NDECCCTRL);
84293db446aSBoris Brezillon }
84393db446aSBoris Brezillon }
84493db446aSBoris Brezillon
84593db446aSBoris Brezillon /* DMA related helpers */
marvell_nfc_enable_dma(struct marvell_nfc * nfc)84693db446aSBoris Brezillon static void marvell_nfc_enable_dma(struct marvell_nfc *nfc)
84793db446aSBoris Brezillon {
84893db446aSBoris Brezillon u32 reg;
84993db446aSBoris Brezillon
85093db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR);
85193db446aSBoris Brezillon writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR);
85293db446aSBoris Brezillon }
85393db446aSBoris Brezillon
marvell_nfc_disable_dma(struct marvell_nfc * nfc)85493db446aSBoris Brezillon static void marvell_nfc_disable_dma(struct marvell_nfc *nfc)
85593db446aSBoris Brezillon {
85693db446aSBoris Brezillon u32 reg;
85793db446aSBoris Brezillon
85893db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR);
85993db446aSBoris Brezillon writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR);
86093db446aSBoris Brezillon }
86193db446aSBoris Brezillon
86293db446aSBoris Brezillon /* Read/write PIO/DMA accessors */
marvell_nfc_xfer_data_dma(struct marvell_nfc * nfc,enum dma_data_direction direction,unsigned int len)86393db446aSBoris Brezillon static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc,
86493db446aSBoris Brezillon enum dma_data_direction direction,
86593db446aSBoris Brezillon unsigned int len)
86693db446aSBoris Brezillon {
86793db446aSBoris Brezillon unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE);
86893db446aSBoris Brezillon struct dma_async_tx_descriptor *tx;
86993db446aSBoris Brezillon struct scatterlist sg;
87093db446aSBoris Brezillon dma_cookie_t cookie;
87193db446aSBoris Brezillon int ret;
87293db446aSBoris Brezillon
87393db446aSBoris Brezillon marvell_nfc_enable_dma(nfc);
87493db446aSBoris Brezillon /* Prepare the DMA transfer */
87593db446aSBoris Brezillon sg_init_one(&sg, nfc->dma_buf, dma_len);
87640c9ba0dSJack Wang ret = dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
87740c9ba0dSJack Wang if (!ret) {
87840c9ba0dSJack Wang dev_err(nfc->dev, "Could not map DMA S/G list\n");
87940c9ba0dSJack Wang return -ENXIO;
88040c9ba0dSJack Wang }
88140c9ba0dSJack Wang
88293db446aSBoris Brezillon tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1,
88393db446aSBoris Brezillon direction == DMA_FROM_DEVICE ?
88493db446aSBoris Brezillon DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
88593db446aSBoris Brezillon DMA_PREP_INTERRUPT);
88693db446aSBoris Brezillon if (!tx) {
88793db446aSBoris Brezillon dev_err(nfc->dev, "Could not prepare DMA S/G list\n");
88840c9ba0dSJack Wang dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
88993db446aSBoris Brezillon return -ENXIO;
89093db446aSBoris Brezillon }
89193db446aSBoris Brezillon
89293db446aSBoris Brezillon /* Do the task and wait for it to finish */
89393db446aSBoris Brezillon cookie = dmaengine_submit(tx);
89493db446aSBoris Brezillon ret = dma_submit_error(cookie);
89593db446aSBoris Brezillon if (ret)
89693db446aSBoris Brezillon return -EIO;
89793db446aSBoris Brezillon
89893db446aSBoris Brezillon dma_async_issue_pending(nfc->dma_chan);
89993db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(nfc->selected_chip);
90093db446aSBoris Brezillon dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
90193db446aSBoris Brezillon marvell_nfc_disable_dma(nfc);
90293db446aSBoris Brezillon if (ret) {
90393db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n",
90493db446aSBoris Brezillon dmaengine_tx_status(nfc->dma_chan, cookie, NULL));
90593db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan);
90693db446aSBoris Brezillon return -ETIMEDOUT;
90793db446aSBoris Brezillon }
90893db446aSBoris Brezillon
90993db446aSBoris Brezillon return 0;
91093db446aSBoris Brezillon }
91193db446aSBoris Brezillon
marvell_nfc_xfer_data_in_pio(struct marvell_nfc * nfc,u8 * in,unsigned int len)91293db446aSBoris Brezillon static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in,
91393db446aSBoris Brezillon unsigned int len)
91493db446aSBoris Brezillon {
91593db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH;
91693db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
91793db446aSBoris Brezillon int i;
91893db446aSBoris Brezillon
91993db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
92093db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH));
92193db446aSBoris Brezillon
92293db446aSBoris Brezillon if (last_len) {
92393db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH];
92493db446aSBoris Brezillon
92593db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
92693db446aSBoris Brezillon memcpy(in + last_full_offset, tmp_buf, last_len);
92793db446aSBoris Brezillon }
92893db446aSBoris Brezillon
92993db446aSBoris Brezillon return 0;
93093db446aSBoris Brezillon }
93193db446aSBoris Brezillon
marvell_nfc_xfer_data_out_pio(struct marvell_nfc * nfc,const u8 * out,unsigned int len)93293db446aSBoris Brezillon static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out,
93393db446aSBoris Brezillon unsigned int len)
93493db446aSBoris Brezillon {
93593db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH;
93693db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
93793db446aSBoris Brezillon int i;
93893db446aSBoris Brezillon
93993db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
94093db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH));
94193db446aSBoris Brezillon
94293db446aSBoris Brezillon if (last_len) {
94393db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH];
94493db446aSBoris Brezillon
94593db446aSBoris Brezillon memcpy(tmp_buf, out + last_full_offset, last_len);
94693db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
94793db446aSBoris Brezillon }
94893db446aSBoris Brezillon
94993db446aSBoris Brezillon return 0;
95093db446aSBoris Brezillon }
95193db446aSBoris Brezillon
marvell_nfc_check_empty_chunk(struct nand_chip * chip,u8 * data,int data_len,u8 * spare,int spare_len,u8 * ecc,int ecc_len,unsigned int * max_bitflips)95293db446aSBoris Brezillon static void marvell_nfc_check_empty_chunk(struct nand_chip *chip,
95393db446aSBoris Brezillon u8 *data, int data_len,
95493db446aSBoris Brezillon u8 *spare, int spare_len,
95593db446aSBoris Brezillon u8 *ecc, int ecc_len,
95693db446aSBoris Brezillon unsigned int *max_bitflips)
95793db446aSBoris Brezillon {
95893db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
95993db446aSBoris Brezillon int bf;
96093db446aSBoris Brezillon
96193db446aSBoris Brezillon /*
96293db446aSBoris Brezillon * Blank pages (all 0xFF) that have not been written may be recognized
96393db446aSBoris Brezillon * as bad if bitflips occur, so whenever an uncorrectable error occurs,
96493db446aSBoris Brezillon * check if the entire page (with ECC bytes) is actually blank or not.
96593db446aSBoris Brezillon */
96693db446aSBoris Brezillon if (!data)
96793db446aSBoris Brezillon data_len = 0;
96893db446aSBoris Brezillon if (!spare)
96993db446aSBoris Brezillon spare_len = 0;
97093db446aSBoris Brezillon if (!ecc)
97193db446aSBoris Brezillon ecc_len = 0;
97293db446aSBoris Brezillon
97393db446aSBoris Brezillon bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len,
97493db446aSBoris Brezillon spare, spare_len, chip->ecc.strength);
97593db446aSBoris Brezillon if (bf < 0) {
97693db446aSBoris Brezillon mtd->ecc_stats.failed++;
97793db446aSBoris Brezillon return;
97893db446aSBoris Brezillon }
97993db446aSBoris Brezillon
98093db446aSBoris Brezillon /* Update the stats and max_bitflips */
98193db446aSBoris Brezillon mtd->ecc_stats.corrected += bf;
98293db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
98393db446aSBoris Brezillon }
98493db446aSBoris Brezillon
98593db446aSBoris Brezillon /*
9861617942aSMiquel Raynal * Check if a chunk is correct or not according to the hardware ECC engine.
98793db446aSBoris Brezillon * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
98893db446aSBoris Brezillon * mtd->ecc_stats.failure is not, the function will instead return a non-zero
98993db446aSBoris Brezillon * value indicating that a check on the emptyness of the subpage must be
9901617942aSMiquel Raynal * performed before actually declaring the subpage as "corrupted".
99193db446aSBoris Brezillon */
marvell_nfc_hw_ecc_check_bitflips(struct nand_chip * chip,unsigned int * max_bitflips)9921617942aSMiquel Raynal static int marvell_nfc_hw_ecc_check_bitflips(struct nand_chip *chip,
99393db446aSBoris Brezillon unsigned int *max_bitflips)
99493db446aSBoris Brezillon {
99593db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
99693db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
99793db446aSBoris Brezillon int bf = 0;
99893db446aSBoris Brezillon u32 ndsr;
99993db446aSBoris Brezillon
100093db446aSBoris Brezillon ndsr = readl_relaxed(nfc->regs + NDSR);
100193db446aSBoris Brezillon
100293db446aSBoris Brezillon /* Check uncorrectable error flag */
100393db446aSBoris Brezillon if (ndsr & NDSR_UNCERR) {
100493db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR);
100593db446aSBoris Brezillon
100693db446aSBoris Brezillon /*
100793db446aSBoris Brezillon * Do not increment ->ecc_stats.failed now, instead, return a
100893db446aSBoris Brezillon * non-zero value to indicate that this chunk was apparently
100993db446aSBoris Brezillon * bad, and it should be check to see if it empty or not. If
101093db446aSBoris Brezillon * the chunk (with ECC bytes) is not declared empty, the calling
101193db446aSBoris Brezillon * function must increment the failure count.
101293db446aSBoris Brezillon */
101393db446aSBoris Brezillon return -EBADMSG;
101493db446aSBoris Brezillon }
101593db446aSBoris Brezillon
101693db446aSBoris Brezillon /* Check correctable error flag */
101793db446aSBoris Brezillon if (ndsr & NDSR_CORERR) {
101893db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR);
101993db446aSBoris Brezillon
1020e0a564aeSMiquel Raynal if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
102193db446aSBoris Brezillon bf = NDSR_ERRCNT(ndsr);
102293db446aSBoris Brezillon else
102393db446aSBoris Brezillon bf = 1;
102493db446aSBoris Brezillon }
102593db446aSBoris Brezillon
102693db446aSBoris Brezillon /* Update the stats and max_bitflips */
102793db446aSBoris Brezillon mtd->ecc_stats.corrected += bf;
102893db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
102993db446aSBoris Brezillon
103093db446aSBoris Brezillon return 0;
103193db446aSBoris Brezillon }
103293db446aSBoris Brezillon
103393db446aSBoris Brezillon /* Hamming read helpers */
marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip * chip,u8 * data_buf,u8 * oob_buf,bool raw,int page)103493db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip,
103593db446aSBoris Brezillon u8 *data_buf, u8 *oob_buf,
103693db446aSBoris Brezillon bool raw, int page)
103793db446aSBoris Brezillon {
103893db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
103993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
104093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
104193db446aSBoris Brezillon struct marvell_nfc_op nfc_op = {
104293db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
104393db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
104493db446aSBoris Brezillon NDCB0_DBC |
104593db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) |
104693db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART),
104793db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page),
104893db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page),
104993db446aSBoris Brezillon };
105093db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
105193db446aSBoris Brezillon int ret;
105293db446aSBoris Brezillon
105393db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */
105493db446aSBoris Brezillon if (nfc->caps->is_nfcv2)
105593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
105693db446aSBoris Brezillon
105793db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
105893db446aSBoris Brezillon if (ret)
105993db446aSBoris Brezillon return ret;
106093db446aSBoris Brezillon
106193db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
106293db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
106393db446aSBoris Brezillon "RDDREQ while draining FIFO (data/oob)");
106493db446aSBoris Brezillon if (ret)
106593db446aSBoris Brezillon return ret;
106693db446aSBoris Brezillon
106793db446aSBoris Brezillon /*
106893db446aSBoris Brezillon * Read the page then the OOB area. Unlike what is shown in current
106993db446aSBoris Brezillon * documentation, spare bytes are protected by the ECC engine, and must
107093db446aSBoris Brezillon * be at the beginning of the OOB area or running this driver on legacy
107193db446aSBoris Brezillon * systems will prevent the discovery of the BBM/BBT.
107293db446aSBoris Brezillon */
107393db446aSBoris Brezillon if (nfc->use_dma) {
107493db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE,
107593db446aSBoris Brezillon lt->data_bytes + oob_bytes);
107693db446aSBoris Brezillon memcpy(data_buf, nfc->dma_buf, lt->data_bytes);
107793db446aSBoris Brezillon memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes);
107893db446aSBoris Brezillon } else {
107993db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes);
108093db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes);
108193db446aSBoris Brezillon }
108293db446aSBoris Brezillon
108393db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip);
108493db446aSBoris Brezillon return ret;
108593db446aSBoris Brezillon }
108693db446aSBoris Brezillon
marvell_nfc_hw_ecc_hmg_read_page_raw(struct nand_chip * chip,u8 * buf,int oob_required,int page)1087b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct nand_chip *chip, u8 *buf,
108893db446aSBoris Brezillon int oob_required, int page)
108993db446aSBoris Brezillon {
1090b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
109193db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
109293db446aSBoris Brezillon true, page);
109393db446aSBoris Brezillon }
109493db446aSBoris Brezillon
marvell_nfc_hw_ecc_hmg_read_page(struct nand_chip * chip,u8 * buf,int oob_required,int page)1095b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page(struct nand_chip *chip, u8 *buf,
1096b9761687SBoris Brezillon int oob_required, int page)
109793db446aSBoris Brezillon {
109893db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
109993db446aSBoris Brezillon unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
110093db446aSBoris Brezillon int max_bitflips = 0, ret;
110193db446aSBoris Brezillon u8 *raw_buf;
110293db446aSBoris Brezillon
1103b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
110493db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip);
110593db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false,
110693db446aSBoris Brezillon page);
11071617942aSMiquel Raynal ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
110893db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip);
110993db446aSBoris Brezillon
111093db446aSBoris Brezillon if (!ret)
111193db446aSBoris Brezillon return max_bitflips;
111293db446aSBoris Brezillon
111393db446aSBoris Brezillon /*
111493db446aSBoris Brezillon * When ECC failures are detected, check if the full page has been
111593db446aSBoris Brezillon * written or not. Ignore the failure if it is actually empty.
111693db446aSBoris Brezillon */
111793db446aSBoris Brezillon raw_buf = kmalloc(full_sz, GFP_KERNEL);
111893db446aSBoris Brezillon if (!raw_buf)
111993db446aSBoris Brezillon return -ENOMEM;
112093db446aSBoris Brezillon
112193db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf +
112293db446aSBoris Brezillon lt->data_bytes, true, page);
112393db446aSBoris Brezillon marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0,
112493db446aSBoris Brezillon &max_bitflips);
112593db446aSBoris Brezillon kfree(raw_buf);
112693db446aSBoris Brezillon
112793db446aSBoris Brezillon return max_bitflips;
112893db446aSBoris Brezillon }
112993db446aSBoris Brezillon
113093db446aSBoris Brezillon /*
113193db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if
113293db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->read_oob_raw() function
113393db446aSBoris Brezillon * also stands for ->read_oob().
113493db446aSBoris Brezillon */
marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip * chip,int page)1135b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page)
113693db446aSBoris Brezillon {
1137eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip);
113893db446aSBoris Brezillon
1139b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
1140eeab7174SBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
1141eeab7174SBoris Brezillon true, page);
114293db446aSBoris Brezillon }
114393db446aSBoris Brezillon
114493db446aSBoris Brezillon /* Hamming write helpers */
marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip * chip,const u8 * data_buf,const u8 * oob_buf,bool raw,int page)114593db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip,
114693db446aSBoris Brezillon const u8 *data_buf,
114793db446aSBoris Brezillon const u8 *oob_buf, bool raw,
114893db446aSBoris Brezillon int page)
114993db446aSBoris Brezillon {
1150e0160cd4SMiquel Raynal const struct nand_sdr_timings *sdr =
1151e0160cd4SMiquel Raynal nand_get_sdr_timings(nand_get_interface_config(chip));
115293db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
115393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
115493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
115593db446aSBoris Brezillon struct marvell_nfc_op nfc_op = {
115693db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) |
115793db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
115893db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN) |
115993db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_PAGEPROG) |
116093db446aSBoris Brezillon NDCB0_DBC,
116193db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page),
116293db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page),
116393db446aSBoris Brezillon };
116493db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
11653e01d525SMiquel Raynal u8 status;
116693db446aSBoris Brezillon int ret;
116793db446aSBoris Brezillon
116893db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */
116993db446aSBoris Brezillon if (nfc->caps->is_nfcv2)
117093db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
117193db446aSBoris Brezillon
117293db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
117393db446aSBoris Brezillon if (ret)
117493db446aSBoris Brezillon return ret;
117593db446aSBoris Brezillon
117693db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
117793db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
117893db446aSBoris Brezillon "WRDREQ while loading FIFO (data)");
117993db446aSBoris Brezillon if (ret)
118093db446aSBoris Brezillon return ret;
118193db446aSBoris Brezillon
118293db446aSBoris Brezillon /* Write the page then the OOB area */
118393db446aSBoris Brezillon if (nfc->use_dma) {
118493db446aSBoris Brezillon memcpy(nfc->dma_buf, data_buf, lt->data_bytes);
118593db446aSBoris Brezillon memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes);
118693db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes +
118793db446aSBoris Brezillon lt->ecc_bytes + lt->spare_bytes);
118893db446aSBoris Brezillon } else {
118993db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes);
119093db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes);
119193db446aSBoris Brezillon }
119293db446aSBoris Brezillon
119393db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip);
119493db446aSBoris Brezillon if (ret)
119593db446aSBoris Brezillon return ret;
119693db446aSBoris Brezillon
119793db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip,
1198e0160cd4SMiquel Raynal PSEC_TO_MSEC(sdr->tPROG_max));
11993e01d525SMiquel Raynal if (ret)
120093db446aSBoris Brezillon return ret;
12013e01d525SMiquel Raynal
12023e01d525SMiquel Raynal /* Check write status on the chip side */
12033e01d525SMiquel Raynal ret = nand_status_op(chip, &status);
12043e01d525SMiquel Raynal if (ret)
12053e01d525SMiquel Raynal return ret;
12063e01d525SMiquel Raynal
12073e01d525SMiquel Raynal if (status & NAND_STATUS_FAIL)
12083e01d525SMiquel Raynal return -EIO;
12093e01d525SMiquel Raynal
12103e01d525SMiquel Raynal return 0;
121193db446aSBoris Brezillon }
121293db446aSBoris Brezillon
marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip * chip,const u8 * buf,int oob_required,int page)1213767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip *chip,
121493db446aSBoris Brezillon const u8 *buf,
121593db446aSBoris Brezillon int oob_required, int page)
121693db446aSBoris Brezillon {
1217b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
121893db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
121993db446aSBoris Brezillon true, page);
122093db446aSBoris Brezillon }
122193db446aSBoris Brezillon
marvell_nfc_hw_ecc_hmg_write_page(struct nand_chip * chip,const u8 * buf,int oob_required,int page)1222767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page(struct nand_chip *chip,
122393db446aSBoris Brezillon const u8 *buf,
122493db446aSBoris Brezillon int oob_required, int page)
122593db446aSBoris Brezillon {
122693db446aSBoris Brezillon int ret;
122793db446aSBoris Brezillon
1228b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
122993db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip);
123093db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
123193db446aSBoris Brezillon false, page);
123293db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip);
123393db446aSBoris Brezillon
123493db446aSBoris Brezillon return ret;
123593db446aSBoris Brezillon }
123693db446aSBoris Brezillon
123793db446aSBoris Brezillon /*
123893db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if
123993db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->write_oob_raw() function
124093db446aSBoris Brezillon * also stands for ->write_oob().
124193db446aSBoris Brezillon */
marvell_nfc_hw_ecc_hmg_write_oob_raw(struct nand_chip * chip,int page)1242767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct nand_chip *chip,
124393db446aSBoris Brezillon int page)
124493db446aSBoris Brezillon {
1245767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
1246eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip);
1247767eb6fbSBoris Brezillon
1248eeab7174SBoris Brezillon memset(buf, 0xFF, mtd->writesize);
124993db446aSBoris Brezillon
1250b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
1251eeab7174SBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1252eeab7174SBoris Brezillon true, page);
125393db446aSBoris Brezillon }
125493db446aSBoris Brezillon
125593db446aSBoris Brezillon /* BCH read helpers */
marvell_nfc_hw_ecc_bch_read_page_raw(struct nand_chip * chip,u8 * buf,int oob_required,int page)1256b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page_raw(struct nand_chip *chip, u8 *buf,
125793db446aSBoris Brezillon int oob_required, int page)
125893db446aSBoris Brezillon {
1259b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
126093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
126193db446aSBoris Brezillon u8 *oob = chip->oob_poi;
126293db446aSBoris Brezillon int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
126393db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
126493db446aSBoris Brezillon lt->last_spare_bytes;
126593db446aSBoris Brezillon int data_len = lt->data_bytes;
126693db446aSBoris Brezillon int spare_len = lt->spare_bytes;
126793db446aSBoris Brezillon int ecc_len = lt->ecc_bytes;
126893db446aSBoris Brezillon int chunk;
126993db446aSBoris Brezillon
1270b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
1271b2525141SBoris Brezillon
127293db446aSBoris Brezillon if (oob_required)
127393db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize);
127493db446aSBoris Brezillon
127593db446aSBoris Brezillon nand_read_page_op(chip, page, 0, NULL, 0);
127693db446aSBoris Brezillon
127793db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) {
127893db446aSBoris Brezillon /* Update last chunk length */
127993db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) {
128093db446aSBoris Brezillon data_len = lt->last_data_bytes;
128193db446aSBoris Brezillon spare_len = lt->last_spare_bytes;
128293db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes;
128393db446aSBoris Brezillon }
128493db446aSBoris Brezillon
128593db446aSBoris Brezillon /* Read data bytes*/
128693db446aSBoris Brezillon nand_change_read_column_op(chip, chunk * chunk_size,
128793db446aSBoris Brezillon buf + (lt->data_bytes * chunk),
128893db446aSBoris Brezillon data_len, false);
128993db446aSBoris Brezillon
129093db446aSBoris Brezillon /* Read spare bytes */
129193db446aSBoris Brezillon nand_read_data_op(chip, oob + (lt->spare_bytes * chunk),
1292b451f5beSMiquel Raynal spare_len, false, false);
129393db446aSBoris Brezillon
129493db446aSBoris Brezillon /* Read ECC bytes */
129593db446aSBoris Brezillon nand_read_data_op(chip, oob + ecc_offset +
129693db446aSBoris Brezillon (ALIGN(lt->ecc_bytes, 32) * chunk),
1297b451f5beSMiquel Raynal ecc_len, false, false);
129893db446aSBoris Brezillon }
129993db446aSBoris Brezillon
130093db446aSBoris Brezillon return 0;
130193db446aSBoris Brezillon }
130293db446aSBoris Brezillon
marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip * chip,int chunk,u8 * data,unsigned int data_len,u8 * spare,unsigned int spare_len,int page)130393db446aSBoris Brezillon static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk,
130493db446aSBoris Brezillon u8 *data, unsigned int data_len,
130593db446aSBoris Brezillon u8 *spare, unsigned int spare_len,
130693db446aSBoris Brezillon int page)
130793db446aSBoris Brezillon {
130893db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
130993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
131093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
131193db446aSBoris Brezillon int i, ret;
131293db446aSBoris Brezillon struct marvell_nfc_op nfc_op = {
131393db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
131493db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
131593db446aSBoris Brezillon NDCB0_LEN_OVRD,
131693db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page),
131793db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page),
131893db446aSBoris Brezillon .ndcb[3] = data_len + spare_len,
131993db446aSBoris Brezillon };
132093db446aSBoris Brezillon
132193db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
132293db446aSBoris Brezillon if (ret)
132393db446aSBoris Brezillon return;
132493db446aSBoris Brezillon
132593db446aSBoris Brezillon if (chunk == 0)
132693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_DBC |
132793db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) |
132893db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART);
132993db446aSBoris Brezillon
133093db446aSBoris Brezillon /*
133190d61763SBoris Brezillon * Trigger the monolithic read on the first chunk, then naked read on
133290d61763SBoris Brezillon * intermediate chunks and finally a last naked read on the last chunk.
133393db446aSBoris Brezillon */
133490d61763SBoris Brezillon if (chunk == 0)
133593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
133690d61763SBoris Brezillon else if (chunk < lt->nchunks - 1)
133790d61763SBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW);
133893db446aSBoris Brezillon else
133993db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
134093db446aSBoris Brezillon
134193db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
134293db446aSBoris Brezillon
134393db446aSBoris Brezillon /*
134493db446aSBoris Brezillon * According to the datasheet, when reading from NDDB
134593db446aSBoris Brezillon * with BCH enabled, after each 32 bytes reads, we
134693db446aSBoris Brezillon * have to make sure that the NDSR.RDDREQ bit is set.
134793db446aSBoris Brezillon *
134893db446aSBoris Brezillon * Drain the FIFO, 8 32-bit reads at a time, and skip
134993db446aSBoris Brezillon * the polling on the last read.
135093db446aSBoris Brezillon *
135193db446aSBoris Brezillon * Length is a multiple of 32 bytes, hence it is a multiple of 8 too.
135293db446aSBoris Brezillon */
135393db446aSBoris Brezillon for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
135493db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
135593db446aSBoris Brezillon "RDDREQ while draining FIFO (data)");
135693db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data,
135793db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS);
135893db446aSBoris Brezillon data += FIFO_DEPTH * BCH_SEQ_READS;
135993db446aSBoris Brezillon }
136093db446aSBoris Brezillon
136193db446aSBoris Brezillon for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
136293db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
136393db446aSBoris Brezillon "RDDREQ while draining FIFO (OOB)");
136493db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, spare,
136593db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS);
136693db446aSBoris Brezillon spare += FIFO_DEPTH * BCH_SEQ_READS;
136793db446aSBoris Brezillon }
136893db446aSBoris Brezillon }
136993db446aSBoris Brezillon
marvell_nfc_hw_ecc_bch_read_page(struct nand_chip * chip,u8 * buf,int oob_required,int page)1370b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page(struct nand_chip *chip,
137193db446aSBoris Brezillon u8 *buf, int oob_required,
137293db446aSBoris Brezillon int page)
137393db446aSBoris Brezillon {
1374b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
137593db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1376dbfc6718SMiquel Raynal int data_len = lt->data_bytes, spare_len = lt->spare_bytes;
1377dbfc6718SMiquel Raynal u8 *data = buf, *spare = chip->oob_poi;
137893db446aSBoris Brezillon int max_bitflips = 0;
137993db446aSBoris Brezillon u32 failure_mask = 0;
1380dbfc6718SMiquel Raynal int chunk, ret;
138193db446aSBoris Brezillon
1382b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
1383b2525141SBoris Brezillon
138493db446aSBoris Brezillon /*
138593db446aSBoris Brezillon * With BCH, OOB is not fully used (and thus not read entirely), not
138693db446aSBoris Brezillon * expected bytes could show up at the end of the OOB buffer if not
138793db446aSBoris Brezillon * explicitly erased.
138893db446aSBoris Brezillon */
138993db446aSBoris Brezillon if (oob_required)
139093db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize);
139193db446aSBoris Brezillon
139293db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip);
139393db446aSBoris Brezillon
139493db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) {
139593db446aSBoris Brezillon /* Update length for the last chunk */
139693db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) {
139793db446aSBoris Brezillon data_len = lt->last_data_bytes;
139893db446aSBoris Brezillon spare_len = lt->last_spare_bytes;
139993db446aSBoris Brezillon }
140093db446aSBoris Brezillon
140193db446aSBoris Brezillon /* Read the chunk and detect number of bitflips */
140293db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len,
140393db446aSBoris Brezillon spare, spare_len, page);
14041617942aSMiquel Raynal ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
140593db446aSBoris Brezillon if (ret)
140693db446aSBoris Brezillon failure_mask |= BIT(chunk);
140793db446aSBoris Brezillon
140893db446aSBoris Brezillon data += data_len;
140993db446aSBoris Brezillon spare += spare_len;
141093db446aSBoris Brezillon }
141193db446aSBoris Brezillon
141293db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip);
141393db446aSBoris Brezillon
141493db446aSBoris Brezillon if (!failure_mask)
141593db446aSBoris Brezillon return max_bitflips;
141693db446aSBoris Brezillon
141793db446aSBoris Brezillon /*
141893db446aSBoris Brezillon * Please note that dumping the ECC bytes during a normal read with OOB
141993db446aSBoris Brezillon * area would add a significant overhead as ECC bytes are "consumed" by
142093db446aSBoris Brezillon * the controller in normal mode and must be re-read in raw mode. To
142193db446aSBoris Brezillon * avoid dropping the performances, we prefer not to include them. The
142293db446aSBoris Brezillon * user should re-read the page in raw mode if ECC bytes are required.
1423dbfc6718SMiquel Raynal */
1424dbfc6718SMiquel Raynal
1425dbfc6718SMiquel Raynal /*
14261617942aSMiquel Raynal * In case there is any subpage read error, we usually re-read only ECC
14271617942aSMiquel Raynal * bytes in raw mode and check if the whole page is empty. In this case,
14281617942aSMiquel Raynal * it is normal that the ECC check failed and we just ignore the error.
142993db446aSBoris Brezillon *
14307fd130f7SMiquel Raynal * However, it has been empirically observed that for some layouts (e.g
14317fd130f7SMiquel Raynal * 2k page, 8b strength per 512B chunk), the controller tries to correct
14327fd130f7SMiquel Raynal * bits and may create itself bitflips in the erased area. To overcome
14337fd130f7SMiquel Raynal * this strange behavior, the whole page is re-read in raw mode, not
14347fd130f7SMiquel Raynal * only the ECC bytes.
143593db446aSBoris Brezillon */
143693db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) {
1437dbfc6718SMiquel Raynal int data_off_in_page, spare_off_in_page, ecc_off_in_page;
1438dbfc6718SMiquel Raynal int data_off, spare_off, ecc_off;
1439dbfc6718SMiquel Raynal int data_len, spare_len, ecc_len;
1440dbfc6718SMiquel Raynal
144193db446aSBoris Brezillon /* No failure reported for this chunk, move to the next one */
144293db446aSBoris Brezillon if (!(failure_mask & BIT(chunk)))
144393db446aSBoris Brezillon continue;
144493db446aSBoris Brezillon
1445dbfc6718SMiquel Raynal data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes +
1446dbfc6718SMiquel Raynal lt->ecc_bytes);
1447dbfc6718SMiquel Raynal spare_off_in_page = data_off_in_page +
1448dbfc6718SMiquel Raynal (chunk < lt->full_chunk_cnt ? lt->data_bytes :
1449dbfc6718SMiquel Raynal lt->last_data_bytes);
1450dbfc6718SMiquel Raynal ecc_off_in_page = spare_off_in_page +
1451dbfc6718SMiquel Raynal (chunk < lt->full_chunk_cnt ? lt->spare_bytes :
1452dbfc6718SMiquel Raynal lt->last_spare_bytes);
1453dbfc6718SMiquel Raynal
1454dbfc6718SMiquel Raynal data_off = chunk * lt->data_bytes;
1455dbfc6718SMiquel Raynal spare_off = chunk * lt->spare_bytes;
1456dbfc6718SMiquel Raynal ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) +
145793db446aSBoris Brezillon lt->last_spare_bytes +
1458dbfc6718SMiquel Raynal (chunk * (lt->ecc_bytes + 2));
145993db446aSBoris Brezillon
1460dbfc6718SMiquel Raynal data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes :
1461dbfc6718SMiquel Raynal lt->last_data_bytes;
1462dbfc6718SMiquel Raynal spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes :
1463dbfc6718SMiquel Raynal lt->last_spare_bytes;
1464dbfc6718SMiquel Raynal ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes :
1465dbfc6718SMiquel Raynal lt->last_ecc_bytes;
146693db446aSBoris Brezillon
14677fd130f7SMiquel Raynal /*
14687fd130f7SMiquel Raynal * Only re-read the ECC bytes, unless we are using the 2k/8b
14697fd130f7SMiquel Raynal * layout which is buggy in the sense that the ECC engine will
14707fd130f7SMiquel Raynal * try to correct data bytes anyway, creating bitflips. In this
14717fd130f7SMiquel Raynal * case, re-read the entire page.
14727fd130f7SMiquel Raynal */
14737fd130f7SMiquel Raynal if (lt->writesize == 2048 && lt->strength == 8) {
14747fd130f7SMiquel Raynal nand_change_read_column_op(chip, data_off_in_page,
14757fd130f7SMiquel Raynal buf + data_off, data_len,
14767fd130f7SMiquel Raynal false);
14777fd130f7SMiquel Raynal nand_change_read_column_op(chip, spare_off_in_page,
14787fd130f7SMiquel Raynal chip->oob_poi + spare_off, spare_len,
14797fd130f7SMiquel Raynal false);
14807fd130f7SMiquel Raynal }
14817fd130f7SMiquel Raynal
1482dbfc6718SMiquel Raynal nand_change_read_column_op(chip, ecc_off_in_page,
1483dbfc6718SMiquel Raynal chip->oob_poi + ecc_off, ecc_len,
1484dbfc6718SMiquel Raynal false);
148593db446aSBoris Brezillon
148693db446aSBoris Brezillon /* Check the entire chunk (data + spare + ecc) for emptyness */
1487dbfc6718SMiquel Raynal marvell_nfc_check_empty_chunk(chip, buf + data_off, data_len,
1488dbfc6718SMiquel Raynal chip->oob_poi + spare_off, spare_len,
1489dbfc6718SMiquel Raynal chip->oob_poi + ecc_off, ecc_len,
149093db446aSBoris Brezillon &max_bitflips);
149193db446aSBoris Brezillon }
149293db446aSBoris Brezillon
149393db446aSBoris Brezillon return max_bitflips;
149493db446aSBoris Brezillon }
149593db446aSBoris Brezillon
marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip * chip,int page)1496b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page)
149793db446aSBoris Brezillon {
1498eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip);
149993db446aSBoris Brezillon
1500eeab7174SBoris Brezillon return chip->ecc.read_page_raw(chip, buf, true, page);
150193db446aSBoris Brezillon }
150293db446aSBoris Brezillon
marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip * chip,int page)1503b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page)
150493db446aSBoris Brezillon {
1505eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip);
150693db446aSBoris Brezillon
1507eeab7174SBoris Brezillon return chip->ecc.read_page(chip, buf, true, page);
150893db446aSBoris Brezillon }
150993db446aSBoris Brezillon
151093db446aSBoris Brezillon /* BCH write helpers */
marvell_nfc_hw_ecc_bch_write_page_raw(struct nand_chip * chip,const u8 * buf,int oob_required,int page)1511767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page_raw(struct nand_chip *chip,
151293db446aSBoris Brezillon const u8 *buf,
151393db446aSBoris Brezillon int oob_required, int page)
151493db446aSBoris Brezillon {
151593db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
151693db446aSBoris Brezillon int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
151793db446aSBoris Brezillon int data_len = lt->data_bytes;
151893db446aSBoris Brezillon int spare_len = lt->spare_bytes;
151993db446aSBoris Brezillon int ecc_len = lt->ecc_bytes;
152093db446aSBoris Brezillon int spare_offset = 0;
152193db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
152293db446aSBoris Brezillon lt->last_spare_bytes;
152393db446aSBoris Brezillon int chunk;
152493db446aSBoris Brezillon
1525b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
1526b2525141SBoris Brezillon
152793db446aSBoris Brezillon nand_prog_page_begin_op(chip, page, 0, NULL, 0);
152893db446aSBoris Brezillon
152993db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) {
153093db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) {
153193db446aSBoris Brezillon data_len = lt->last_data_bytes;
153293db446aSBoris Brezillon spare_len = lt->last_spare_bytes;
153393db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes;
153493db446aSBoris Brezillon }
153593db446aSBoris Brezillon
153693db446aSBoris Brezillon /* Point to the column of the next chunk */
153793db446aSBoris Brezillon nand_change_write_column_op(chip, chunk * full_chunk_size,
153893db446aSBoris Brezillon NULL, 0, false);
153993db446aSBoris Brezillon
154093db446aSBoris Brezillon /* Write the data */
154193db446aSBoris Brezillon nand_write_data_op(chip, buf + (chunk * lt->data_bytes),
154293db446aSBoris Brezillon data_len, false);
154393db446aSBoris Brezillon
154493db446aSBoris Brezillon if (!oob_required)
154593db446aSBoris Brezillon continue;
154693db446aSBoris Brezillon
154793db446aSBoris Brezillon /* Write the spare bytes */
154893db446aSBoris Brezillon if (spare_len)
154993db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + spare_offset,
155093db446aSBoris Brezillon spare_len, false);
155193db446aSBoris Brezillon
155293db446aSBoris Brezillon /* Write the ECC bytes */
155393db446aSBoris Brezillon if (ecc_len)
155493db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + ecc_offset,
155593db446aSBoris Brezillon ecc_len, false);
155693db446aSBoris Brezillon
155793db446aSBoris Brezillon spare_offset += spare_len;
155893db446aSBoris Brezillon ecc_offset += ALIGN(ecc_len, 32);
155993db446aSBoris Brezillon }
156093db446aSBoris Brezillon
156193db446aSBoris Brezillon return nand_prog_page_end_op(chip);
156293db446aSBoris Brezillon }
156393db446aSBoris Brezillon
156493db446aSBoris Brezillon static int
marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip * chip,int chunk,const u8 * data,unsigned int data_len,const u8 * spare,unsigned int spare_len,int page)156593db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk,
156693db446aSBoris Brezillon const u8 *data, unsigned int data_len,
156793db446aSBoris Brezillon const u8 *spare, unsigned int spare_len,
156893db446aSBoris Brezillon int page)
156993db446aSBoris Brezillon {
157093db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
157193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
157293db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1573a2ee41fdSMiquel Raynal u32 xtype;
157493db446aSBoris Brezillon int ret;
157593db446aSBoris Brezillon struct marvell_nfc_op nfc_op = {
157693db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD,
157793db446aSBoris Brezillon .ndcb[3] = data_len + spare_len,
157893db446aSBoris Brezillon };
157993db446aSBoris Brezillon
158093db446aSBoris Brezillon /*
158193db446aSBoris Brezillon * First operation dispatches the CMD_SEQIN command, issue the address
158293db446aSBoris Brezillon * cycles and asks for the first chunk of data.
158393db446aSBoris Brezillon * All operations in the middle (if any) will issue a naked write and
158493db446aSBoris Brezillon * also ask for data.
158593db446aSBoris Brezillon * Last operation (if any) asks for the last chunk of data through a
158693db446aSBoris Brezillon * last naked write.
158793db446aSBoris Brezillon */
158893db446aSBoris Brezillon if (chunk == 0) {
1589a2ee41fdSMiquel Raynal if (lt->nchunks == 1)
1590a2ee41fdSMiquel Raynal xtype = XTYPE_MONOLITHIC_RW;
1591a2ee41fdSMiquel Raynal else
1592a2ee41fdSMiquel Raynal xtype = XTYPE_WRITE_DISPATCH;
1593a2ee41fdSMiquel Raynal
1594a2ee41fdSMiquel Raynal nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) |
159593db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
159693db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN);
159793db446aSBoris Brezillon nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
159893db446aSBoris Brezillon nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page);
159993db446aSBoris Brezillon } else if (chunk < lt->nchunks - 1) {
160093db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW);
160193db446aSBoris Brezillon } else {
160293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
160393db446aSBoris Brezillon }
160493db446aSBoris Brezillon
160593db446aSBoris Brezillon /* Always dispatch the PAGEPROG command on the last chunk */
160693db446aSBoris Brezillon if (chunk == lt->nchunks - 1)
160793db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC;
160893db446aSBoris Brezillon
160993db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
161093db446aSBoris Brezillon if (ret)
161193db446aSBoris Brezillon return ret;
161293db446aSBoris Brezillon
161393db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
161493db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
161593db446aSBoris Brezillon "WRDREQ while loading FIFO (data)");
161693db446aSBoris Brezillon if (ret)
161793db446aSBoris Brezillon return ret;
161893db446aSBoris Brezillon
161993db446aSBoris Brezillon /* Transfer the contents */
162093db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len));
162193db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len));
162293db446aSBoris Brezillon
162393db446aSBoris Brezillon return 0;
162493db446aSBoris Brezillon }
162593db446aSBoris Brezillon
marvell_nfc_hw_ecc_bch_write_page(struct nand_chip * chip,const u8 * buf,int oob_required,int page)1626767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip,
162793db446aSBoris Brezillon const u8 *buf,
162893db446aSBoris Brezillon int oob_required, int page)
162993db446aSBoris Brezillon {
1630e0160cd4SMiquel Raynal const struct nand_sdr_timings *sdr =
1631e0160cd4SMiquel Raynal nand_get_sdr_timings(nand_get_interface_config(chip));
1632767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
163393db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
163493db446aSBoris Brezillon const u8 *data = buf;
163593db446aSBoris Brezillon const u8 *spare = chip->oob_poi;
163693db446aSBoris Brezillon int data_len = lt->data_bytes;
163793db446aSBoris Brezillon int spare_len = lt->spare_bytes;
163893db446aSBoris Brezillon int chunk, ret;
16393e01d525SMiquel Raynal u8 status;
164093db446aSBoris Brezillon
1641b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs);
1642b2525141SBoris Brezillon
164393db446aSBoris Brezillon /* Spare data will be written anyway, so clear it to avoid garbage */
164493db446aSBoris Brezillon if (!oob_required)
164593db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize);
164693db446aSBoris Brezillon
164793db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip);
164893db446aSBoris Brezillon
164993db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) {
165093db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) {
165193db446aSBoris Brezillon data_len = lt->last_data_bytes;
165293db446aSBoris Brezillon spare_len = lt->last_spare_bytes;
165393db446aSBoris Brezillon }
165493db446aSBoris Brezillon
165593db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len,
165693db446aSBoris Brezillon spare, spare_len, page);
165793db446aSBoris Brezillon data += data_len;
165893db446aSBoris Brezillon spare += spare_len;
165993db446aSBoris Brezillon
166093db446aSBoris Brezillon /*
166193db446aSBoris Brezillon * Waiting only for CMDD or PAGED is not enough, ECC are
166293db446aSBoris Brezillon * partially written. No flag is set once the operation is
166393db446aSBoris Brezillon * really finished but the ND_RUN bit is cleared, so wait for it
166493db446aSBoris Brezillon * before stepping into the next command.
166593db446aSBoris Brezillon */
166693db446aSBoris Brezillon marvell_nfc_wait_ndrun(chip);
166793db446aSBoris Brezillon }
166893db446aSBoris Brezillon
1669e0160cd4SMiquel Raynal ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max));
167093db446aSBoris Brezillon
167193db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip);
167293db446aSBoris Brezillon
167393db446aSBoris Brezillon if (ret)
167493db446aSBoris Brezillon return ret;
167593db446aSBoris Brezillon
16763e01d525SMiquel Raynal /* Check write status on the chip side */
16773e01d525SMiquel Raynal ret = nand_status_op(chip, &status);
16783e01d525SMiquel Raynal if (ret)
16793e01d525SMiquel Raynal return ret;
16803e01d525SMiquel Raynal
16813e01d525SMiquel Raynal if (status & NAND_STATUS_FAIL)
16823e01d525SMiquel Raynal return -EIO;
16833e01d525SMiquel Raynal
168493db446aSBoris Brezillon return 0;
168593db446aSBoris Brezillon }
168693db446aSBoris Brezillon
marvell_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip * chip,int page)1687767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip *chip,
168893db446aSBoris Brezillon int page)
168993db446aSBoris Brezillon {
1690767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
1691eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip);
1692767eb6fbSBoris Brezillon
1693eeab7174SBoris Brezillon memset(buf, 0xFF, mtd->writesize);
169493db446aSBoris Brezillon
1695eeab7174SBoris Brezillon return chip->ecc.write_page_raw(chip, buf, true, page);
169693db446aSBoris Brezillon }
169793db446aSBoris Brezillon
marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip * chip,int page)1698767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page)
169993db446aSBoris Brezillon {
1700767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
1701eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip);
1702767eb6fbSBoris Brezillon
1703eeab7174SBoris Brezillon memset(buf, 0xFF, mtd->writesize);
170493db446aSBoris Brezillon
1705eeab7174SBoris Brezillon return chip->ecc.write_page(chip, buf, true, page);
170693db446aSBoris Brezillon }
170793db446aSBoris Brezillon
170893db446aSBoris Brezillon /* NAND framework ->exec_op() hooks and related helpers */
marvell_nfc_parse_instructions(struct nand_chip * chip,const struct nand_subop * subop,struct marvell_nfc_op * nfc_op)170993db446aSBoris Brezillon static void marvell_nfc_parse_instructions(struct nand_chip *chip,
171093db446aSBoris Brezillon const struct nand_subop *subop,
171193db446aSBoris Brezillon struct marvell_nfc_op *nfc_op)
171293db446aSBoris Brezillon {
171393db446aSBoris Brezillon const struct nand_op_instr *instr = NULL;
171493db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
171593db446aSBoris Brezillon bool first_cmd = true;
171693db446aSBoris Brezillon unsigned int op_id;
171793db446aSBoris Brezillon int i;
171893db446aSBoris Brezillon
171993db446aSBoris Brezillon /* Reset the input structure as most of its fields will be OR'ed */
172093db446aSBoris Brezillon memset(nfc_op, 0, sizeof(struct marvell_nfc_op));
172193db446aSBoris Brezillon
172293db446aSBoris Brezillon for (op_id = 0; op_id < subop->ninstrs; op_id++) {
172393db446aSBoris Brezillon unsigned int offset, naddrs;
172493db446aSBoris Brezillon const u8 *addrs;
172521a26806SMiquel Raynal int len;
172693db446aSBoris Brezillon
172793db446aSBoris Brezillon instr = &subop->instrs[op_id];
172893db446aSBoris Brezillon
172993db446aSBoris Brezillon switch (instr->type) {
173093db446aSBoris Brezillon case NAND_OP_CMD_INSTR:
173193db446aSBoris Brezillon if (first_cmd)
173293db446aSBoris Brezillon nfc_op->ndcb[0] |=
173393db446aSBoris Brezillon NDCB0_CMD1(instr->ctx.cmd.opcode);
173493db446aSBoris Brezillon else
173593db446aSBoris Brezillon nfc_op->ndcb[0] |=
173693db446aSBoris Brezillon NDCB0_CMD2(instr->ctx.cmd.opcode) |
173793db446aSBoris Brezillon NDCB0_DBC;
173893db446aSBoris Brezillon
173993db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns;
174093db446aSBoris Brezillon first_cmd = false;
174193db446aSBoris Brezillon break;
174293db446aSBoris Brezillon
174393db446aSBoris Brezillon case NAND_OP_ADDR_INSTR:
174493db446aSBoris Brezillon offset = nand_subop_get_addr_start_off(subop, op_id);
174593db446aSBoris Brezillon naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
174693db446aSBoris Brezillon addrs = &instr->ctx.addr.addrs[offset];
174793db446aSBoris Brezillon
174893db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs);
174993db446aSBoris Brezillon
175093db446aSBoris Brezillon for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
175193db446aSBoris Brezillon nfc_op->ndcb[1] |= addrs[i] << (8 * i);
175293db446aSBoris Brezillon
175393db446aSBoris Brezillon if (naddrs >= 5)
175493db446aSBoris Brezillon nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]);
175593db446aSBoris Brezillon if (naddrs >= 6)
175693db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]);
175793db446aSBoris Brezillon if (naddrs == 7)
175893db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]);
175993db446aSBoris Brezillon
176093db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns;
176193db446aSBoris Brezillon break;
176293db446aSBoris Brezillon
176393db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR:
176493db446aSBoris Brezillon nfc_op->data_instr = instr;
176593db446aSBoris Brezillon nfc_op->data_instr_idx = op_id;
176693db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ);
176793db446aSBoris Brezillon if (nfc->caps->is_nfcv2) {
176893db446aSBoris Brezillon nfc_op->ndcb[0] |=
176993db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
177093db446aSBoris Brezillon NDCB0_LEN_OVRD;
177121a26806SMiquel Raynal len = nand_subop_get_data_len(subop, op_id);
177293db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
177393db446aSBoris Brezillon }
177493db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns;
177593db446aSBoris Brezillon break;
177693db446aSBoris Brezillon
177793db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR:
177893db446aSBoris Brezillon nfc_op->data_instr = instr;
177993db446aSBoris Brezillon nfc_op->data_instr_idx = op_id;
178093db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE);
178193db446aSBoris Brezillon if (nfc->caps->is_nfcv2) {
178293db446aSBoris Brezillon nfc_op->ndcb[0] |=
178393db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
178493db446aSBoris Brezillon NDCB0_LEN_OVRD;
178521a26806SMiquel Raynal len = nand_subop_get_data_len(subop, op_id);
178693db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
178793db446aSBoris Brezillon }
178893db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns;
178993db446aSBoris Brezillon break;
179093db446aSBoris Brezillon
179193db446aSBoris Brezillon case NAND_OP_WAITRDY_INSTR:
179293db446aSBoris Brezillon nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
179393db446aSBoris Brezillon nfc_op->rdy_delay_ns = instr->delay_ns;
179493db446aSBoris Brezillon break;
179593db446aSBoris Brezillon }
179693db446aSBoris Brezillon }
179793db446aSBoris Brezillon }
179893db446aSBoris Brezillon
marvell_nfc_xfer_data_pio(struct nand_chip * chip,const struct nand_subop * subop,struct marvell_nfc_op * nfc_op)179993db446aSBoris Brezillon static int marvell_nfc_xfer_data_pio(struct nand_chip *chip,
180093db446aSBoris Brezillon const struct nand_subop *subop,
180193db446aSBoris Brezillon struct marvell_nfc_op *nfc_op)
180293db446aSBoris Brezillon {
180393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
180493db446aSBoris Brezillon const struct nand_op_instr *instr = nfc_op->data_instr;
180593db446aSBoris Brezillon unsigned int op_id = nfc_op->data_instr_idx;
180693db446aSBoris Brezillon unsigned int len = nand_subop_get_data_len(subop, op_id);
180793db446aSBoris Brezillon unsigned int offset = nand_subop_get_data_start_off(subop, op_id);
180893db446aSBoris Brezillon bool reading = (instr->type == NAND_OP_DATA_IN_INSTR);
180993db446aSBoris Brezillon int ret;
181093db446aSBoris Brezillon
181193db446aSBoris Brezillon if (instr->ctx.data.force_8bit)
181293db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, true);
181393db446aSBoris Brezillon
181493db446aSBoris Brezillon if (reading) {
181593db446aSBoris Brezillon u8 *in = instr->ctx.data.buf.in + offset;
181693db446aSBoris Brezillon
181793db446aSBoris Brezillon ret = marvell_nfc_xfer_data_in_pio(nfc, in, len);
181893db446aSBoris Brezillon } else {
181993db446aSBoris Brezillon const u8 *out = instr->ctx.data.buf.out + offset;
182093db446aSBoris Brezillon
182193db446aSBoris Brezillon ret = marvell_nfc_xfer_data_out_pio(nfc, out, len);
182293db446aSBoris Brezillon }
182393db446aSBoris Brezillon
182493db446aSBoris Brezillon if (instr->ctx.data.force_8bit)
182593db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, false);
182693db446aSBoris Brezillon
182793db446aSBoris Brezillon return ret;
182893db446aSBoris Brezillon }
182993db446aSBoris Brezillon
marvell_nfc_monolithic_access_exec(struct nand_chip * chip,const struct nand_subop * subop)183093db446aSBoris Brezillon static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip,
183193db446aSBoris Brezillon const struct nand_subop *subop)
183293db446aSBoris Brezillon {
183393db446aSBoris Brezillon struct marvell_nfc_op nfc_op;
183493db446aSBoris Brezillon bool reading;
183593db446aSBoris Brezillon int ret;
183693db446aSBoris Brezillon
183793db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op);
183893db446aSBoris Brezillon reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR);
183993db446aSBoris Brezillon
184093db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
184193db446aSBoris Brezillon if (ret)
184293db446aSBoris Brezillon return ret;
184393db446aSBoris Brezillon
184493db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
184593db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
184693db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data");
184793db446aSBoris Brezillon if (ret)
184893db446aSBoris Brezillon return ret;
184993db446aSBoris Brezillon
185093db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns);
185193db446aSBoris Brezillon
185293db446aSBoris Brezillon if (reading) {
185393db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) {
185493db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
185593db446aSBoris Brezillon if (ret)
185693db446aSBoris Brezillon return ret;
185793db446aSBoris Brezillon }
185893db446aSBoris Brezillon
185993db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns);
186093db446aSBoris Brezillon }
186193db446aSBoris Brezillon
186293db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
186393db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip);
186493db446aSBoris Brezillon if (ret)
186593db446aSBoris Brezillon return ret;
186693db446aSBoris Brezillon
186793db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns);
186893db446aSBoris Brezillon
186993db446aSBoris Brezillon if (!reading) {
187093db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) {
187193db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
187293db446aSBoris Brezillon if (ret)
187393db446aSBoris Brezillon return ret;
187493db446aSBoris Brezillon }
187593db446aSBoris Brezillon
187693db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns);
187793db446aSBoris Brezillon }
187893db446aSBoris Brezillon
187993db446aSBoris Brezillon /*
188093db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each
188193db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it
188293db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case.
188393db446aSBoris Brezillon */
188493db446aSBoris Brezillon if (!reading) {
188593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
188693db446aSBoris Brezillon
188793db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
188893db446aSBoris Brezillon nfc->regs + NDCR);
188993db446aSBoris Brezillon }
189093db446aSBoris Brezillon
189193db446aSBoris Brezillon return 0;
189293db446aSBoris Brezillon }
189393db446aSBoris Brezillon
marvell_nfc_naked_access_exec(struct nand_chip * chip,const struct nand_subop * subop)189493db446aSBoris Brezillon static int marvell_nfc_naked_access_exec(struct nand_chip *chip,
189593db446aSBoris Brezillon const struct nand_subop *subop)
189693db446aSBoris Brezillon {
189793db446aSBoris Brezillon struct marvell_nfc_op nfc_op;
189893db446aSBoris Brezillon int ret;
189993db446aSBoris Brezillon
190093db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op);
190193db446aSBoris Brezillon
190293db446aSBoris Brezillon /*
190393db446aSBoris Brezillon * Naked access are different in that they need to be flagged as naked
190493db446aSBoris Brezillon * by the controller. Reset the controller registers fields that inform
190593db446aSBoris Brezillon * on the type and refill them according to the ongoing operation.
190693db446aSBoris Brezillon */
190793db446aSBoris Brezillon nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) |
190893db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MASK));
190993db446aSBoris Brezillon switch (subop->instrs[0].type) {
191093db446aSBoris Brezillon case NAND_OP_CMD_INSTR:
191193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD);
191293db446aSBoris Brezillon break;
191393db446aSBoris Brezillon case NAND_OP_ADDR_INSTR:
191493db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR);
191593db446aSBoris Brezillon break;
191693db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR:
191793db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) |
191893db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
191993db446aSBoris Brezillon break;
192093db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR:
192193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) |
192293db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
192393db446aSBoris Brezillon break;
192493db446aSBoris Brezillon default:
192593db446aSBoris Brezillon /* This should never happen */
192693db446aSBoris Brezillon break;
192793db446aSBoris Brezillon }
192893db446aSBoris Brezillon
192993db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
193093db446aSBoris Brezillon if (ret)
193193db446aSBoris Brezillon return ret;
193293db446aSBoris Brezillon
193393db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
193493db446aSBoris Brezillon
193593db446aSBoris Brezillon if (!nfc_op.data_instr) {
193693db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip);
193793db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns);
193893db446aSBoris Brezillon return ret;
193993db446aSBoris Brezillon }
194093db446aSBoris Brezillon
194193db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
194293db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data");
194393db446aSBoris Brezillon if (ret)
194493db446aSBoris Brezillon return ret;
194593db446aSBoris Brezillon
194693db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
194793db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip);
194893db446aSBoris Brezillon if (ret)
194993db446aSBoris Brezillon return ret;
195093db446aSBoris Brezillon
195193db446aSBoris Brezillon /*
195293db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each
195393db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it
195493db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case.
195593db446aSBoris Brezillon */
195693db446aSBoris Brezillon if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) {
195793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
195893db446aSBoris Brezillon
195993db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
196093db446aSBoris Brezillon nfc->regs + NDCR);
196193db446aSBoris Brezillon }
196293db446aSBoris Brezillon
196393db446aSBoris Brezillon return 0;
196493db446aSBoris Brezillon }
196593db446aSBoris Brezillon
marvell_nfc_naked_waitrdy_exec(struct nand_chip * chip,const struct nand_subop * subop)196693db446aSBoris Brezillon static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip,
196793db446aSBoris Brezillon const struct nand_subop *subop)
196893db446aSBoris Brezillon {
196993db446aSBoris Brezillon struct marvell_nfc_op nfc_op;
197093db446aSBoris Brezillon int ret;
197193db446aSBoris Brezillon
197293db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op);
197393db446aSBoris Brezillon
197493db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
197593db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns);
197693db446aSBoris Brezillon
197793db446aSBoris Brezillon return ret;
197893db446aSBoris Brezillon }
197993db446aSBoris Brezillon
marvell_nfc_read_id_type_exec(struct nand_chip * chip,const struct nand_subop * subop)198093db446aSBoris Brezillon static int marvell_nfc_read_id_type_exec(struct nand_chip *chip,
198193db446aSBoris Brezillon const struct nand_subop *subop)
198293db446aSBoris Brezillon {
198393db446aSBoris Brezillon struct marvell_nfc_op nfc_op;
198493db446aSBoris Brezillon int ret;
198593db446aSBoris Brezillon
198693db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op);
198793db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
198893db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID);
198993db446aSBoris Brezillon
199093db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
199193db446aSBoris Brezillon if (ret)
199293db446aSBoris Brezillon return ret;
199393db446aSBoris Brezillon
199493db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
199593db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
199693db446aSBoris Brezillon "RDDREQ while reading ID");
199793db446aSBoris Brezillon if (ret)
199893db446aSBoris Brezillon return ret;
199993db446aSBoris Brezillon
200093db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns);
200193db446aSBoris Brezillon
200293db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) {
200393db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
200493db446aSBoris Brezillon if (ret)
200593db446aSBoris Brezillon return ret;
200693db446aSBoris Brezillon }
200793db446aSBoris Brezillon
200893db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns);
200993db446aSBoris Brezillon
201093db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
201193db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip);
201293db446aSBoris Brezillon if (ret)
201393db446aSBoris Brezillon return ret;
201493db446aSBoris Brezillon
201593db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns);
201693db446aSBoris Brezillon
201793db446aSBoris Brezillon return 0;
201893db446aSBoris Brezillon }
201993db446aSBoris Brezillon
marvell_nfc_read_status_exec(struct nand_chip * chip,const struct nand_subop * subop)202093db446aSBoris Brezillon static int marvell_nfc_read_status_exec(struct nand_chip *chip,
202193db446aSBoris Brezillon const struct nand_subop *subop)
202293db446aSBoris Brezillon {
202393db446aSBoris Brezillon struct marvell_nfc_op nfc_op;
202493db446aSBoris Brezillon int ret;
202593db446aSBoris Brezillon
202693db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op);
202793db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
202893db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS);
202993db446aSBoris Brezillon
203093db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
203193db446aSBoris Brezillon if (ret)
203293db446aSBoris Brezillon return ret;
203393db446aSBoris Brezillon
203493db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
203593db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
203693db446aSBoris Brezillon "RDDREQ while reading status");
203793db446aSBoris Brezillon if (ret)
203893db446aSBoris Brezillon return ret;
203993db446aSBoris Brezillon
204093db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns);
204193db446aSBoris Brezillon
204293db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) {
204393db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
204493db446aSBoris Brezillon if (ret)
204593db446aSBoris Brezillon return ret;
204693db446aSBoris Brezillon }
204793db446aSBoris Brezillon
204893db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns);
204993db446aSBoris Brezillon
205093db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
205193db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip);
205293db446aSBoris Brezillon if (ret)
205393db446aSBoris Brezillon return ret;
205493db446aSBoris Brezillon
205593db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns);
205693db446aSBoris Brezillon
205793db446aSBoris Brezillon return 0;
205893db446aSBoris Brezillon }
205993db446aSBoris Brezillon
marvell_nfc_reset_cmd_type_exec(struct nand_chip * chip,const struct nand_subop * subop)206093db446aSBoris Brezillon static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip,
206193db446aSBoris Brezillon const struct nand_subop *subop)
206293db446aSBoris Brezillon {
206393db446aSBoris Brezillon struct marvell_nfc_op nfc_op;
206493db446aSBoris Brezillon int ret;
206593db446aSBoris Brezillon
206693db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op);
206793db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET);
206893db446aSBoris Brezillon
206993db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
207093db446aSBoris Brezillon if (ret)
207193db446aSBoris Brezillon return ret;
207293db446aSBoris Brezillon
207393db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
207493db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip);
207593db446aSBoris Brezillon if (ret)
207693db446aSBoris Brezillon return ret;
207793db446aSBoris Brezillon
207893db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns);
207993db446aSBoris Brezillon
208093db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
208193db446aSBoris Brezillon if (ret)
208293db446aSBoris Brezillon return ret;
208393db446aSBoris Brezillon
208493db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns);
208593db446aSBoris Brezillon
208693db446aSBoris Brezillon return 0;
208793db446aSBoris Brezillon }
208893db446aSBoris Brezillon
marvell_nfc_erase_cmd_type_exec(struct nand_chip * chip,const struct nand_subop * subop)208993db446aSBoris Brezillon static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip,
209093db446aSBoris Brezillon const struct nand_subop *subop)
209193db446aSBoris Brezillon {
209293db446aSBoris Brezillon struct marvell_nfc_op nfc_op;
209393db446aSBoris Brezillon int ret;
209493db446aSBoris Brezillon
209593db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op);
209693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE);
209793db446aSBoris Brezillon
209893db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip);
209993db446aSBoris Brezillon if (ret)
210093db446aSBoris Brezillon return ret;
210193db446aSBoris Brezillon
210293db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op);
210393db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip);
210493db446aSBoris Brezillon if (ret)
210593db446aSBoris Brezillon return ret;
210693db446aSBoris Brezillon
210793db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns);
210893db446aSBoris Brezillon
210993db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
211093db446aSBoris Brezillon if (ret)
211193db446aSBoris Brezillon return ret;
211293db446aSBoris Brezillon
211393db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns);
211493db446aSBoris Brezillon
211593db446aSBoris Brezillon return 0;
211693db446aSBoris Brezillon }
211793db446aSBoris Brezillon
211893db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER(
211993db446aSBoris Brezillon /* Monolithic reads/writes */
212093db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
212193db446aSBoris Brezillon marvell_nfc_monolithic_access_exec,
212293db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false),
212393db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2),
212493db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true),
212593db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
212693db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
212793db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
212893db446aSBoris Brezillon marvell_nfc_monolithic_access_exec,
212993db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false),
213093db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2),
213193db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE),
213293db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true),
213393db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
213493db446aSBoris Brezillon /* Naked commands */
213593db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
213693db446aSBoris Brezillon marvell_nfc_naked_access_exec,
213793db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false)),
213893db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
213993db446aSBoris Brezillon marvell_nfc_naked_access_exec,
214093db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)),
214193db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
214293db446aSBoris Brezillon marvell_nfc_naked_access_exec,
214393db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
214493db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
214593db446aSBoris Brezillon marvell_nfc_naked_access_exec,
214693db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)),
214793db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
214893db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec,
214993db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
215093db446aSBoris Brezillon );
215193db446aSBoris Brezillon
215293db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER(
215393db446aSBoris Brezillon /* Naked commands not supported, use a function for each pattern */
215493db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
215593db446aSBoris Brezillon marvell_nfc_read_id_type_exec,
215693db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false),
215793db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
215893db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)),
215993db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
216093db446aSBoris Brezillon marvell_nfc_erase_cmd_type_exec,
216193db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false),
216293db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
216393db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false),
216493db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
216593db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
216693db446aSBoris Brezillon marvell_nfc_read_status_exec,
216793db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false),
216893db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)),
216993db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
217093db446aSBoris Brezillon marvell_nfc_reset_cmd_type_exec,
217193db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false),
217293db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
217393db446aSBoris Brezillon NAND_OP_PARSER_PATTERN(
217493db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec,
217593db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
217693db446aSBoris Brezillon );
217793db446aSBoris Brezillon
marvell_nfc_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)217893db446aSBoris Brezillon static int marvell_nfc_exec_op(struct nand_chip *chip,
217993db446aSBoris Brezillon const struct nand_operation *op,
218093db446aSBoris Brezillon bool check_only)
218193db446aSBoris Brezillon {
218293db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
218393db446aSBoris Brezillon
2184ce446b4bSBoris Brezillon if (!check_only)
2185b2525141SBoris Brezillon marvell_nfc_select_target(chip, op->cs);
2186b2525141SBoris Brezillon
218793db446aSBoris Brezillon if (nfc->caps->is_nfcv2)
218893db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser,
218993db446aSBoris Brezillon op, check_only);
219093db446aSBoris Brezillon else
219193db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser,
219293db446aSBoris Brezillon op, check_only);
219393db446aSBoris Brezillon }
219493db446aSBoris Brezillon
219593db446aSBoris Brezillon /*
219693db446aSBoris Brezillon * Layouts were broken in old pxa3xx_nand driver, these are supposed to be
219793db446aSBoris Brezillon * usable.
219893db446aSBoris Brezillon */
marvell_nand_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)219993db446aSBoris Brezillon static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
220093db446aSBoris Brezillon struct mtd_oob_region *oobregion)
220193db446aSBoris Brezillon {
220293db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd);
220393db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
220493db446aSBoris Brezillon
220593db446aSBoris Brezillon if (section)
220693db446aSBoris Brezillon return -ERANGE;
220793db446aSBoris Brezillon
220893db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) +
220993db446aSBoris Brezillon lt->last_ecc_bytes;
221093db446aSBoris Brezillon oobregion->offset = mtd->oobsize - oobregion->length;
221193db446aSBoris Brezillon
221293db446aSBoris Brezillon return 0;
221393db446aSBoris Brezillon }
221493db446aSBoris Brezillon
marvell_nand_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)221593db446aSBoris Brezillon static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section,
221693db446aSBoris Brezillon struct mtd_oob_region *oobregion)
221793db446aSBoris Brezillon {
221893db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd);
221993db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
222093db446aSBoris Brezillon
222193db446aSBoris Brezillon if (section)
222293db446aSBoris Brezillon return -ERANGE;
222393db446aSBoris Brezillon
222493db446aSBoris Brezillon /*
222593db446aSBoris Brezillon * Bootrom looks in bytes 0 & 5 for bad blocks for the
222693db446aSBoris Brezillon * 4KB page / 4bit BCH combination.
222793db446aSBoris Brezillon */
222893db446aSBoris Brezillon if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K)
222993db446aSBoris Brezillon oobregion->offset = 6;
223093db446aSBoris Brezillon else
223193db446aSBoris Brezillon oobregion->offset = 2;
223293db446aSBoris Brezillon
223393db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) +
223493db446aSBoris Brezillon lt->last_spare_bytes - oobregion->offset;
223593db446aSBoris Brezillon
223693db446aSBoris Brezillon return 0;
223793db446aSBoris Brezillon }
223893db446aSBoris Brezillon
223993db446aSBoris Brezillon static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = {
224093db446aSBoris Brezillon .ecc = marvell_nand_ooblayout_ecc,
224193db446aSBoris Brezillon .free = marvell_nand_ooblayout_free,
224293db446aSBoris Brezillon };
224393db446aSBoris Brezillon
marvell_nand_hw_ecc_controller_init(struct mtd_info * mtd,struct nand_ecc_ctrl * ecc)224482c6c04eSMiquel Raynal static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd,
224593db446aSBoris Brezillon struct nand_ecc_ctrl *ecc)
224693db446aSBoris Brezillon {
224793db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd);
224893db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
224993db446aSBoris Brezillon const struct marvell_hw_ecc_layout *l;
225093db446aSBoris Brezillon int i;
225193db446aSBoris Brezillon
225293db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 &&
225393db446aSBoris Brezillon (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) {
225493db446aSBoris Brezillon dev_err(nfc->dev,
225593db446aSBoris Brezillon "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n",
225693db446aSBoris Brezillon mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize);
225793db446aSBoris Brezillon return -ENOTSUPP;
225893db446aSBoris Brezillon }
225993db446aSBoris Brezillon
226093db446aSBoris Brezillon to_marvell_nand(chip)->layout = NULL;
226193db446aSBoris Brezillon for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) {
226293db446aSBoris Brezillon l = &marvell_nfc_layouts[i];
226393db446aSBoris Brezillon if (mtd->writesize == l->writesize &&
226493db446aSBoris Brezillon ecc->size == l->chunk && ecc->strength == l->strength) {
226593db446aSBoris Brezillon to_marvell_nand(chip)->layout = l;
226693db446aSBoris Brezillon break;
226793db446aSBoris Brezillon }
226893db446aSBoris Brezillon }
226993db446aSBoris Brezillon
227093db446aSBoris Brezillon if (!to_marvell_nand(chip)->layout ||
227193db446aSBoris Brezillon (!nfc->caps->is_nfcv2 && ecc->strength > 1)) {
227293db446aSBoris Brezillon dev_err(nfc->dev,
227393db446aSBoris Brezillon "ECC strength %d at page size %d is not supported\n",
227493db446aSBoris Brezillon ecc->strength, mtd->writesize);
227593db446aSBoris Brezillon return -ENOTSUPP;
227693db446aSBoris Brezillon }
227793db446aSBoris Brezillon
22787fd130f7SMiquel Raynal /* Special care for the layout 2k/8-bit/512B */
22797fd130f7SMiquel Raynal if (l->writesize == 2048 && l->strength == 8) {
22807fd130f7SMiquel Raynal if (mtd->oobsize < 128) {
22817fd130f7SMiquel Raynal dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n");
22827fd130f7SMiquel Raynal return -ENOTSUPP;
22837fd130f7SMiquel Raynal } else {
22847fd130f7SMiquel Raynal chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
22857fd130f7SMiquel Raynal }
22867fd130f7SMiquel Raynal }
22877fd130f7SMiquel Raynal
228893db446aSBoris Brezillon mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops);
228993db446aSBoris Brezillon ecc->steps = l->nchunks;
229093db446aSBoris Brezillon ecc->size = l->data_bytes;
229193db446aSBoris Brezillon
229293db446aSBoris Brezillon if (ecc->strength == 1) {
2293e0a564aeSMiquel Raynal chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
229493db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
229593db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
229693db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
229793db446aSBoris Brezillon ecc->read_oob = ecc->read_oob_raw;
229893db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw;
229993db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page;
230093db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
230193db446aSBoris Brezillon ecc->write_oob = ecc->write_oob_raw;
230293db446aSBoris Brezillon } else {
2303e0a564aeSMiquel Raynal chip->ecc.algo = NAND_ECC_ALGO_BCH;
230493db446aSBoris Brezillon ecc->strength = 16;
230593db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
230693db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;
230793db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw;
230893db446aSBoris Brezillon ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob;
230993db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw;
231093db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_bch_write_page;
231193db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw;
231293db446aSBoris Brezillon ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob;
231393db446aSBoris Brezillon }
231493db446aSBoris Brezillon
231593db446aSBoris Brezillon return 0;
231693db446aSBoris Brezillon }
231793db446aSBoris Brezillon
marvell_nand_ecc_init(struct mtd_info * mtd,struct nand_ecc_ctrl * ecc)231893db446aSBoris Brezillon static int marvell_nand_ecc_init(struct mtd_info *mtd,
231993db446aSBoris Brezillon struct nand_ecc_ctrl *ecc)
232093db446aSBoris Brezillon {
232193db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd);
232253576c7bSMiquel Raynal const struct nand_ecc_props *requirements =
232353576c7bSMiquel Raynal nanddev_get_ecc_requirements(&chip->base);
232493db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
232593db446aSBoris Brezillon int ret;
232693db446aSBoris Brezillon
2327bace41f8SMiquel Raynal if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2328bace41f8SMiquel Raynal (!ecc->size || !ecc->strength)) {
232953576c7bSMiquel Raynal if (requirements->step_size && requirements->strength) {
233053576c7bSMiquel Raynal ecc->size = requirements->step_size;
233153576c7bSMiquel Raynal ecc->strength = requirements->strength;
233293db446aSBoris Brezillon } else {
233393db446aSBoris Brezillon dev_info(nfc->dev,
233493db446aSBoris Brezillon "No minimum ECC strength, using 1b/512B\n");
233593db446aSBoris Brezillon ecc->size = 512;
233693db446aSBoris Brezillon ecc->strength = 1;
233793db446aSBoris Brezillon }
233893db446aSBoris Brezillon }
233993db446aSBoris Brezillon
2340bace41f8SMiquel Raynal switch (ecc->engine_type) {
2341bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_ON_HOST:
234282c6c04eSMiquel Raynal ret = marvell_nand_hw_ecc_controller_init(mtd, ecc);
234393db446aSBoris Brezillon if (ret)
234493db446aSBoris Brezillon return ret;
234593db446aSBoris Brezillon break;
2346bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_NONE:
2347bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_SOFT:
2348bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_ON_DIE:
234993db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 &&
235093db446aSBoris Brezillon mtd->writesize != SZ_2K) {
235193db446aSBoris Brezillon dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n",
235293db446aSBoris Brezillon mtd->writesize);
235393db446aSBoris Brezillon return -EINVAL;
235493db446aSBoris Brezillon }
235593db446aSBoris Brezillon break;
235693db446aSBoris Brezillon default:
235793db446aSBoris Brezillon return -EINVAL;
235893db446aSBoris Brezillon }
235993db446aSBoris Brezillon
236093db446aSBoris Brezillon return 0;
236193db446aSBoris Brezillon }
236293db446aSBoris Brezillon
236393db446aSBoris Brezillon static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
236493db446aSBoris Brezillon static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
236593db446aSBoris Brezillon
236693db446aSBoris Brezillon static struct nand_bbt_descr bbt_main_descr = {
236793db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
236893db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION,
236993db446aSBoris Brezillon .offs = 8,
237093db446aSBoris Brezillon .len = 6,
237193db446aSBoris Brezillon .veroffs = 14,
237293db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */
237393db446aSBoris Brezillon .pattern = bbt_pattern
237493db446aSBoris Brezillon };
237593db446aSBoris Brezillon
237693db446aSBoris Brezillon static struct nand_bbt_descr bbt_mirror_descr = {
237793db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
237893db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION,
237993db446aSBoris Brezillon .offs = 8,
238093db446aSBoris Brezillon .len = 6,
238193db446aSBoris Brezillon .veroffs = 14,
238293db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */
238393db446aSBoris Brezillon .pattern = bbt_mirror_pattern
238493db446aSBoris Brezillon };
238593db446aSBoris Brezillon
marvell_nfc_setup_interface(struct nand_chip * chip,int chipnr,const struct nand_interface_config * conf)23864c46667bSMiquel Raynal static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,
23874c46667bSMiquel Raynal const struct nand_interface_config *conf)
238893db446aSBoris Brezillon {
238993db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
239093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
23916b6de654SBoris Brezillon unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2;
239293db446aSBoris Brezillon const struct nand_sdr_timings *sdr;
239393db446aSBoris Brezillon struct marvell_nfc_timings nfc_tmg;
239493db446aSBoris Brezillon int read_delay;
239593db446aSBoris Brezillon
239693db446aSBoris Brezillon sdr = nand_get_sdr_timings(conf);
239793db446aSBoris Brezillon if (IS_ERR(sdr))
239893db446aSBoris Brezillon return PTR_ERR(sdr);
239993db446aSBoris Brezillon
240072b9a3fcSChris Packham if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode)
240172b9a3fcSChris Packham return -EOPNOTSUPP;
240272b9a3fcSChris Packham
240393db446aSBoris Brezillon /*
240493db446aSBoris Brezillon * SDR timings are given in pico-seconds while NFC timings must be
240593db446aSBoris Brezillon * expressed in NAND controller clock cycles, which is half of the
240693db446aSBoris Brezillon * frequency of the accessible ECC clock retrieved by clk_get_rate().
240793db446aSBoris Brezillon * This is not written anywhere in the datasheet but was observed
240893db446aSBoris Brezillon * with an oscilloscope.
240993db446aSBoris Brezillon *
241093db446aSBoris Brezillon * NFC datasheet gives equations from which thoses calculations
241193db446aSBoris Brezillon * are derived, they tend to be slightly more restrictives than the
241293db446aSBoris Brezillon * given core timings and may improve the overall speed.
241393db446aSBoris Brezillon */
241493db446aSBoris Brezillon nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1;
241593db446aSBoris Brezillon nfc_tmg.tRH = nfc_tmg.tRP;
241693db446aSBoris Brezillon nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1;
241793db446aSBoris Brezillon nfc_tmg.tWH = nfc_tmg.tWP;
241893db446aSBoris Brezillon nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns);
241993db446aSBoris Brezillon nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1;
242093db446aSBoris Brezillon nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns);
242193db446aSBoris Brezillon /*
242293db446aSBoris Brezillon * Read delay is the time of propagation from SoC pins to NFC internal
242393db446aSBoris Brezillon * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In
242493db446aSBoris Brezillon * EDO mode, an additional delay of tRH must be taken into account so
242593db446aSBoris Brezillon * the data is sampled on the falling edge instead of the rising edge.
242693db446aSBoris Brezillon */
242793db446aSBoris Brezillon read_delay = sdr->tRC_min >= 30000 ?
242893db446aSBoris Brezillon MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH;
242993db446aSBoris Brezillon
243093db446aSBoris Brezillon nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns);
243193db446aSBoris Brezillon /*
243293db446aSBoris Brezillon * tWHR and tRHW are supposed to be read to write delays (and vice
243393db446aSBoris Brezillon * versa) but in some cases, ie. when doing a change column, they must
243493db446aSBoris Brezillon * be greater than that to be sure tCCS delay is respected.
243593db446aSBoris Brezillon */
243693db446aSBoris Brezillon nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
2437e64ab8e8SZheng Yongjun period_ns) - 2;
243893db446aSBoris Brezillon nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
243993db446aSBoris Brezillon period_ns);
244093db446aSBoris Brezillon
244193db446aSBoris Brezillon /*
244293db446aSBoris Brezillon * NFCv2: Use WAIT_MODE (wait for RB line), do not rely only on delays.
244393db446aSBoris Brezillon * NFCv1: No WAIT_MODE, tR must be maximal.
244493db446aSBoris Brezillon */
244593db446aSBoris Brezillon if (nfc->caps->is_nfcv2) {
244693db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns);
244793db446aSBoris Brezillon } else {
244893db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max,
244993db446aSBoris Brezillon period_ns);
245093db446aSBoris Brezillon if (nfc_tmg.tR + 3 > nfc_tmg.tCH)
245193db446aSBoris Brezillon nfc_tmg.tR = nfc_tmg.tCH - 3;
245293db446aSBoris Brezillon else
245393db446aSBoris Brezillon nfc_tmg.tR = 0;
245493db446aSBoris Brezillon }
245593db446aSBoris Brezillon
245693db446aSBoris Brezillon if (chipnr < 0)
245793db446aSBoris Brezillon return 0;
245893db446aSBoris Brezillon
245993db446aSBoris Brezillon marvell_nand->ndtr0 =
246093db446aSBoris Brezillon NDTR0_TRP(nfc_tmg.tRP) |
246193db446aSBoris Brezillon NDTR0_TRH(nfc_tmg.tRH) |
246293db446aSBoris Brezillon NDTR0_ETRP(nfc_tmg.tRP) |
246393db446aSBoris Brezillon NDTR0_TWP(nfc_tmg.tWP) |
246493db446aSBoris Brezillon NDTR0_TWH(nfc_tmg.tWH) |
246593db446aSBoris Brezillon NDTR0_TCS(nfc_tmg.tCS) |
246693db446aSBoris Brezillon NDTR0_TCH(nfc_tmg.tCH);
246793db446aSBoris Brezillon
246893db446aSBoris Brezillon marvell_nand->ndtr1 =
246993db446aSBoris Brezillon NDTR1_TAR(nfc_tmg.tAR) |
247093db446aSBoris Brezillon NDTR1_TWHR(nfc_tmg.tWHR) |
247193db446aSBoris Brezillon NDTR1_TR(nfc_tmg.tR);
247293db446aSBoris Brezillon
247393db446aSBoris Brezillon if (nfc->caps->is_nfcv2) {
247493db446aSBoris Brezillon marvell_nand->ndtr0 |=
247593db446aSBoris Brezillon NDTR0_RD_CNT_DEL(read_delay) |
247693db446aSBoris Brezillon NDTR0_SELCNTR |
247793db446aSBoris Brezillon NDTR0_TADL(nfc_tmg.tADL);
247893db446aSBoris Brezillon
247993db446aSBoris Brezillon marvell_nand->ndtr1 |=
248093db446aSBoris Brezillon NDTR1_TRHW(nfc_tmg.tRHW) |
248193db446aSBoris Brezillon NDTR1_WAIT_MODE;
248293db446aSBoris Brezillon }
248393db446aSBoris Brezillon
24848a6f4d34SChris Packham /*
24858a6f4d34SChris Packham * Reset nfc->selected_chip so the next command will cause the timing
24868a6f4d34SChris Packham * registers to be updated in marvell_nfc_select_target().
24878a6f4d34SChris Packham */
24888a6f4d34SChris Packham nfc->selected_chip = NULL;
24898a6f4d34SChris Packham
249093db446aSBoris Brezillon return 0;
249193db446aSBoris Brezillon }
249293db446aSBoris Brezillon
marvell_nand_attach_chip(struct nand_chip * chip)24938831e48bSMiquel Raynal static int marvell_nand_attach_chip(struct nand_chip *chip)
24948831e48bSMiquel Raynal {
24958831e48bSMiquel Raynal struct mtd_info *mtd = nand_to_mtd(chip);
24968831e48bSMiquel Raynal struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
24978831e48bSMiquel Raynal struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
24988831e48bSMiquel Raynal struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev);
24998831e48bSMiquel Raynal int ret;
25008831e48bSMiquel Raynal
25018831e48bSMiquel Raynal if (pdata && pdata->flash_bbt)
25028831e48bSMiquel Raynal chip->bbt_options |= NAND_BBT_USE_FLASH;
25038831e48bSMiquel Raynal
25048831e48bSMiquel Raynal if (chip->bbt_options & NAND_BBT_USE_FLASH) {
25058831e48bSMiquel Raynal /*
25068831e48bSMiquel Raynal * We'll use a bad block table stored in-flash and don't
25078831e48bSMiquel Raynal * allow writing the bad block marker to the flash.
25088831e48bSMiquel Raynal */
25098831e48bSMiquel Raynal chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
25108831e48bSMiquel Raynal chip->bbt_td = &bbt_main_descr;
25118831e48bSMiquel Raynal chip->bbt_md = &bbt_mirror_descr;
25128831e48bSMiquel Raynal }
25138831e48bSMiquel Raynal
25148831e48bSMiquel Raynal /* Save the chip-specific fields of NDCR */
25158831e48bSMiquel Raynal marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize);
25168831e48bSMiquel Raynal if (chip->options & NAND_BUSWIDTH_16)
25178831e48bSMiquel Raynal marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
25188831e48bSMiquel Raynal
25198831e48bSMiquel Raynal /*
25208831e48bSMiquel Raynal * On small page NANDs, only one cycle is needed to pass the
25218831e48bSMiquel Raynal * column address.
25228831e48bSMiquel Raynal */
25238831e48bSMiquel Raynal if (mtd->writesize <= 512) {
25248831e48bSMiquel Raynal marvell_nand->addr_cyc = 1;
25258831e48bSMiquel Raynal } else {
25268831e48bSMiquel Raynal marvell_nand->addr_cyc = 2;
25278831e48bSMiquel Raynal marvell_nand->ndcr |= NDCR_RA_START;
25288831e48bSMiquel Raynal }
25298831e48bSMiquel Raynal
25308831e48bSMiquel Raynal /*
25318831e48bSMiquel Raynal * Now add the number of cycles needed to pass the row
25328831e48bSMiquel Raynal * address.
25338831e48bSMiquel Raynal *
25348831e48bSMiquel Raynal * Addressing a chip using CS 2 or 3 should also need the third row
25358831e48bSMiquel Raynal * cycle but due to inconsistance in the documentation and lack of
25368831e48bSMiquel Raynal * hardware to test this situation, this case is not supported.
25378831e48bSMiquel Raynal */
25388831e48bSMiquel Raynal if (chip->options & NAND_ROW_ADDR_3)
25398831e48bSMiquel Raynal marvell_nand->addr_cyc += 3;
25408831e48bSMiquel Raynal else
25418831e48bSMiquel Raynal marvell_nand->addr_cyc += 2;
25428831e48bSMiquel Raynal
25438831e48bSMiquel Raynal if (pdata) {
25448831e48bSMiquel Raynal chip->ecc.size = pdata->ecc_step_size;
25458831e48bSMiquel Raynal chip->ecc.strength = pdata->ecc_strength;
25468831e48bSMiquel Raynal }
25478831e48bSMiquel Raynal
25488831e48bSMiquel Raynal ret = marvell_nand_ecc_init(mtd, &chip->ecc);
25498831e48bSMiquel Raynal if (ret) {
25508831e48bSMiquel Raynal dev_err(nfc->dev, "ECC init failed: %d\n", ret);
25518831e48bSMiquel Raynal return ret;
25528831e48bSMiquel Raynal }
25538831e48bSMiquel Raynal
2554bace41f8SMiquel Raynal if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
25558831e48bSMiquel Raynal /*
25568831e48bSMiquel Raynal * Subpage write not available with hardware ECC, prohibit also
25578831e48bSMiquel Raynal * subpage read as in userspace subpage access would still be
25588831e48bSMiquel Raynal * allowed and subpage write, if used, would lead to numerous
25598831e48bSMiquel Raynal * uncorrectable ECC errors.
25608831e48bSMiquel Raynal */
25618831e48bSMiquel Raynal chip->options |= NAND_NO_SUBPAGE_WRITE;
25628831e48bSMiquel Raynal }
25638831e48bSMiquel Raynal
25648831e48bSMiquel Raynal if (pdata || nfc->caps->legacy_of_bindings) {
25658831e48bSMiquel Raynal /*
25668831e48bSMiquel Raynal * We keep the MTD name unchanged to avoid breaking platforms
25678831e48bSMiquel Raynal * where the MTD cmdline parser is used and the bootloader
25688831e48bSMiquel Raynal * has not been updated to use the new naming scheme.
25698831e48bSMiquel Raynal */
25708831e48bSMiquel Raynal mtd->name = "pxa3xx_nand-0";
25718831e48bSMiquel Raynal } else if (!mtd->name) {
25728831e48bSMiquel Raynal /*
25738831e48bSMiquel Raynal * If the new bindings are used and the bootloader has not been
25748831e48bSMiquel Raynal * updated to pass a new mtdparts parameter on the cmdline, you
25758831e48bSMiquel Raynal * should define the following property in your NAND node, ie:
25768831e48bSMiquel Raynal *
25778831e48bSMiquel Raynal * label = "main-storage";
25788831e48bSMiquel Raynal *
25798831e48bSMiquel Raynal * This way, mtd->name will be set by the core when
25808831e48bSMiquel Raynal * nand_set_flash_node() is called.
25818831e48bSMiquel Raynal */
25828831e48bSMiquel Raynal mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
25838831e48bSMiquel Raynal "%s:nand.%d", dev_name(nfc->dev),
25848831e48bSMiquel Raynal marvell_nand->sels[0].cs);
25858831e48bSMiquel Raynal if (!mtd->name) {
25868831e48bSMiquel Raynal dev_err(nfc->dev, "Failed to allocate mtd->name\n");
25878831e48bSMiquel Raynal return -ENOMEM;
25888831e48bSMiquel Raynal }
25898831e48bSMiquel Raynal }
25908831e48bSMiquel Raynal
25918831e48bSMiquel Raynal return 0;
25928831e48bSMiquel Raynal }
25938831e48bSMiquel Raynal
25948831e48bSMiquel Raynal static const struct nand_controller_ops marvell_nand_controller_ops = {
25958831e48bSMiquel Raynal .attach_chip = marvell_nand_attach_chip,
2596f2abfeb2SBoris Brezillon .exec_op = marvell_nfc_exec_op,
25974c46667bSMiquel Raynal .setup_interface = marvell_nfc_setup_interface,
25988831e48bSMiquel Raynal };
25998831e48bSMiquel Raynal
marvell_nand_chip_init(struct device * dev,struct marvell_nfc * nfc,struct device_node * np)260093db446aSBoris Brezillon static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
260193db446aSBoris Brezillon struct device_node *np)
260293db446aSBoris Brezillon {
260393db446aSBoris Brezillon struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev);
260493db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand;
260593db446aSBoris Brezillon struct mtd_info *mtd;
260693db446aSBoris Brezillon struct nand_chip *chip;
260793db446aSBoris Brezillon int nsels, ret, i;
260893db446aSBoris Brezillon u32 cs, rb;
260993db446aSBoris Brezillon
261093db446aSBoris Brezillon /*
261193db446aSBoris Brezillon * The legacy "num-cs" property indicates the number of CS on the only
261293db446aSBoris Brezillon * chip connected to the controller (legacy bindings does not support
2613f6997becSMiquel Raynal * more than one chip). The CS and RB pins are always the #0.
261493db446aSBoris Brezillon *
261593db446aSBoris Brezillon * When not using legacy bindings, a couple of "reg" and "nand-rb"
261693db446aSBoris Brezillon * properties must be filled. For each chip, expressed as a subnode,
261793db446aSBoris Brezillon * "reg" points to the CS lines and "nand-rb" to the RB line.
261893db446aSBoris Brezillon */
2619f6997becSMiquel Raynal if (pdata || nfc->caps->legacy_of_bindings) {
262093db446aSBoris Brezillon nsels = 1;
2621f6997becSMiquel Raynal } else {
2622f6997becSMiquel Raynal nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
2623f6997becSMiquel Raynal if (nsels <= 0) {
2624f6997becSMiquel Raynal dev_err(dev, "missing/invalid reg property\n");
262593db446aSBoris Brezillon return -EINVAL;
262693db446aSBoris Brezillon }
262793db446aSBoris Brezillon }
262893db446aSBoris Brezillon
262993db446aSBoris Brezillon /* Alloc the nand chip structure */
26307b301965SGustavo A. R. Silva marvell_nand = devm_kzalloc(dev,
26317b301965SGustavo A. R. Silva struct_size(marvell_nand, sels, nsels),
263293db446aSBoris Brezillon GFP_KERNEL);
263393db446aSBoris Brezillon if (!marvell_nand) {
263493db446aSBoris Brezillon dev_err(dev, "could not allocate chip structure\n");
263593db446aSBoris Brezillon return -ENOMEM;
263693db446aSBoris Brezillon }
263793db446aSBoris Brezillon
263893db446aSBoris Brezillon marvell_nand->nsels = nsels;
263993db446aSBoris Brezillon marvell_nand->selected_die = -1;
264093db446aSBoris Brezillon
264193db446aSBoris Brezillon for (i = 0; i < nsels; i++) {
264293db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) {
264393db446aSBoris Brezillon /*
264493db446aSBoris Brezillon * Legacy bindings use the CS lines in natural
264593db446aSBoris Brezillon * order (0, 1, ...)
264693db446aSBoris Brezillon */
264793db446aSBoris Brezillon cs = i;
264893db446aSBoris Brezillon } else {
264993db446aSBoris Brezillon /* Retrieve CS id */
265093db446aSBoris Brezillon ret = of_property_read_u32_index(np, "reg", i, &cs);
265193db446aSBoris Brezillon if (ret) {
265293db446aSBoris Brezillon dev_err(dev, "could not retrieve reg property: %d\n",
265393db446aSBoris Brezillon ret);
265493db446aSBoris Brezillon return ret;
265593db446aSBoris Brezillon }
265693db446aSBoris Brezillon }
265793db446aSBoris Brezillon
265893db446aSBoris Brezillon if (cs >= nfc->caps->max_cs_nb) {
265993db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max CS = %d)\n",
266093db446aSBoris Brezillon cs, nfc->caps->max_cs_nb);
266193db446aSBoris Brezillon return -EINVAL;
266293db446aSBoris Brezillon }
266393db446aSBoris Brezillon
266493db446aSBoris Brezillon if (test_and_set_bit(cs, &nfc->assigned_cs)) {
266593db446aSBoris Brezillon dev_err(dev, "CS %d already assigned\n", cs);
266693db446aSBoris Brezillon return -EINVAL;
266793db446aSBoris Brezillon }
266893db446aSBoris Brezillon
266993db446aSBoris Brezillon /*
267093db446aSBoris Brezillon * The cs variable represents the chip select id, which must be
267193db446aSBoris Brezillon * converted in bit fields for NDCB0 and NDCB2 to select the
267293db446aSBoris Brezillon * right chip. Unfortunately, due to a lack of information on
267393db446aSBoris Brezillon * the subject and incoherent documentation, the user should not
267493db446aSBoris Brezillon * use CS1 and CS3 at all as asserting them is not supported in
267593db446aSBoris Brezillon * a reliable way (due to multiplexing inside ADDR5 field).
267693db446aSBoris Brezillon */
267793db446aSBoris Brezillon marvell_nand->sels[i].cs = cs;
267893db446aSBoris Brezillon switch (cs) {
267993db446aSBoris Brezillon case 0:
268093db446aSBoris Brezillon case 2:
268193db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = 0;
268293db446aSBoris Brezillon break;
268393db446aSBoris Brezillon case 1:
268493db446aSBoris Brezillon case 3:
268593db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL;
268693db446aSBoris Brezillon break;
268793db446aSBoris Brezillon default:
268893db446aSBoris Brezillon return -EINVAL;
268993db446aSBoris Brezillon }
269093db446aSBoris Brezillon
269193db446aSBoris Brezillon /* Retrieve RB id */
269293db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) {
269393db446aSBoris Brezillon /* Legacy bindings always use RB #0 */
269493db446aSBoris Brezillon rb = 0;
269593db446aSBoris Brezillon } else {
269693db446aSBoris Brezillon ret = of_property_read_u32_index(np, "nand-rb", i,
269793db446aSBoris Brezillon &rb);
269893db446aSBoris Brezillon if (ret) {
269993db446aSBoris Brezillon dev_err(dev,
270093db446aSBoris Brezillon "could not retrieve RB property: %d\n",
270193db446aSBoris Brezillon ret);
270293db446aSBoris Brezillon return ret;
270393db446aSBoris Brezillon }
270493db446aSBoris Brezillon }
270593db446aSBoris Brezillon
270693db446aSBoris Brezillon if (rb >= nfc->caps->max_rb_nb) {
270793db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max RB = %d)\n",
270893db446aSBoris Brezillon rb, nfc->caps->max_rb_nb);
270993db446aSBoris Brezillon return -EINVAL;
271093db446aSBoris Brezillon }
271193db446aSBoris Brezillon
271293db446aSBoris Brezillon marvell_nand->sels[i].rb = rb;
271393db446aSBoris Brezillon }
271493db446aSBoris Brezillon
271593db446aSBoris Brezillon chip = &marvell_nand->chip;
271693db446aSBoris Brezillon chip->controller = &nfc->controller;
271793db446aSBoris Brezillon nand_set_flash_node(chip, np);
271893db446aSBoris Brezillon
2719ce107713STony O'Brien if (of_property_read_bool(np, "marvell,nand-keep-config"))
27207a08dbaeSBoris Brezillon chip->options |= NAND_KEEP_TIMINGS;
272193db446aSBoris Brezillon
272293db446aSBoris Brezillon mtd = nand_to_mtd(chip);
272393db446aSBoris Brezillon mtd->dev.parent = dev;
272493db446aSBoris Brezillon
272593db446aSBoris Brezillon /*
272693db446aSBoris Brezillon * Save a reference value for timing registers before
27274c46667bSMiquel Raynal * ->setup_interface() is called.
272893db446aSBoris Brezillon */
272993db446aSBoris Brezillon marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0);
273093db446aSBoris Brezillon marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1);
273193db446aSBoris Brezillon
273293db446aSBoris Brezillon chip->options |= NAND_BUSWIDTH_AUTO;
27338831e48bSMiquel Raynal
273400ad378fSBoris Brezillon ret = nand_scan(chip, marvell_nand->nsels);
273593db446aSBoris Brezillon if (ret) {
27368831e48bSMiquel Raynal dev_err(dev, "could not scan the nand chip\n");
273793db446aSBoris Brezillon return ret;
273893db446aSBoris Brezillon }
273993db446aSBoris Brezillon
274093db446aSBoris Brezillon if (pdata)
274193db446aSBoris Brezillon /* Legacy bindings support only one chip */
27423383fb35SBoris Brezillon ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
274393db446aSBoris Brezillon else
274493db446aSBoris Brezillon ret = mtd_device_register(mtd, NULL, 0);
274593db446aSBoris Brezillon if (ret) {
274693db446aSBoris Brezillon dev_err(dev, "failed to register mtd device: %d\n", ret);
27477a0c18fbSMiquel Raynal nand_cleanup(chip);
274893db446aSBoris Brezillon return ret;
274993db446aSBoris Brezillon }
275093db446aSBoris Brezillon
275193db446aSBoris Brezillon list_add_tail(&marvell_nand->node, &nfc->chips);
275293db446aSBoris Brezillon
275393db446aSBoris Brezillon return 0;
275493db446aSBoris Brezillon }
275593db446aSBoris Brezillon
marvell_nand_chips_cleanup(struct marvell_nfc * nfc)2756c525b7afSMiquel Raynal static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc)
2757c525b7afSMiquel Raynal {
2758c525b7afSMiquel Raynal struct marvell_nand_chip *entry, *temp;
27595ecbba61SMiquel Raynal struct nand_chip *chip;
27605ecbba61SMiquel Raynal int ret;
2761c525b7afSMiquel Raynal
2762c525b7afSMiquel Raynal list_for_each_entry_safe(entry, temp, &nfc->chips, node) {
27635ecbba61SMiquel Raynal chip = &entry->chip;
27645ecbba61SMiquel Raynal ret = mtd_device_unregister(nand_to_mtd(chip));
27655ecbba61SMiquel Raynal WARN_ON(ret);
27665ecbba61SMiquel Raynal nand_cleanup(chip);
2767c525b7afSMiquel Raynal list_del(&entry->node);
2768c525b7afSMiquel Raynal }
2769c525b7afSMiquel Raynal }
2770c525b7afSMiquel Raynal
marvell_nand_chips_init(struct device * dev,struct marvell_nfc * nfc)277193db446aSBoris Brezillon static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc)
277293db446aSBoris Brezillon {
277393db446aSBoris Brezillon struct device_node *np = dev->of_node;
277493db446aSBoris Brezillon struct device_node *nand_np;
277593db446aSBoris Brezillon int max_cs = nfc->caps->max_cs_nb;
277693db446aSBoris Brezillon int nchips;
277793db446aSBoris Brezillon int ret;
277893db446aSBoris Brezillon
277993db446aSBoris Brezillon if (!np)
278093db446aSBoris Brezillon nchips = 1;
278193db446aSBoris Brezillon else
278293db446aSBoris Brezillon nchips = of_get_child_count(np);
278393db446aSBoris Brezillon
278493db446aSBoris Brezillon if (nchips > max_cs) {
278593db446aSBoris Brezillon dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips,
278693db446aSBoris Brezillon max_cs);
278793db446aSBoris Brezillon return -EINVAL;
278893db446aSBoris Brezillon }
278993db446aSBoris Brezillon
279093db446aSBoris Brezillon /*
279193db446aSBoris Brezillon * Legacy bindings do not use child nodes to exhibit NAND chip
279293db446aSBoris Brezillon * properties and layout. Instead, NAND properties are mixed with the
279393db446aSBoris Brezillon * controller ones, and partitions are defined as direct subnodes of the
279493db446aSBoris Brezillon * NAND controller node.
279593db446aSBoris Brezillon */
279693db446aSBoris Brezillon if (nfc->caps->legacy_of_bindings) {
279793db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, np);
279893db446aSBoris Brezillon return ret;
279993db446aSBoris Brezillon }
280093db446aSBoris Brezillon
280193db446aSBoris Brezillon for_each_child_of_node(np, nand_np) {
280293db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, nand_np);
280393db446aSBoris Brezillon if (ret) {
280493db446aSBoris Brezillon of_node_put(nand_np);
2805c525b7afSMiquel Raynal goto cleanup_chips;
280693db446aSBoris Brezillon }
280793db446aSBoris Brezillon }
280893db446aSBoris Brezillon
280993db446aSBoris Brezillon return 0;
281093db446aSBoris Brezillon
2811c525b7afSMiquel Raynal cleanup_chips:
2812c525b7afSMiquel Raynal marvell_nand_chips_cleanup(nfc);
281393db446aSBoris Brezillon
2814c525b7afSMiquel Raynal return ret;
281593db446aSBoris Brezillon }
281693db446aSBoris Brezillon
marvell_nfc_init_dma(struct marvell_nfc * nfc)281793db446aSBoris Brezillon static int marvell_nfc_init_dma(struct marvell_nfc *nfc)
281893db446aSBoris Brezillon {
281993db446aSBoris Brezillon struct platform_device *pdev = container_of(nfc->dev,
282093db446aSBoris Brezillon struct platform_device,
282193db446aSBoris Brezillon dev);
282293db446aSBoris Brezillon struct dma_slave_config config = {};
282393db446aSBoris Brezillon struct resource *r;
282493db446aSBoris Brezillon int ret;
282593db446aSBoris Brezillon
282693db446aSBoris Brezillon if (!IS_ENABLED(CONFIG_PXA_DMA)) {
282793db446aSBoris Brezillon dev_warn(nfc->dev,
282893db446aSBoris Brezillon "DMA not enabled in configuration\n");
282993db446aSBoris Brezillon return -ENOTSUPP;
283093db446aSBoris Brezillon }
283193db446aSBoris Brezillon
283293db446aSBoris Brezillon ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32));
283393db446aSBoris Brezillon if (ret)
283493db446aSBoris Brezillon return ret;
283593db446aSBoris Brezillon
2836cf9e2389SPeter Ujfalusi nfc->dma_chan = dma_request_chan(nfc->dev, "data");
2837cf9e2389SPeter Ujfalusi if (IS_ERR(nfc->dma_chan)) {
2838cf9e2389SPeter Ujfalusi ret = PTR_ERR(nfc->dma_chan);
2839cf9e2389SPeter Ujfalusi nfc->dma_chan = NULL;
28406ce92faeSKrzysztof Kozlowski return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n");
284193db446aSBoris Brezillon }
284293db446aSBoris Brezillon
284393db446aSBoris Brezillon r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2844aafe30baSPeter Ujfalusi if (!r) {
2845aafe30baSPeter Ujfalusi ret = -ENXIO;
2846aafe30baSPeter Ujfalusi goto release_channel;
2847aafe30baSPeter Ujfalusi }
284893db446aSBoris Brezillon
284993db446aSBoris Brezillon config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
285093db446aSBoris Brezillon config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
285193db446aSBoris Brezillon config.src_addr = r->start + NDDB;
285293db446aSBoris Brezillon config.dst_addr = r->start + NDDB;
285393db446aSBoris Brezillon config.src_maxburst = 32;
285493db446aSBoris Brezillon config.dst_maxburst = 32;
285593db446aSBoris Brezillon ret = dmaengine_slave_config(nfc->dma_chan, &config);
285693db446aSBoris Brezillon if (ret < 0) {
285793db446aSBoris Brezillon dev_err(nfc->dev, "Failed to configure DMA channel\n");
2858aafe30baSPeter Ujfalusi goto release_channel;
285993db446aSBoris Brezillon }
286093db446aSBoris Brezillon
286193db446aSBoris Brezillon /*
286293db446aSBoris Brezillon * DMA must act on length multiple of 32 and this length may be
286393db446aSBoris Brezillon * bigger than the destination buffer. Use this buffer instead
286493db446aSBoris Brezillon * for DMA transfers and then copy the desired amount of data to
286593db446aSBoris Brezillon * the provided buffer.
286693db446aSBoris Brezillon */
286793db446aSBoris Brezillon nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA);
2868aafe30baSPeter Ujfalusi if (!nfc->dma_buf) {
2869aafe30baSPeter Ujfalusi ret = -ENOMEM;
2870aafe30baSPeter Ujfalusi goto release_channel;
2871aafe30baSPeter Ujfalusi }
287293db446aSBoris Brezillon
287393db446aSBoris Brezillon nfc->use_dma = true;
287493db446aSBoris Brezillon
287593db446aSBoris Brezillon return 0;
2876aafe30baSPeter Ujfalusi
2877aafe30baSPeter Ujfalusi release_channel:
2878aafe30baSPeter Ujfalusi dma_release_channel(nfc->dma_chan);
2879aafe30baSPeter Ujfalusi nfc->dma_chan = NULL;
2880aafe30baSPeter Ujfalusi
2881aafe30baSPeter Ujfalusi return ret;
288293db446aSBoris Brezillon }
288393db446aSBoris Brezillon
marvell_nfc_reset(struct marvell_nfc * nfc)2884bd9c3f9bSDaniel Mack static void marvell_nfc_reset(struct marvell_nfc *nfc)
2885bd9c3f9bSDaniel Mack {
2886bd9c3f9bSDaniel Mack /*
2887bd9c3f9bSDaniel Mack * ECC operations and interruptions are only enabled when specifically
2888bd9c3f9bSDaniel Mack * needed. ECC shall not be activated in the early stages (fails probe).
2889bd9c3f9bSDaniel Mack * Arbiter flag, even if marked as "reserved", must be set (empirical).
2890bd9c3f9bSDaniel Mack * SPARE_EN bit must always be set or ECC bytes will not be at the same
2891bd9c3f9bSDaniel Mack * offset in the read page and this will fail the protection.
2892bd9c3f9bSDaniel Mack */
2893bd9c3f9bSDaniel Mack writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN |
2894bd9c3f9bSDaniel Mack NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR);
2895bd9c3f9bSDaniel Mack writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR);
2896bd9c3f9bSDaniel Mack writel_relaxed(0, nfc->regs + NDECCCTRL);
2897bd9c3f9bSDaniel Mack }
2898bd9c3f9bSDaniel Mack
marvell_nfc_init(struct marvell_nfc * nfc)289993db446aSBoris Brezillon static int marvell_nfc_init(struct marvell_nfc *nfc)
290093db446aSBoris Brezillon {
290193db446aSBoris Brezillon struct device_node *np = nfc->dev->of_node;
290293db446aSBoris Brezillon
290393db446aSBoris Brezillon /*
290493db446aSBoris Brezillon * Some SoCs like A7k/A8k need to enable manually the NAND
290593db446aSBoris Brezillon * controller, gated clocks and reset bits to avoid being bootloader
290693db446aSBoris Brezillon * dependent. This is done through the use of the System Functions
290793db446aSBoris Brezillon * registers.
290893db446aSBoris Brezillon */
290993db446aSBoris Brezillon if (nfc->caps->need_system_controller) {
291093db446aSBoris Brezillon struct regmap *sysctrl_base =
291193db446aSBoris Brezillon syscon_regmap_lookup_by_phandle(np,
291293db446aSBoris Brezillon "marvell,system-controller");
291393db446aSBoris Brezillon
291493db446aSBoris Brezillon if (IS_ERR(sysctrl_base))
291593db446aSBoris Brezillon return PTR_ERR(sysctrl_base);
291693db446aSBoris Brezillon
291788aa3bbfSThomas Petazzoni regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX,
291888aa3bbfSThomas Petazzoni GENCONF_SOC_DEVICE_MUX_NFC_EN |
291993db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST |
292093db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST |
2921c13bf589SHamish Martin GENCONF_SOC_DEVICE_MUX_NFC_INT_EN |
2922c13bf589SHamish Martin GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN);
292393db446aSBoris Brezillon
292488aa3bbfSThomas Petazzoni regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL,
292588aa3bbfSThomas Petazzoni GENCONF_CLK_GATING_CTRL_ND_GATE,
292688aa3bbfSThomas Petazzoni GENCONF_CLK_GATING_CTRL_ND_GATE);
292793db446aSBoris Brezillon }
292893db446aSBoris Brezillon
292993db446aSBoris Brezillon /* Configure the DMA if appropriate */
293093db446aSBoris Brezillon if (!nfc->caps->is_nfcv2)
293193db446aSBoris Brezillon marvell_nfc_init_dma(nfc);
293293db446aSBoris Brezillon
2933bd9c3f9bSDaniel Mack marvell_nfc_reset(nfc);
293493db446aSBoris Brezillon
293593db446aSBoris Brezillon return 0;
293693db446aSBoris Brezillon }
293793db446aSBoris Brezillon
marvell_nfc_probe(struct platform_device * pdev)293893db446aSBoris Brezillon static int marvell_nfc_probe(struct platform_device *pdev)
293993db446aSBoris Brezillon {
294093db446aSBoris Brezillon struct device *dev = &pdev->dev;
294193db446aSBoris Brezillon struct marvell_nfc *nfc;
294293db446aSBoris Brezillon int ret;
294393db446aSBoris Brezillon int irq;
294493db446aSBoris Brezillon
294593db446aSBoris Brezillon nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc),
294693db446aSBoris Brezillon GFP_KERNEL);
294793db446aSBoris Brezillon if (!nfc)
294893db446aSBoris Brezillon return -ENOMEM;
294993db446aSBoris Brezillon
295093db446aSBoris Brezillon nfc->dev = dev;
29517da45139SMiquel Raynal nand_controller_init(&nfc->controller);
29528831e48bSMiquel Raynal nfc->controller.ops = &marvell_nand_controller_ops;
295393db446aSBoris Brezillon INIT_LIST_HEAD(&nfc->chips);
295493db446aSBoris Brezillon
29555dcc9976SMiquel Raynal nfc->regs = devm_platform_ioremap_resource(pdev, 0);
295693db446aSBoris Brezillon if (IS_ERR(nfc->regs))
295793db446aSBoris Brezillon return PTR_ERR(nfc->regs);
295893db446aSBoris Brezillon
295993db446aSBoris Brezillon irq = platform_get_irq(pdev, 0);
2960aab478caSStephen Boyd if (irq < 0)
296193db446aSBoris Brezillon return irq;
296293db446aSBoris Brezillon
29636b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, "core");
2964961ba15cSGregory CLEMENT
2965961ba15cSGregory CLEMENT /* Managed the legacy case (when the first clock was not named) */
29666b6de654SBoris Brezillon if (nfc->core_clk == ERR_PTR(-ENOENT))
29676b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, NULL);
2968961ba15cSGregory CLEMENT
29696b6de654SBoris Brezillon if (IS_ERR(nfc->core_clk))
29706b6de654SBoris Brezillon return PTR_ERR(nfc->core_clk);
297193db446aSBoris Brezillon
29726b6de654SBoris Brezillon ret = clk_prepare_enable(nfc->core_clk);
297393db446aSBoris Brezillon if (ret)
297493db446aSBoris Brezillon return ret;
297593db446aSBoris Brezillon
2976961ba15cSGregory CLEMENT nfc->reg_clk = devm_clk_get(&pdev->dev, "reg");
2977f9e64d61SDaniel Mack if (IS_ERR(nfc->reg_clk)) {
2978961ba15cSGregory CLEMENT if (PTR_ERR(nfc->reg_clk) != -ENOENT) {
2979961ba15cSGregory CLEMENT ret = PTR_ERR(nfc->reg_clk);
29806b6de654SBoris Brezillon goto unprepare_core_clk;
2981961ba15cSGregory CLEMENT }
2982f9e64d61SDaniel Mack
2983f9e64d61SDaniel Mack nfc->reg_clk = NULL;
2984961ba15cSGregory CLEMENT }
2985961ba15cSGregory CLEMENT
2986f9e64d61SDaniel Mack ret = clk_prepare_enable(nfc->reg_clk);
2987f9e64d61SDaniel Mack if (ret)
2988f9e64d61SDaniel Mack goto unprepare_core_clk;
2989f9e64d61SDaniel Mack
299093db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_ALL_INT);
299193db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
299293db446aSBoris Brezillon ret = devm_request_irq(dev, irq, marvell_nfc_isr,
299393db446aSBoris Brezillon 0, "marvell-nfc", nfc);
299493db446aSBoris Brezillon if (ret)
2995961ba15cSGregory CLEMENT goto unprepare_reg_clk;
299693db446aSBoris Brezillon
299793db446aSBoris Brezillon /* Get NAND controller capabilities */
299893db446aSBoris Brezillon if (pdev->id_entry)
299993db446aSBoris Brezillon nfc->caps = (void *)pdev->id_entry->driver_data;
300093db446aSBoris Brezillon else
300193db446aSBoris Brezillon nfc->caps = of_device_get_match_data(&pdev->dev);
300293db446aSBoris Brezillon
300393db446aSBoris Brezillon if (!nfc->caps) {
300493db446aSBoris Brezillon dev_err(dev, "Could not retrieve NFC caps\n");
300593db446aSBoris Brezillon ret = -EINVAL;
3006961ba15cSGregory CLEMENT goto unprepare_reg_clk;
300793db446aSBoris Brezillon }
300893db446aSBoris Brezillon
300993db446aSBoris Brezillon /* Init the controller and then probe the chips */
301093db446aSBoris Brezillon ret = marvell_nfc_init(nfc);
301193db446aSBoris Brezillon if (ret)
3012961ba15cSGregory CLEMENT goto unprepare_reg_clk;
301393db446aSBoris Brezillon
301493db446aSBoris Brezillon platform_set_drvdata(pdev, nfc);
301593db446aSBoris Brezillon
301693db446aSBoris Brezillon ret = marvell_nand_chips_init(dev, nfc);
301793db446aSBoris Brezillon if (ret)
3018aafe30baSPeter Ujfalusi goto release_dma;
301993db446aSBoris Brezillon
302093db446aSBoris Brezillon return 0;
302193db446aSBoris Brezillon
3022aafe30baSPeter Ujfalusi release_dma:
3023aafe30baSPeter Ujfalusi if (nfc->use_dma)
3024aafe30baSPeter Ujfalusi dma_release_channel(nfc->dma_chan);
3025961ba15cSGregory CLEMENT unprepare_reg_clk:
3026961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk);
30276b6de654SBoris Brezillon unprepare_core_clk:
30286b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk);
302993db446aSBoris Brezillon
303093db446aSBoris Brezillon return ret;
303193db446aSBoris Brezillon }
303293db446aSBoris Brezillon
marvell_nfc_remove(struct platform_device * pdev)3033ec185b18SUwe Kleine-König static void marvell_nfc_remove(struct platform_device *pdev)
303493db446aSBoris Brezillon {
303593db446aSBoris Brezillon struct marvell_nfc *nfc = platform_get_drvdata(pdev);
303693db446aSBoris Brezillon
303793db446aSBoris Brezillon marvell_nand_chips_cleanup(nfc);
303893db446aSBoris Brezillon
303993db446aSBoris Brezillon if (nfc->use_dma) {
304093db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan);
304193db446aSBoris Brezillon dma_release_channel(nfc->dma_chan);
304293db446aSBoris Brezillon }
304393db446aSBoris Brezillon
3044961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk);
30456b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk);
304693db446aSBoris Brezillon }
304793db446aSBoris Brezillon
marvell_nfc_suspend(struct device * dev)3048bd9c3f9bSDaniel Mack static int __maybe_unused marvell_nfc_suspend(struct device *dev)
3049bd9c3f9bSDaniel Mack {
3050bd9c3f9bSDaniel Mack struct marvell_nfc *nfc = dev_get_drvdata(dev);
3051bd9c3f9bSDaniel Mack struct marvell_nand_chip *chip;
3052bd9c3f9bSDaniel Mack
3053bd9c3f9bSDaniel Mack list_for_each_entry(chip, &nfc->chips, node)
3054bd9c3f9bSDaniel Mack marvell_nfc_wait_ndrun(&chip->chip);
3055bd9c3f9bSDaniel Mack
3056bd9c3f9bSDaniel Mack clk_disable_unprepare(nfc->reg_clk);
3057bd9c3f9bSDaniel Mack clk_disable_unprepare(nfc->core_clk);
3058bd9c3f9bSDaniel Mack
3059bd9c3f9bSDaniel Mack return 0;
3060bd9c3f9bSDaniel Mack }
3061bd9c3f9bSDaniel Mack
marvell_nfc_resume(struct device * dev)3062bd9c3f9bSDaniel Mack static int __maybe_unused marvell_nfc_resume(struct device *dev)
3063bd9c3f9bSDaniel Mack {
3064bd9c3f9bSDaniel Mack struct marvell_nfc *nfc = dev_get_drvdata(dev);
3065bd9c3f9bSDaniel Mack int ret;
3066bd9c3f9bSDaniel Mack
3067bd9c3f9bSDaniel Mack ret = clk_prepare_enable(nfc->core_clk);
3068bd9c3f9bSDaniel Mack if (ret < 0)
3069bd9c3f9bSDaniel Mack return ret;
3070bd9c3f9bSDaniel Mack
3071bd9c3f9bSDaniel Mack ret = clk_prepare_enable(nfc->reg_clk);
3072ae94c495SYang Yingliang if (ret < 0) {
3073ae94c495SYang Yingliang clk_disable_unprepare(nfc->core_clk);
3074bd9c3f9bSDaniel Mack return ret;
3075ae94c495SYang Yingliang }
3076bd9c3f9bSDaniel Mack
3077bd9c3f9bSDaniel Mack /*
3078bd9c3f9bSDaniel Mack * Reset nfc->selected_chip so the next command will cause the timing
30792e16dc73SMiquel Raynal * registers to be restored in marvell_nfc_select_target().
3080bd9c3f9bSDaniel Mack */
3081bd9c3f9bSDaniel Mack nfc->selected_chip = NULL;
3082bd9c3f9bSDaniel Mack
3083bd9c3f9bSDaniel Mack /* Reset registers that have lost their contents */
3084bd9c3f9bSDaniel Mack marvell_nfc_reset(nfc);
3085bd9c3f9bSDaniel Mack
3086bd9c3f9bSDaniel Mack return 0;
3087bd9c3f9bSDaniel Mack }
3088bd9c3f9bSDaniel Mack
3089bd9c3f9bSDaniel Mack static const struct dev_pm_ops marvell_nfc_pm_ops = {
3090bd9c3f9bSDaniel Mack SET_SYSTEM_SLEEP_PM_OPS(marvell_nfc_suspend, marvell_nfc_resume)
3091bd9c3f9bSDaniel Mack };
3092bd9c3f9bSDaniel Mack
309393db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = {
309493db446aSBoris Brezillon .max_cs_nb = 4,
309593db446aSBoris Brezillon .max_rb_nb = 2,
309693db446aSBoris Brezillon .need_system_controller = true,
309793db446aSBoris Brezillon .is_nfcv2 = true,
309893db446aSBoris Brezillon };
309993db446aSBoris Brezillon
310072b9a3fcSChris Packham static const struct marvell_nfc_caps marvell_ac5_caps = {
310172b9a3fcSChris Packham .max_cs_nb = 2,
310272b9a3fcSChris Packham .max_rb_nb = 1,
310372b9a3fcSChris Packham .is_nfcv2 = true,
310472b9a3fcSChris Packham .max_mode_number = 3,
310572b9a3fcSChris Packham };
310672b9a3fcSChris Packham
310793db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_caps = {
310893db446aSBoris Brezillon .max_cs_nb = 4,
310993db446aSBoris Brezillon .max_rb_nb = 2,
311093db446aSBoris Brezillon .is_nfcv2 = true,
311193db446aSBoris Brezillon };
311293db446aSBoris Brezillon
311393db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = {
311493db446aSBoris Brezillon .max_cs_nb = 2,
311593db446aSBoris Brezillon .max_rb_nb = 1,
311693db446aSBoris Brezillon .use_dma = true,
311793db446aSBoris Brezillon };
311893db446aSBoris Brezillon
311993db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = {
312093db446aSBoris Brezillon .max_cs_nb = 4,
312193db446aSBoris Brezillon .max_rb_nb = 2,
312293db446aSBoris Brezillon .need_system_controller = true,
312393db446aSBoris Brezillon .legacy_of_bindings = true,
312493db446aSBoris Brezillon .is_nfcv2 = true,
312593db446aSBoris Brezillon };
312693db446aSBoris Brezillon
312793db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = {
312893db446aSBoris Brezillon .max_cs_nb = 4,
312993db446aSBoris Brezillon .max_rb_nb = 2,
313093db446aSBoris Brezillon .legacy_of_bindings = true,
313193db446aSBoris Brezillon .is_nfcv2 = true,
313293db446aSBoris Brezillon };
313393db446aSBoris Brezillon
313493db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = {
313593db446aSBoris Brezillon .max_cs_nb = 2,
313693db446aSBoris Brezillon .max_rb_nb = 1,
313793db446aSBoris Brezillon .legacy_of_bindings = true,
313893db446aSBoris Brezillon .use_dma = true,
313993db446aSBoris Brezillon };
314093db446aSBoris Brezillon
314193db446aSBoris Brezillon static const struct platform_device_id marvell_nfc_platform_ids[] = {
314293db446aSBoris Brezillon {
314393db446aSBoris Brezillon .name = "pxa3xx-nand",
314493db446aSBoris Brezillon .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps,
314593db446aSBoris Brezillon },
314693db446aSBoris Brezillon { /* sentinel */ },
314793db446aSBoris Brezillon };
314893db446aSBoris Brezillon MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids);
314993db446aSBoris Brezillon
315093db446aSBoris Brezillon static const struct of_device_id marvell_nfc_of_ids[] = {
315193db446aSBoris Brezillon {
315293db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand-controller",
315393db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_caps,
315493db446aSBoris Brezillon },
315593db446aSBoris Brezillon {
315672b9a3fcSChris Packham .compatible = "marvell,ac5-nand-controller",
315772b9a3fcSChris Packham .data = &marvell_ac5_caps,
315872b9a3fcSChris Packham },
315972b9a3fcSChris Packham {
316093db446aSBoris Brezillon .compatible = "marvell,armada370-nand-controller",
316193db446aSBoris Brezillon .data = &marvell_armada370_nfc_caps,
316293db446aSBoris Brezillon },
316393db446aSBoris Brezillon {
316493db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand-controller",
316593db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_caps,
316693db446aSBoris Brezillon },
316793db446aSBoris Brezillon /* Support for old/deprecated bindings: */
316893db446aSBoris Brezillon {
316993db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand",
317093db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_legacy_caps,
317193db446aSBoris Brezillon },
317293db446aSBoris Brezillon {
317393db446aSBoris Brezillon .compatible = "marvell,armada370-nand",
317493db446aSBoris Brezillon .data = &marvell_armada370_nfc_legacy_caps,
317593db446aSBoris Brezillon },
317693db446aSBoris Brezillon {
317793db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand",
317893db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_legacy_caps,
317993db446aSBoris Brezillon },
318093db446aSBoris Brezillon { /* sentinel */ },
318193db446aSBoris Brezillon };
318293db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids);
318393db446aSBoris Brezillon
318493db446aSBoris Brezillon static struct platform_driver marvell_nfc_driver = {
318593db446aSBoris Brezillon .driver = {
318693db446aSBoris Brezillon .name = "marvell-nfc",
318793db446aSBoris Brezillon .of_match_table = marvell_nfc_of_ids,
3188bd9c3f9bSDaniel Mack .pm = &marvell_nfc_pm_ops,
318993db446aSBoris Brezillon },
319093db446aSBoris Brezillon .id_table = marvell_nfc_platform_ids,
319193db446aSBoris Brezillon .probe = marvell_nfc_probe,
3192ec185b18SUwe Kleine-König .remove_new = marvell_nfc_remove,
319393db446aSBoris Brezillon };
319493db446aSBoris Brezillon module_platform_driver(marvell_nfc_driver);
319593db446aSBoris Brezillon
319693db446aSBoris Brezillon MODULE_LICENSE("GPL");
319793db446aSBoris Brezillon MODULE_DESCRIPTION("Marvell NAND controller driver");
3198