Lines Matching +full:pico +full:- +full:seconds
1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
19 /* this might need panel specific set-up as-well */
22 /* -------------- controller specific stuff -------------- */
100 /* IPU_CONF and its bits already defined in imx-regs.h */
352 * sdc_init_panel() - initialize a synchronous LCD panel.
371 return -EACCES; in sdc_init_panel()
374 reg = width + mode->left_margin + mode->right_margin - 1; in sdc_init_panel()
379 reg = ((mode->hsync_len - 1) << 26) | (reg << 16); in sdc_init_panel()
382 reg = height + mode->upper_margin + mode->lower_margin - 1; in sdc_init_panel()
387 reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16); in sdc_init_panel()
401 return -EINVAL; in sdc_init_panel()
408 * Opposed to the kernel driver mode->pixclock is the time of one in sdc_init_panel()
409 * pixel in pico seconds, so: in sdc_init_panel()
410 * pixel_clk = 1e12 / mode->pixclock in sdc_init_panel()
413 * div = ipu_clk * 16 / (1e12 / mode->pixclock) in sdc_init_panel()
415 * div = ipu_clk * 16 * mode->pixclock / 1e12 in sdc_init_panel()
421 div = ((clock/1024) * (mode->pixclock/128)) / 476837; in sdc_init_panel()
432 writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); in sdc_init_panel()
440 writel(old_conf | mode->sync, DI_DISP_SIG_POL); in sdc_init_panel()
446 ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC); in sdc_init_panel()
464 params->pp.fw = width - 1; in ipu_ch_param_set_size()
465 params->pp.fh_l = height - 1; in ipu_ch_param_set_size()
466 params->pp.fh_h = (height - 1) >> 8; in ipu_ch_param_set_size()
467 params->pp.sl = stride - 1; in ipu_ch_param_set_size()
472 params->ip.bpp = 2; in ipu_ch_param_set_size()
473 params->ip.pfs = 4; in ipu_ch_param_set_size()
474 params->ip.npb = 7; in ipu_ch_param_set_size()
475 params->ip.sat = 2; /* SAT = 32-bit access */ in ipu_ch_param_set_size()
476 params->ip.ofs0 = 0; /* Red bit offset */ in ipu_ch_param_set_size()
477 params->ip.ofs1 = 5; /* Green bit offset */ in ipu_ch_param_set_size()
478 params->ip.ofs2 = 11; /* Blue bit offset */ in ipu_ch_param_set_size()
479 params->ip.ofs3 = 16; /* Alpha bit offset */ in ipu_ch_param_set_size()
480 params->ip.wid0 = 4; /* Red bit width - 1 */ in ipu_ch_param_set_size()
481 params->ip.wid1 = 5; /* Green bit width - 1 */ in ipu_ch_param_set_size()
482 params->ip.wid2 = 4; /* Blue bit width - 1 */ in ipu_ch_param_set_size()
485 params->ip.bpp = 1; /* 24 BPP & RGB PFS */ in ipu_ch_param_set_size()
486 params->ip.pfs = 4; in ipu_ch_param_set_size()
487 params->ip.npb = 7; in ipu_ch_param_set_size()
488 params->ip.sat = 2; /* SAT = 32-bit access */ in ipu_ch_param_set_size()
489 params->ip.ofs0 = 16; /* Red bit offset */ in ipu_ch_param_set_size()
490 params->ip.ofs1 = 8; /* Green bit offset */ in ipu_ch_param_set_size()
491 params->ip.ofs2 = 0; /* Blue bit offset */ in ipu_ch_param_set_size()
492 params->ip.ofs3 = 24; /* Alpha bit offset */ in ipu_ch_param_set_size()
493 params->ip.wid0 = 7; /* Red bit width - 1 */ in ipu_ch_param_set_size()
494 params->ip.wid1 = 7; /* Green bit width - 1 */ in ipu_ch_param_set_size()
495 params->ip.wid2 = 7; /* Blue bit width - 1 */ in ipu_ch_param_set_size()
502 params->pp.nsb = 1; in ipu_ch_param_set_size()
508 params->pp.eba0 = (u32)buf0; in ipu_ch_param_set_buffer()
509 params->pp.eba1 = (u32)buf1; in ipu_ch_param_set_buffer()
515 for (; num_words > 0; num_words--) { in ipu_write_param_mem()
552 params.pp.npb = 16 - 1; in ipu_init_channel_buffer()
560 /* Disable double-buffering */ in ipu_init_channel_buffer()
580 * ipu_enable_channel() - enable an IPU channel.
611 return -EACCES; in ipu_update_channel_buffer()
613 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */ in ipu_update_channel_buffer()
663 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
676 writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS); in mx3fb_set_par()
725 /* Service request counter to maximum - shouldn't be needed */ in ll_disp3_enable()
740 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ in ll_disp3_enable()
745 /* This might be board-specific */ in ll_disp3_enable()
751 /* Use global - not per-pixel - Alpha-blending */ in ll_disp3_enable()
761 /* Disable colour-keying for background */ in ll_disp3_enable()
778 /* ------------------------ public part ------------------- */
847 t1 = (mode->left_margin + mode->xres + in video_hw_init()
848 mode->right_margin + mode->hsync_len) / 8; in video_hw_init()
850 t1 *= mode->pixclock; in video_hw_init()
853 t1 *= (mode->upper_margin + mode->yres + in video_hw_init()
854 mode->lower_margin + mode->vsync_len); in video_hw_init()
860 mode->xres, mode->yres, in video_hw_init()
863 panel.winSizeX = mode->xres; in video_hw_init()
864 panel.winSizeY = mode->yres; in video_hw_init()
865 panel.plnSizeX = mode->xres; in video_hw_init()
866 panel.plnSizeY = mode->yres; in video_hw_init()