/openbmc/linux/include/uapi/linux/ |
H A D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 4 * Copyright 2006-2009 Solarflare Communications Inc. 22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ 25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ 40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */ 41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */ 42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */ 49 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */ 51 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ 58 /* Media-dependent registers. */ [all …]
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/openbmc/u-boot/include/linux/ |
H A D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 4 * Copyright 2006-2009 Solarflare Communications Inc. 21 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ 24 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ 39 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */ 40 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */ 41 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */ 48 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ 52 /* Media-dependent registers. */ 53 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | samsung,ufs-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung SoC series UFS PHY 10 - Alim Akhtar <alim.akhtar@samsung.com> 13 "#phy-cells": 18 - samsung,exynos7-ufs-phy 19 - samsung,exynosautov9-ufs-phy 20 - tesla,fsd-ufs-phy [all …]
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H A D | cdns,dphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Pratyush Yadav <pratyush@kernel.org> 15 - cdns,dphy 16 - ti,j721e-dphy 23 - description: PMA state machine clock 24 - description: PLL reference clock 26 clock-names: [all …]
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H A D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Kishon Vijay Abraham I <kishon@ti.com> 16 - ti,j721e-wiz-16g 17 - ti,j721e-wiz-10g 18 - ti,j721s2-wiz-10g 19 - ti,am64-wiz-10g [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 provides connectivity to an external ethernet PHY supporting different 22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> 27 - xlnx,axi-ethernet-1.00.a 28 - xlnx,axi-ethernet-1.01.a 29 - xlnx,axi-ethernet-2.01.a 35 axistream-connected is specified, in which case the reg [all …]
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/openbmc/u-boot/drivers/net/phy/ |
H A D | xilinx_phy.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Xilinx PCS/PMA Core phy driver 5 * Copyright (C) 2015 - 2016 Xilinx, Inc. 10 #include <phy.h> 22 /* Known PHY IDs */ 46 if (AUTONEG_ENABLE == phydev->autoneg) { in xilinxphy_startup() 51 phydev->duplex = DUPLEX_FULL; in xilinxphy_startup() 53 phydev->duplex = DUPLEX_HALF; in xilinxphy_startup() 57 phydev->speed = SPEED_1000; in xilinxphy_startup() 61 phydev->speed = SPEED_100; in xilinxphy_startup() [all …]
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H A D | generic_10g.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Generic PHY Management code 8 * Based loosely off of Linux's PHY Lib 12 #include <phy.h> 22 u32 mmd_mask = phydev->mmds & MDIO_DEVS_LINK; in gen10g_startup() 24 phydev->link = 1; in gen10g_startup() 27 phydev->speed = SPEED_10000; in gen10g_startup() 28 phydev->duplex = DUPLEX_FULL; in gen10g_startup() 31 * Go through all the link-reporting devices, and make sure in gen10g_startup() 43 phydev->link = 0; in gen10g_startup() [all …]
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/openbmc/linux/drivers/net/phy/ |
H A D | phy-c45.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Clause 45 PHY support 9 #include <linux/phy.h> 11 #include "mdio-open-alliance.h" 14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 21 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able() 26 phydev->pma_extable = val; in genphy_c45_baset1_able() 29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able() 33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 48 * genphy_c45_pma_resume - wakes up the PMA module [all …]
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H A D | marvell10g.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Marvell 10G 88x3310 PHY driver 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 18 * XAUI PHYXS -- <appropriate PCS as above> [all …]
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H A D | marvell-88q2xxx.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Marvell 88Q2XXX automotive 100BASE-T1/1000BASE-T1 PHY driver 7 #include <linux/phy.h> 51 /* Read vendor specific Auto-Negotiation status register to get local in mv88q2xxx_read_link_gbit() 61 * drops can be detected. Do not double-read the status in mv88q2xxx_read_link_gbit() 65 if (!phy_polling_mode(phydev) || !phydev->link) { in mv88q2xxx_read_link_gbit() 82 phydev->link = link; in mv88q2xxx_read_link_gbit() 92 * drops can be detected. Do not double-read the status in mv88q2xxx_read_link_100m() 97 if (!phy_polling_mode(phydev) || !phydev->link) { in mv88q2xxx_read_link_100m() 114 phydev->link = true; in mv88q2xxx_read_link_100m() [all …]
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H A D | marvell-88x2222.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Marvell 88x2222 dual-port multi-speed ethernet transceiver. 7 * 1000Base-X or 10GBase-R on the line side. 8 * SGMII over 1000Base-X. 11 #include <linux/phy.h> 38 /* 1000Base-X/SGMII Control Register */ 41 /* 1000BASE-X/SGMII Status Register */ 44 /* 1000Base-X Auto-Negotiation Advertisement Register */ 47 /* 1000Base-X PHY Specific Status Register */ 62 /* SFI PMA transmit enable */ [all …]
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/openbmc/linux/drivers/net/ethernet/sfc/falcon/ |
H A D | qt202x_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Copyright 2006-2012 Solarflare Communications Inc. 15 #include "phy.h" 27 /* Quake-specific MDIO registers */ 85 ((1 << PCS_FW_HEARTB_WIDTH) - 1)); in qt2025c_wait_heartbeat() 92 * PHY's on-board EEPROM so it cannot load firmware */ in qt2025c_wait_heartbeat() 93 netif_err(efx, hw, efx->net_dev, in qt2025c_wait_heartbeat() 97 return -ETIMEDOUT; in qt2025c_wait_heartbeat() 116 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= in qt2025c_wait_fw_status_good() 120 return -ETIMEDOUT; in qt2025c_wait_fw_status_good() [all …]
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H A D | txc43128_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Copyright 2006-2011 Solarflare Communications Inc. 9 * see www.transwitch.com, part is TXC-43128 16 #include "phy.h" 30 * Compile-time config 35 /* Total length of time we'll wait for the PHY to come out of reset (ms) */ 52 /* Lane power-down */ 56 * initiates a logic reset. Self-clearing */ 69 /* Lane power-down */ 108 /* Lane power-down */ [all …]
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/openbmc/linux/drivers/phy/rockchip/ |
H A D | phy-rockchip-snps-pcie3.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Rockchip PCIE3.0 phy driver 16 #include <linux/phy/pcie.h> 17 #include <linux/phy/phy.h> 58 struct phy *phy; member 69 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument 71 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode() 76 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode() 79 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode() 82 dev_err(&phy->dev, "%s, invalid mode\n", __func__); in rockchip_p3phy_set_mode() [all …]
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/openbmc/linux/drivers/phy/cadence/ |
H A D | phy-cadence-sierra.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Cadence Sierra PHY Driver 10 #include <linux/clk-provider.h> 15 #include <linux/phy/phy.h> 23 #include <dt-bindings/phy/phy.h> 24 #include <dt-bindings/phy/phy-cadence.h> 29 /* PHY register offsets */ 203 /* PHY PCS common registers */ 209 /* PHY PCS lane registers */ 216 /* PHY PMA common registers */ [all …]
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H A D | phy-cadence-torrent.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Cadence Torrent SD0801 PHY driver. 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-cadence.h> 12 #include <linux/clk-provider.h> 20 #include <linux/phy/phy.h> 62 * register offsets from DPTX PHY register block base (i.e MHDP 77 * register offsets from SD0801 PHY register block base (i.e MHDP 168 /* PMA TX Lane registers */ 189 /* PMA RX Lane registers */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | cdns,mhdp8546.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Swapnil Jakhade <sjakhade@cadence.com> 11 - Yuti Amonkar <yamonkar@cadence.com> 16 - cdns,mhdp8546 17 - ti,j721e-mhdp8546 22 - description: 23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). 24 The AUX and PMA registers are not part of this range, they are instead [all …]
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/openbmc/linux/drivers/net/ethernet/xilinx/ |
H A D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved. 147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/ 157 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */ 201 /* Transmit inter-frame gap adjustment value */ 217 #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */ 235 /* In-Band FCS enable (FCS not stripped) */ 251 /* In-Band FCS enable (FCS not generated) */ 255 /* Inter-frame gap adjustment enable */ 277 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */ [all …]
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/openbmc/linux/drivers/phy/samsung/ |
H A D | phy-samsung-ufs.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * UFS PHY driver for Samsung SoC 18 #include <linux/phy/phy.h> 22 #include "phy-samsung-ufs.h" 24 #define for_each_phy_lane(phy, i) \ argument 25 for (i = 0; i < (phy)->lane_cnt; i++) 27 for (; (cfg)->id; (cfg)++) 31 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, in samsung_ufs_phy_config() argument 39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config() 42 if (cfg->id == PHY_TRSV_BLK) in samsung_ufs_phy_config() [all …]
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/ |
H A D | ael1002.c | 2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved. 14 * - Redistributions of source code must retain the above 18 * - Redistributions in binary form must reproduce the above 62 /* PHY module I2C device address */ 68 /* PHY transceiver type */ 84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument 88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs() 89 if (rv->clear_bits == 0xffff) in set_phy_regs() 90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs() 91 rv->set_bits); in set_phy_regs() [all …]
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/openbmc/linux/drivers/phy/ti/ |
H A D | phy-am654-serdes.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/ 9 #include <dt-bindings/phy/phy.h> 11 #include <linux/clk-provider.h> 17 #include <linux/phy/phy.h> 119 /* AHB PMA Lane Configuration */ 142 /* Mid-speed initial calibration control */ 145 /* High-speed initial calibration control */ 148 /* Mid-speed recalibration control */ 151 /* High-speed recalibration control */ [all …]
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/openbmc/linux/drivers/net/ |
H A D | mdio.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * mdio.c: Generic support for MDIO-compatible transceivers 4 * Copyright 2006-2009 Solarflare Communications Inc. 14 MODULE_DESCRIPTION("Generic support for MDIO-compatible transceivers"); 15 MODULE_AUTHOR("Copyright 2006-2009 Solarflare Communications Inc."); 19 * mdio45_probe - probe for an MDIO (clause 45) device 21 * @prtad: Expected PHY address 30 /* Assume PHY must have at least one of PMA/PMD, WIS, PCS, PHY in mdio45_probe() 34 stat2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_STAT2); in mdio45_probe() 40 devs1 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS1); in mdio45_probe() [all …]
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/openbmc/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos7.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/clock/exynos7-clk.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 31 arm-pmu { 32 compatible = "arm,cortex-a57-pmu"; 37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, 43 compatible = "fixed-clock"; [all …]
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/openbmc/linux/drivers/scsi/bfa/ |
H A D | bfa_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 4 * Copyright (c) 2014- QLogic Corporation. 8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter. 34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */ 102 * All numerical fields are in big-endian format. 125 BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if persists, 129 BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */ 132 BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */ 148 BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists [all …]
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