Lines Matching +full:phy +full:- +full:pma
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
9 #include <linux/phy.h>
11 #include "mdio-open-alliance.h"
14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
21 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
26 phydev->pma_extable = val; in genphy_c45_baset1_able()
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
48 * genphy_c45_pma_resume - wakes up the PMA module
54 return -EOPNOTSUPP; in genphy_c45_pma_resume()
62 * genphy_c45_pma_suspend - suspends the PMA module
68 return -EOPNOTSUPP; in genphy_c45_pma_suspend()
76 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave
84 switch (phydev->master_slave_set) { in genphy_c45_pma_baset1_setup_master_slave()
97 return -EOPNOTSUPP; in genphy_c45_pma_baset1_setup_master_slave()
106 * genphy_c45_pma_setup_forced - configures a forced speed
114 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
115 return -EINVAL; in genphy_c45_pma_setup_forced()
127 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 in genphy_c45_pma_setup_forced()
128 * in 802.3-2012 and 802.3-2015. in genphy_c45_pma_setup_forced()
132 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
145 /* Assume 1000base-T */ in genphy_c45_pma_setup_forced()
150 /* Assume 2.5Gbase-T */ in genphy_c45_pma_setup_forced()
155 /* Assume 5Gbase-T */ in genphy_c45_pma_setup_forced()
160 /* Assume 10Gbase-T */ in genphy_c45_pma_setup_forced()
164 return -EINVAL; in genphy_c45_pma_setup_forced()
181 if (phydev->speed == SPEED_1000) in genphy_c45_pma_setup_forced()
195 * The preference is set in the BIT(4) of BASE-T1 AN
197 * is forced or not, it is set in the BIT(12) of BASE-T1
199 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation
213 switch (phydev->master_slave_set) { in genphy_c45_baset1_an_config_aneg()
233 return -EOPNOTSUPP; in genphy_c45_baset1_an_config_aneg()
236 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
245 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
258 * genphy_c45_an_config_aneg - configure advertisement registers
261 * Configure advertisement registers based on modes set in phydev->advertising
271 linkmode_and(phydev->advertising, phydev->advertising, in genphy_c45_an_config_aneg()
272 phydev->supported); in genphy_c45_an_config_aneg()
283 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
294 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
310 * genphy_c45_an_disable_aneg - disable auto-negotiation
313 * Disable auto-negotiation in the Clause 45 PHY. The link parameters
314 * are controlled through the PMA/PMD MMD registers.
331 * genphy_c45_restart_aneg - Enable and restart auto-negotiation
334 * This assumes that the auto-negotiation MMD is present.
336 * Enable and restart auto-negotiation.
351 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
355 * This assumes that the auto-negotiation MMD is present.
357 * Check, and restart auto-negotiation if needed.
385 * genphy_c45_aneg_done - return auto-negotiation complete status
388 * This assumes that the auto-negotiation MMD is present.
390 * Reads the status register from the auto-negotiation MMD, returning:
391 * - positive if auto-negotiation is complete
392 * - negative errno code on error
393 * - zero otherwise
410 * genphy_c45_read_link - read the overall link status from the MMDs
414 * that the link is up, set phydev->link to 1. If an error is encountered,
423 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_read_link()
432 phydev->link = 0; in genphy_c45_read_link()
442 * drops can be detected. Do not double-read the status in genphy_c45_read_link()
446 if (!phy_polling_mode(phydev) || !phydev->link) { in genphy_c45_read_link()
462 phydev->link = link; in genphy_c45_read_link()
468 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
469 * if autoneg is complete. If so read the BASE-T1 Autonegotiation
482 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); in genphy_c45_baset1_read_lpa()
483 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
484 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
486 phydev->pause = 0; in genphy_c45_baset1_read_lpa()
487 phydev->asym_pause = 0; in genphy_c45_baset1_read_lpa()
492 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); in genphy_c45_baset1_read_lpa()
498 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
499 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; in genphy_c45_baset1_read_lpa()
500 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; in genphy_c45_baset1_read_lpa()
506 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
512 * genphy_c45_read_lpa - read the link partner advertisement and pause
517 * in @phydev. This assumes that the auto-negotiation MMD is present, and
518 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
534 phydev->lp_advertising); in genphy_c45_read_lpa()
535 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
536 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
537 phydev->pause = 0; in genphy_c45_read_lpa()
538 phydev->asym_pause = 0; in genphy_c45_read_lpa()
543 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, in genphy_c45_read_lpa()
551 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
552 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
553 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
560 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
567 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave
575 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
576 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
583 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_pma_baset1_read_master_slave()
584 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in genphy_c45_pma_baset1_read_master_slave()
586 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_pma_baset1_read_master_slave()
587 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in genphy_c45_pma_baset1_read_master_slave()
595 * genphy_c45_read_pma - read link speed etc from PMA
602 linkmode_zero(phydev->lp_advertising); in genphy_c45_read_pma()
610 phydev->speed = SPEED_10; in genphy_c45_read_pma()
613 phydev->speed = SPEED_100; in genphy_c45_read_pma()
616 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
619 phydev->speed = SPEED_2500; in genphy_c45_read_pma()
622 phydev->speed = SPEED_5000; in genphy_c45_read_pma()
625 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
628 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
632 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
645 * genphy_c45_read_mdix - read mdix status from PMA
652 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
660 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
664 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
668 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
678 * genphy_c45_write_eee_adv - write advertised EEE link modes
686 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_write_eee_adv()
692 val &= ~phydev->eee_broken_modes; in genphy_c45_write_eee_adv()
694 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 in genphy_c45_write_eee_adv()
710 phydev->supported_eee)) { in genphy_c45_write_eee_adv()
712 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register in genphy_c45_write_eee_adv()
729 * genphy_c45_read_eee_adv - read advertised EEE link modes
737 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_adv()
738 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 in genphy_c45_read_eee_adv()
749 phydev->supported_eee)) { in genphy_c45_read_eee_adv()
750 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register in genphy_c45_read_eee_adv()
764 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes
773 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_lpa()
774 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1 in genphy_c45_read_eee_lpa()
785 phydev->supported_eee)) { in genphy_c45_read_eee_lpa()
786 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register in genphy_c45_read_eee_lpa()
800 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20
807 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1 in genphy_c45_read_eee_cap1()
815 * read as 0. Also, it seems unlikely anybody will build a PHY which in genphy_c45_read_eee_cap1()
816 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE. in genphy_c45_read_eee_cap1()
822 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap1()
827 linkmode_and(phydev->supported_eee, phydev->supported_eee, in genphy_c45_read_eee_cap1()
828 phydev->supported); in genphy_c45_read_eee_cap1()
834 * genphy_c45_read_eee_abilities - read supported EEE link modes
845 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_abilities()
852 phydev->supported)) { in genphy_c45_read_eee_abilities()
853 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register in genphy_c45_read_eee_abilities()
861 phydev->supported_eee, in genphy_c45_read_eee_abilities()
870 * genphy_c45_an_config_eee_aneg - configure EEE advertisement
875 if (!phydev->eee_enabled) { in genphy_c45_an_config_eee_aneg()
881 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); in genphy_c45_an_config_eee_aneg()
885 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA
888 * Read the supported link modes from the extended BASE-T1 ability register
899 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
903 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
907 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
915 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
923 * genphy_c45_pma_read_abilities - read supported link modes from PMA
926 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
928 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
930 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
937 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); in genphy_c45_pma_read_abilities()
938 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_pma_read_abilities()
945 phydev->supported); in genphy_c45_pma_read_abilities()
953 phydev->supported, in genphy_c45_pma_read_abilities()
957 phydev->supported, in genphy_c45_pma_read_abilities()
961 phydev->supported, in genphy_c45_pma_read_abilities()
970 phydev->supported, in genphy_c45_pma_read_abilities()
973 phydev->supported, in genphy_c45_pma_read_abilities()
976 phydev->supported, in genphy_c45_pma_read_abilities()
979 phydev->supported, in genphy_c45_pma_read_abilities()
982 phydev->supported, in genphy_c45_pma_read_abilities()
985 phydev->supported, in genphy_c45_pma_read_abilities()
989 phydev->supported, in genphy_c45_pma_read_abilities()
992 phydev->supported, in genphy_c45_pma_read_abilities()
996 phydev->supported, in genphy_c45_pma_read_abilities()
999 phydev->supported, in genphy_c45_pma_read_abilities()
1009 phydev->supported, in genphy_c45_pma_read_abilities()
1013 phydev->supported, in genphy_c45_pma_read_abilities()
1034 * The preference is read from the BIT(4) of BASE-T1 AN
1036 * is forced or not, it is read from BASE-T1 AN advertisement
1044 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_baset1_read_status()
1045 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_baset1_read_status()
1057 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_baset1_read_status()
1059 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_baset1_read_status()
1062 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; in genphy_c45_baset1_read_status()
1064 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; in genphy_c45_baset1_read_status()
1072 * genphy_c45_read_status - read PHY status
1075 * Reads status from PHY and sets phy_device members accordingly.
1085 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_status()
1086 phydev->duplex = DUPLEX_UNKNOWN; in genphy_c45_read_status()
1087 phydev->pause = 0; in genphy_c45_read_status()
1088 phydev->asym_pause = 0; in genphy_c45_read_status()
1090 if (phydev->autoneg == AUTONEG_ENABLE) { in genphy_c45_read_status()
1111 * genphy_c45_config_aneg - restart auto-negotiation or forced setup
1114 * Description: If auto-negotiation is enabled, we configure the
1115 * advertising, and then restart auto-negotiation. If it is not
1123 if (phydev->autoneg == AUTONEG_DISABLE) in genphy_c45_config_aneg()
1153 * genphy_c45_fast_retrain - configure fast retrain registers
1157 * Description: If fast-retrain is enabled, we configure PHY as
1170 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { in genphy_c45_fast_retrain()
1188 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers
1192 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1206 return -ENODEV; in genphy_c45_plca_get_cfg()
1208 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM; in genphy_c45_plca_get_cfg()
1214 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN); in genphy_c45_plca_get_cfg()
1220 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8; in genphy_c45_plca_get_cfg()
1221 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID); in genphy_c45_plca_get_cfg()
1227 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT; in genphy_c45_plca_get_cfg()
1233 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8; in genphy_c45_plca_get_cfg()
1234 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR); in genphy_c45_plca_get_cfg()
1241 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers
1243 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are
1246 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1256 // PLCA IDVER is read-only in genphy_c45_plca_set_cfg()
1257 if (plca_cfg->version >= 0) in genphy_c45_plca_set_cfg()
1258 return -EINVAL; in genphy_c45_plca_set_cfg()
1261 if (plca_cfg->enabled == 0) { in genphy_c45_plca_set_cfg()
1271 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) { in genphy_c45_plca_set_cfg()
1272 /* if one between node count and node ID is -not- to be in genphy_c45_plca_set_cfg()
1276 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) { in genphy_c45_plca_set_cfg()
1286 if (plca_cfg->node_cnt >= 0) in genphy_c45_plca_set_cfg()
1288 (plca_cfg->node_cnt << 8); in genphy_c45_plca_set_cfg()
1290 if (plca_cfg->node_id >= 0) in genphy_c45_plca_set_cfg()
1292 (plca_cfg->node_id); in genphy_c45_plca_set_cfg()
1301 if (plca_cfg->to_tmr >= 0) { in genphy_c45_plca_set_cfg()
1304 plca_cfg->to_tmr); in genphy_c45_plca_set_cfg()
1311 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) { in genphy_c45_plca_set_cfg()
1312 /* if one between burst count and burst timer is -not- to be in genphy_c45_plca_set_cfg()
1316 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) { in genphy_c45_plca_set_cfg()
1326 if (plca_cfg->burst_cnt >= 0) in genphy_c45_plca_set_cfg()
1328 (plca_cfg->burst_cnt << 8); in genphy_c45_plca_set_cfg()
1330 if (plca_cfg->burst_tmr >= 0) in genphy_c45_plca_set_cfg()
1332 (plca_cfg->burst_tmr); in genphy_c45_plca_set_cfg()
1342 if (plca_cfg->enabled > 0) { in genphy_c45_plca_set_cfg()
1356 * genphy_c45_plca_get_status - get PLCA status from standard registers
1360 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1373 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST); in genphy_c45_plca_get_status()
1379 * genphy_c45_eee_is_active - get EEE status
1385 * Description: this function will read local and link partner PHY
1408 eee_active = phy_check_valid(phydev->speed, phydev->duplex, in genphy_c45_eee_is_active()
1425 * genphy_c45_ethtool_get_eee - get EEE supported and status
1444 data->eee_enabled = is_enabled; in genphy_c45_ethtool_get_eee()
1445 data->eee_active = ret; in genphy_c45_ethtool_get_eee()
1447 if (!ethtool_convert_link_mode_to_legacy_u32(&data->supported, in genphy_c45_ethtool_get_eee()
1448 phydev->supported_eee)) in genphy_c45_ethtool_get_eee()
1450 if (!ethtool_convert_link_mode_to_legacy_u32(&data->advertised, adv)) in genphy_c45_ethtool_get_eee()
1452 if (!ethtool_convert_link_mode_to_legacy_u32(&data->lp_advertised, lp)) in genphy_c45_ethtool_get_eee()
1463 * genphy_c45_ethtool_set_eee - set EEE supported and status
1471 * non-destructive way.
1478 if (data->eee_enabled) { in genphy_c45_ethtool_set_eee()
1479 if (data->advertised) { in genphy_c45_ethtool_set_eee()
1483 data->advertised); in genphy_c45_ethtool_set_eee()
1484 linkmode_andnot(adv, adv, phydev->supported_eee); in genphy_c45_ethtool_set_eee()
1487 return -EINVAL; in genphy_c45_ethtool_set_eee()
1490 ethtool_convert_legacy_u32_to_link_mode(phydev->advertising_eee, in genphy_c45_ethtool_set_eee()
1491 data->advertised); in genphy_c45_ethtool_set_eee()
1493 linkmode_copy(phydev->advertising_eee, in genphy_c45_ethtool_set_eee()
1494 phydev->supported_eee); in genphy_c45_ethtool_set_eee()
1497 phydev->eee_enabled = true; in genphy_c45_ethtool_set_eee()
1499 phydev->eee_enabled = false; in genphy_c45_ethtool_set_eee()
1515 .name = "Generic Clause 45 PHY",