ethernet/xilinx/xilinx_axienet.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
147 #define XAE_IFGP_OFFSET		0x00000008 /* Tx Inter-frame gap adjustment*/
157 #define XAE_PPST_OFFSET		0x00000030 /* PCS PMA Soft Temac Status Reg */
201 /* Transmit inter-frame gap adjustment value */
217 #define XAE_INT_PHYRSTCMPLT_MASK	0x00000100 /* Phy Reset complete */
235 /* In-Band FCS enable (FCS not stripped) */
251 /* In-Band FCS enable (FCS not generated) */
255 /* Inter-frame gap adjustment enable */
277 #define XAE_PHYC_RGMIIHD_MASK		0x00000002 /* RGMII Half-duplex */
291 #define XAE_MDIO_MCR_PHYAD_MASK		0x1F000000 /* Phy Address Mask */
292 #define XAE_MDIO_MCR_PHYAD_SHIFT	24	   /* Phy Address Shift */
343 /* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */
348  * struct axidma_bd - Axi Dma buffer descriptor layout
383  * struct axienet_local - axienet private per device data
389  * @pcs_phy:	Reference to PCS/PMA PHY if used
390  * @pcs:	phylink pcs structure for PCS PHY
392  * @axi_clk:	AXI4-Lite bus clock
393  * @misc_clks:	Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
427  * @phy_mode:	Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
509  * struct axiethernet_option - Used to set axi ethernet hardware options
521  * axienet_ior - Memory mapped Axi Ethernet register read
531 	return ioread32(lp->regs + offset);  in axienet_ior()
541 	if (lp->mii_bus)  in axienet_lock_mii()
542 		mutex_lock(&lp->mii_bus->mdio_lock);  in axienet_lock_mii()
547 	if (lp->mii_bus)  in axienet_unlock_mii()
548 		mutex_unlock(&lp->mii_bus->mdio_lock);  in axienet_unlock_mii()
552  * axienet_iow - Memory mapped Axi Ethernet register write
563 	iowrite32(value, lp->regs + offset);  in axienet_iow()
567  * axienet_dma_out32 - Memory mapped Axi DMA register write.
579 	iowrite32(value, lp->dma_regs + reg);  in axienet_dma_out32()
584  * axienet_dma_out64 - Memory mapped Axi DMA register write.
595 	iowrite64(value, lp->dma_regs + reg);  in axienet_dma_out64()
601 	if (lp->features & XAE_FEATURE_DMA_64BIT)  in axienet_dma_out_addr()