Lines Matching +full:phy +full:- +full:pma
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
31 arm-pmu {
32 compatible = "arm,cortex-a57-pmu";
37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
43 compatible = "fixed-clock";
44 clock-output-names = "fin_pll";
45 #clock-cells = <0>;
49 #address-cells = <1>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a57";
56 enable-method = "psci";
57 i-cache-size = <0xc000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <256>;
63 next-level-cache = <&atlas_l2>;
68 compatible = "arm,cortex-a57";
70 enable-method = "psci";
71 i-cache-size = <0xc000>;
72 i-cache-line-size = <64>;
73 i-cache-sets = <256>;
74 d-cache-size = <0x8000>;
75 d-cache-line-size = <64>;
76 d-cache-sets = <256>;
77 next-level-cache = <&atlas_l2>;
82 compatible = "arm,cortex-a57";
84 enable-method = "psci";
85 i-cache-size = <0xc000>;
86 i-cache-line-size = <64>;
87 i-cache-sets = <256>;
88 d-cache-size = <0x8000>;
89 d-cache-line-size = <64>;
90 d-cache-sets = <256>;
91 next-level-cache = <&atlas_l2>;
96 compatible = "arm,cortex-a57";
98 enable-method = "psci";
99 i-cache-size = <0xc000>;
100 i-cache-line-size = <64>;
101 i-cache-sets = <256>;
102 d-cache-size = <0x8000>;
103 d-cache-line-size = <64>;
104 d-cache-sets = <256>;
105 next-level-cache = <&atlas_l2>;
108 atlas_l2: l2-cache0 {
110 cache-level = <2>;
111 cache-unified;
112 cache-size = <0x200000>;
113 cache-line-size = <64>;
114 cache-sets = <2048>;
126 compatible = "simple-bus";
127 #address-cells = <1>;
128 #size-cells = <1>;
132 compatible = "samsung,exynos4210-chipid";
136 gic: interrupt-controller@11001000 {
137 compatible = "arm,gic-400";
138 #interrupt-cells = <3>;
139 #address-cells = <0>;
140 interrupt-controller;
147 pdma0: dma-controller@10e10000 {
152 clock-names = "apb_pclk";
153 #dma-cells = <1>;
156 pdma1: dma-controller@10eb0000 {
161 clock-names = "apb_pclk";
162 #dma-cells = <1>;
165 clock_topc: clock-controller@10570000 {
166 compatible = "samsung,exynos7-clock-topc";
168 #clock-cells = <1>;
171 clock_top0: clock-controller@105d0000 {
172 compatible = "samsung,exynos7-clock-top0";
174 #clock-cells = <1>;
180 clock-names = "fin_pll", "dout_sclk_bus0_pll",
185 clock_top1: clock-controller@105e0000 {
186 compatible = "samsung,exynos7-clock-top1";
188 #clock-cells = <1>;
193 clock-names = "fin_pll", "dout_sclk_bus0_pll",
198 clock_ccore: clock-controller@105b0000 {
199 compatible = "samsung,exynos7-clock-ccore";
201 #clock-cells = <1>;
203 clock-names = "fin_pll", "dout_aclk_ccore_133";
206 clock_peric0: clock-controller@13610000 {
207 compatible = "samsung,exynos7-clock-peric0";
209 #clock-cells = <1>;
212 clock-names = "fin_pll", "dout_aclk_peric0_66",
216 clock_peric1: clock-controller@14c80000 {
217 compatible = "samsung,exynos7-clock-peric1";
219 #clock-cells = <1>;
233 clock-names = "fin_pll",
248 clock_peris: clock-controller@10040000 {
249 compatible = "samsung,exynos7-clock-peris";
251 #clock-cells = <1>;
253 clock-names = "fin_pll", "dout_aclk_peris_66";
256 clock_fsys0: clock-controller@10e90000 {
257 compatible = "samsung,exynos7-clock-fsys0";
259 #clock-cells = <1>;
262 clock-names = "fin_pll", "dout_aclk_fsys0_200",
266 clock_fsys1: clock-controller@156e0000 {
267 compatible = "samsung,exynos7-clock-fsys1";
269 #clock-cells = <1>;
276 clock-names = "fin_pll", "dout_aclk_fsys1_200",
283 compatible = "samsung,exynos4210-uart";
288 clock-names = "uart", "clk_uart_baud0";
293 compatible = "samsung,exynos4210-uart";
298 clock-names = "uart", "clk_uart_baud0";
303 compatible = "samsung,exynos4210-uart";
308 clock-names = "uart", "clk_uart_baud0";
313 compatible = "samsung,exynos4210-uart";
318 clock-names = "uart", "clk_uart_baud0";
323 compatible = "samsung,exynos7-pinctrl";
326 wakeup-interrupt-controller {
327 compatible = "samsung,exynos7-wakeup-eint";
328 interrupt-parent = <&gic>;
334 compatible = "samsung,exynos7-pinctrl";
340 compatible = "samsung,exynos7-pinctrl";
346 compatible = "samsung,exynos7-pinctrl";
352 compatible = "samsung,exynos7-pinctrl";
358 compatible = "samsung,exynos7-pinctrl";
364 compatible = "samsung,exynos7-pinctrl";
370 compatible = "samsung,exynos7-pinctrl";
376 compatible = "samsung,exynos7-pinctrl";
382 compatible = "samsung,exynos7-hsi2c";
385 #address-cells = <1>;
386 #size-cells = <0>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&hs_i2c0_bus>;
390 clock-names = "hsi2c";
395 compatible = "samsung,exynos7-hsi2c";
398 #address-cells = <1>;
399 #size-cells = <0>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&hs_i2c1_bus>;
403 clock-names = "hsi2c";
408 compatible = "samsung,exynos7-hsi2c";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&hs_i2c2_bus>;
416 clock-names = "hsi2c";
421 compatible = "samsung,exynos7-hsi2c";
424 #address-cells = <1>;
425 #size-cells = <0>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&hs_i2c3_bus>;
429 clock-names = "hsi2c";
434 compatible = "samsung,exynos7-hsi2c";
437 #address-cells = <1>;
438 #size-cells = <0>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&hs_i2c4_bus>;
442 clock-names = "hsi2c";
447 compatible = "samsung,exynos7-hsi2c";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&hs_i2c5_bus>;
455 clock-names = "hsi2c";
460 compatible = "samsung,exynos7-hsi2c";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&hs_i2c6_bus>;
468 clock-names = "hsi2c";
473 compatible = "samsung,exynos7-hsi2c";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&hs_i2c7_bus>;
481 clock-names = "hsi2c";
486 compatible = "samsung,exynos7-hsi2c";
489 #address-cells = <1>;
490 #size-cells = <0>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&hs_i2c8_bus>;
494 clock-names = "hsi2c";
499 compatible = "samsung,exynos7-hsi2c";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&hs_i2c9_bus>;
507 clock-names = "hsi2c";
512 compatible = "samsung,exynos7-hsi2c";
515 #address-cells = <1>;
516 #size-cells = <0>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&hs_i2c10_bus>;
520 clock-names = "hsi2c";
525 compatible = "samsung,exynos7-hsi2c";
528 #address-cells = <1>;
529 #size-cells = <0>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&hs_i2c11_bus>;
533 clock-names = "hsi2c";
537 pmu_system_controller: system-controller@105c0000 {
538 compatible = "samsung,exynos7-pmu", "syscon";
543 compatible = "samsung,s3c6410-rtc";
548 clock-names = "rtc";
553 compatible = "samsung,exynos7-wdt";
557 clock-names = "watchdog";
558 samsung,syscon-phandle = <&pmu_system_controller>;
563 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
568 interrupt-names = "job", "mmu", "gpu";
574 compatible = "samsung,exynos7-dw-mshc-smu";
576 #address-cells = <1>;
577 #size-cells = <0>;
581 clock-names = "biu", "ciu";
582 fifo-depth = <0x40>;
587 compatible = "samsung,exynos7-dw-mshc";
589 #address-cells = <1>;
590 #size-cells = <0>;
594 clock-names = "biu", "ciu";
595 fifo-depth = <0x40>;
600 compatible = "samsung,exynos7-dw-mshc-smu";
602 #address-cells = <1>;
603 #size-cells = <0>;
607 clock-names = "biu", "ciu";
608 fifo-depth = <0x40>;
613 compatible = "samsung,exynos7-adc";
617 clock-names = "adc";
618 #io-channel-cells = <1>;
623 compatible = "samsung,exynos4210-pwm";
630 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
631 #pwm-cells = <3>;
633 clock-names = "timers";
637 compatible = "samsung,exynos7-tmu";
642 clock-names = "tmu_apbif", "tmu_sclk";
643 #thermal-sensor-cells = <0>;
647 compatible = "samsung,exynos7-ufs";
652 reg-names = "hci", "vs_hci", "unipro", "ufsp";
656 clock-names = "core_clk", "sclk_unipro_main";
657 freq-table-hz = <0 0>, <0 0>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
661 phy-names = "ufs-phy";
665 ufs_phy: ufs-phy@15571800 {
666 compatible = "samsung,exynos7-ufs-phy";
668 reg-names = "phy-pma";
669 samsung,pmu-syscon = <&pmu_system_controller>;
670 #phy-cells = <0>;
675 clock-names = "ref_clk", "rx1_symbol_clk",
680 usbdrd_phy: phy@15500000 {
681 compatible = "samsung,exynos7-usbdrd-phy";
688 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
689 samsung,pmu-syscon = <&pmu_system_controller>;
690 #phy-cells = <1>;
694 compatible = "samsung,exynos7-dwusb3";
698 clock-names = "usbdrd30", "usbdrd30_susp_clk",
700 #address-cells = <1>;
701 #size-cells = <1>;
709 phy-names = "usb2-phy", "usb3-phy";
714 thermal-zones {
715 atlas_thermal: cluster0-thermal {
716 polling-delay-passive = <0>; /* milliseconds */
717 polling-delay = <0>; /* milliseconds */
718 thermal-sensors = <&tmuctrl_0>;
719 #include "exynos7-trip-points.dtsi"
724 compatible = "arm,armv8-timer";
736 #include "exynos7-pinctrl.dtsi"
737 #include "arm/samsung/exynos-syscon-restart.dtsi"