| /openbmc/linux/drivers/pci/controller/ |
| H A D | pcie-rcar-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
16 #include <linux/clk-provider.h>
33 #include "pcie-rcar.h"
44 /* Structure representing the PCIe interface */
46 struct rcar_pcie pcie; member
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
7 tristate "Aardvark PCIe controller"
13 Add support for Aardvark 64bit PCIe Host Controller. This
18 tristate "Altera PCIe controller"
21 Say Y here if you want to enable PCIe controller support on Altera
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
38 tristate "Apple PCIe controller"
44 Say Y here if you want to enable PCIe controller support on Apple
45 system-on-chips, like the Apple M1. This is required for the USB
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| H A D | pcie-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
35 /* MediaTek-specific configuration registers */
40 /* Host-PCI bridge registers */
48 /* PCIe RC control registers */
67 * struct mt7621_pcie_port - PCIe port information
70 * @pcie: pointer to PCIe host info
81 struct mt7621_pcie *pcie; member
91 * struct mt7621_pcie - PCIe host information
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| H A D | pcie-mediatek.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
32 /* PCIe shared registers */
38 /* PCIe per port registers */
44 #define PCIE_PORT_PERST(x) BIT(1 + (x))
69 /* PCIe V2 share registers */
72 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
74 /* PCIe V2 per-port registers */
97 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
103 /* PCIe V2 configuration transaction header */
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| H A D | pcie-rcar.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
12 #include "pcie-rcar.h"
14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
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| H A D | pcie-mediatek-gen3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
43 #define PCIE_PHY_RSTB BIT(1)
61 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
65 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
69 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
83 #define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
95 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
98 #define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
104 * struct mtk_msi_set - MSI information for each set
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| H A D | pcie-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
28 #define EP_MODE_SURVIVE_PERST_SHIFT 1
43 #define CFG_ADDR_CFG_TYPE_1 1
56 #define CFG_RD_UR 1
73 #define OARR_SIZE_CFG_SHIFT 1
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | mvebu-gated-clock.txt | 12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
16 3 ge1 Gigabit Ethernet 1
18 5 pex0 PCIe Cntrl 0
19 9 pex1 PCIe Cntrl 1
20 15 sata0 SATA Host 0
21 17 sdio SDHCI Host
25 30 sata1 SATA Host 0
29 -----------------------------------
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: cdns-pcie-host.yaml#
19 - const: ti,j721e-pcie-host
20 - description: PCIe controller in AM64
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| H A D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PCI host controller
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
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| H A D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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| H A D | apple,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple PCIe host controller
10 - Mark Kettenis <kettenis@openbsd.org>
13 The Apple PCIe host controller is a PCIe host controller with
16 The controller incorporates Synopsys DesigWare PCIe logic to
18 PCIe host bridges is absent.
22 the standard "reset-gpios" and "max-link-speed" properties appear on
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| H A D | pcie-al.txt | 1 * Amazon Annapurna Labs PCIe host bridge
3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
5 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
7 Properties of the host controller node that differ from it are:
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
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| H A D | microchip,pcie-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PCIe Root Port Bridge Controller
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: microchip,pcie-host-1.0 # PolarFire
23 reg-names:
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| /openbmc/qemu/docs/config/ |
| H A D | mach-virt-serial.cfg | 1 # mach-virt - VirtIO guest (serial console)
6 # $ qemu-system-aarch64 \
7 # -nodefaults \
8 # -readconfig mach-virt-serial.cfg \
9 # -display none -serial mon:stdio \
10 # -cpu host
19 # ---------------------------------------------------------
21 # Using -nodefaults is required to have full control over
29 # 00:00.0 Host bridge
40 # We use '-display none' to prevent QEMU from creating a
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| H A D | mach-virt-graphical.cfg | 1 # mach-virt - VirtIO guest (graphical console)
6 # $ qemu-system-aarch64 \
7 # -nodefaults \
8 # -readconfig mach-virt-graphical.cfg \
9 # -cpu host
18 # ---------------------------------------------------------
20 # Using -nodefaults is required to have full control over
28 # 00:00.0 Host bridge
48 # Using less than 1 GiB of memory is probably not going to
55 # same GIC version as the host.
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| H A D | q35-virtio-graphical.cfg | 1 # q35 - VirtIO guest (graphical console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-virtio-graphical.cfg
17 # ---------------------------------------------------------
19 # Using -nodefaults is required to have full control over
28 # 00:00.0 Host bridge
29 # 00:1f.0 ISA bridge / LPC
30 # 00:1f.2 SATA (AHCI) controller
31 # 00:1f.3 SMBus controller
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| H A D | q35-virtio-serial.cfg | 1 # q35 - VirtIO guest (serial console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-virtio-serial.cfg \
9 # -display none -serial mon:stdio
18 # ---------------------------------------------------------
20 # Using -nodefaults is required to have full control over
29 # 00:00.0 Host bridge
30 # 00:1f.0 ISA bridge / LPC
31 # 00:1f.2 SATA (AHCI) controller
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| H A D | q35-emulated.cfg | 1 # q35 - Emulated guest (graphical console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-emulated.cfg
17 # ---------------------------------------------------------
19 # Using -nodefaults is required to have full control over
28 # 00:00.0 Host bridge
29 # 00:1f.0 ISA bridge / LPC
30 # 00:1f.2 SATA (AHCI) controller
31 # 00:1f.3 SMBus controller
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| /openbmc/qemu/docs/ |
| H A D | bypass-iommu.txt | 10 passthrough devices with no-iommu mode and devices go through vIOMMU in
13 PCI host bridges have a bypass_iommu property. This property is used to
14 determine whether the devices attached on the PCI host bridge will bypass
17 bypass vIOMMU. When bypass_iommu property is not set for a host bridge,
22 The bypass iommu feature support PXB host bridge and default main host
29 1. The following is the bypass iommu options:
30 (1) PCI expander bridge
31 qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
32 (2) Arm default host bridge
33 qemu -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true
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| /openbmc/linux/Documentation/admin-guide/ |
| H A D | thunderbolt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 manager is an entity running on the host router (host controller)
19 ``user`` which means PCIe tunneling is disabled by default. The
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
37 ACTION=="add", SUBSYSTEM=="thunderbolt", ATTR{authorized}=="0", ATTR{authorized}="1"
46 be DMA masters and thus read contents of the host memory without CPU and OS
50 Some USB4 systems have a BIOS setting to disable PCIe tunneling. This is
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| /openbmc/qemu/docs/specs/ |
| H A D | pci-ids.rst | 6 virtual devices. The vendor IDs are 1af4 (formerly Qumranet ID) and 1b36.
11 1af4 vendor ID
12 --------------
14 The 1000 -> 10ff device ID range is used as follows for virtio-pci devices.
18 1af4:1000
20 1af4:1001
22 1af4:1002
24 1af4:1003
26 1af4:1004
27 SCSI host bus adapter device (legacy)
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| /openbmc/linux/Documentation/misc-devices/ |
| H A D | spear-pcie-gadget.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Spear PCIe Gadget Driver
24 PCIe gadget support for SPEAr13XX platform
29 Its main purpose is to configure selected dual mode PCIe controller as device
31 type. This driver can be used to show spear's PCIe device capability.
37 -----------------------
42 no_of_msi zero if MSI is not enabled by host. A positive value is the
53 ------------------------
61 inta write 1 to assert INTA and 0 to de-assert.
78 Program all PCIe registers in such a way that when this device is connected
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