qemu/docs/bypass-iommu.txt

10 passthrough devices with no-iommu mode and devices go through vIOMMU in
13 PCI host bridges have a bypass_iommu property. This property is used to
14 determine whether the devices attached on the PCI host bridge will bypass
17 bypass vIOMMU. When bypass_iommu property is not set for a host bridge,
22 The bypass iommu feature support PXB host bridge and default main host
29 1. The following is the bypass iommu options:
30  (1) PCI expander bridge
31      qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
32  (2) Arm default host bridge
33      qemu -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true
35      qemu -machine q35,default_bus_bypass_iommu=true
40 qemu-system-aarch64 \
41  -machine virt,kernel_irqchip=on,iommu=smmuv3,default_bus_bypass_iommu=true \
42  -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3.0x1 \
43  -device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x3.0x2,bypass_iommu=true \
46  - a default host bridge which bypass SMMUv3
47  - a pxb host bridge which go through SMMUv3
48  - a pxb host bridge which bypass SMMUv3
53 qemu-system-x86_64 \
54  -machine q35,accel=kvm,default_bus_bypass_iommu=true \
55  -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3 \
56  -device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x4,bypass_iommu=true \
57  -device intel-iommu \
60  - a default host bridge which bypass iommu
61  - a pxb host bridge which go through iommu
62  - a pxb host bridge which bypass iommu
74  - Address space
75    Add bypass iommu property check of PCI Host and do not get iommu address
77  - Arm SMMUv3 support
80  - X86 IOMMU support
81    To support Intel iommu, we traverse all PCI host bridge and get information
85  - Machine and PXB options