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/openbmc/linux/drivers/nvmem/
H A Drockchip-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip OTP Driver
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
41 #define OTPC_SBPI_DONE BIT(1)
64 #define RK3588_BURST_NUM 1
68 #define RK3588_RD_DONE BIT(1)
85 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
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H A Dlan9662-otpc.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/nvmem-provider.h>
18 #define OTP_OTP_FUNC_CMD_OTP_PROGRAM BIT(1)
27 #define OTP_OTP_STATUS_OTP_CPUMPEN BIT(1)
47 static int lan9662_otp_power(struct lan9662_otp *otp, bool up) in lan9662_otp_power() argument
49 void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); in lan9662_otp_power()
53 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_power()
55 return -ETIMEDOUT; in lan9662_otp_power()
63 static int lan9662_otp_execute(struct lan9662_otp *otp) in lan9662_otp_execute() argument
65 if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), in lan9662_otp_execute()
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H A Dsunplus-ocotp.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-provider.h>
21 * OTP memory
48 #define OTP_LOAD_SECURE_DATA BIT(1)
49 #define OTP_LOAD_SECURE_DATA_MASK ~BIT(1)
78 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
94 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
95 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
96 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
97 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
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H A Dmxs-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MXS On-Chip OTP driver
15 #include <linux/nvmem-provider.h>
36 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
41 while (timeout--) { in mxs_ocotp_wait()
42 status = readl(otp->base); in mxs_ocotp_wait()
51 return -EBUSY; in mxs_ocotp_wait()
53 return -EIO; in mxs_ocotp_wait()
61 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
65 ret = clk_enable(otp->clk); in mxs_ocotp_read()
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H A Dlpc18xx_otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * NXP LPC18xx/43xx OTP memory NVMEM driver
10 * TODO: add support for writing OTP register via API in boot ROM.
15 #include <linux/nvmem-provider.h>
21 * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
26 * Bank 1/2 is generale purpose or AES key storage for secure devices.
43 struct lpc18xx_otp *otp = context; in lpc18xx_otp_read() local
49 if (count > (LPC18XX_OTP_SIZE - index)) in lpc18xx_otp_read()
50 count = LPC18XX_OTP_SIZE - index; in lpc18xx_otp_read()
53 *buf++ = readl(otp->base + i * LPC18XX_OTP_WORD_SIZE); in lpc18xx_otp_read()
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H A Dnintendo-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Nintendo Wii and Wii U OTP driver
5 * This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
7 * This memory contains common and per-console keys, signatures and
10 * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware/OTP
19 #include <linux/nvmem-provider.h>
39 .name = "wii-otp",
40 .num_banks = 1,
44 .name = "wiiu-otp",
56 while (words--) { in nintendo_otp_reg_read()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
37 calibration data required for the PCIe or the USB-C PHY.
40 be called nvmem-apple-efuses.
43 tristate "Broadcom On-Chip OTP Controller support"
48 Say y here to enable read/write access to the Broadcom OTP
52 will be called nvmem-bcm-ocotp.
72 will be called nvmem-imx-iim.
75 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
79 This is a driver for the On-Chip OTP Controller (OCOTP) available on
80 i.MX6 SoCs, providing access to 4 Kbits of one-time programmable
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H A Dimx-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
21 #include <linux/nvmem-provider.h>
28 * OTP Bank0 Word0
31 * of two consecutive OTP words.
106 void __iomem *base = priv->base; in imx_ocotp_wait_for_busy()
108 bm_ctrl_busy = priv->params->ctrl.bm_busy; in imx_ocotp_wait_for_busy()
109 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_wait_for_busy()
113 for (count = 10000; count >= 0; count--) { in imx_ocotp_wait_for_busy()
123 * - A write is performed to a shadow register during a shadow in imx_ocotp_wait_for_busy()
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/openbmc/u-boot/arch/arm/mach-stm32mp/
H A Dbsec.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
25 #define BSEC_SWLOCK_OFF 0x07C /* write in OTP sticky lock */
47 * OTP Lock services definition
53 * bsec_check_error() - Check status of one otp
55 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
56 * Return: 0 if no error, -EAGAIN or -ENOTSUPP
58 static u32 bsec_check_error(u32 base, u32 otp) in bsec_check_error() argument
63 bit = 1 << (otp & OTP_LOCK_MASK); in bsec_check_error()
64 bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); in bsec_check_error()
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H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
48 * - boot instance = bit 31:16
49 * - boot device = bit 15:0
57 /* BSEC OTP index */
93 * bit 1 / 17 => nsaid1 read/write Enable in security_init()
99 /* bit 0 / 1 => Region Enable for filter 0/1 */ in security_init()
100 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); in security_init()
102 /* Enable Filter 0 and 1 */ in security_init()
103 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); in security_init()
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/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Drockchip,otp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3588-otp
20 maxItems: 1
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H A Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
7 - reg: Must contain an entry with the physical base address and length
8 for each entry in reg-names.
9 - address-cells: must be set to 1.
10 - size-cells: must be set to 1.
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
18 #address-cells = <1>;
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H A Dnintendo-otp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
11 which contains common and per-console keys, signatures and related data
14 See https://wiiubrew.org/wiki/Hardware/OTP
17 - Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
20 - $ref: nvmem.yaml#
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H A Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
24 - st,stm32f4-otp
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-eeprom-read.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
9 #include "iwl-drv.h"
10 #include "iwl-debug.h"
11 #include "iwl-eeprom-read.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
19 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
22 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 User-defined MTD device name. Can be used to assign user friendly
24 '#address-cells':
27 '#size-cells':
34 - compatible
37 "@[0-9a-f]+$":
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/openbmc/openbmc/meta-aspeed/classes/
H A Dotptool.bbclass2 # to create OTP image
9 OTPTOOL_EXTRA_DEPENDS ?= " socsec-native"
10 DEPENDS += '${@oe.utils.conditional("SOCSEC_SIGN_ENABLE", "1", "${OTPTOOL_EXTRA_DEPENDS}", "", d)}'
13 local otptool_config=$1
16 …otptool_user_folder="$([ -n "${OTPTOOL_USER_DIR}" ] && echo --user_data_folder ${OTPTOOL_USER_DIR}…
17 mkdir -p "${otptool_config_outdir}"
19 --key_folder ${OTPTOOL_KEY_DIR} \
20 --output_folder "${otptool_config_outdir}" \
25 if [ $? -ne 0 ]; then
26 bbfatal "Generated OTP image failed."
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Deeprom.c1 // SPDX-License-Identifier: ISC
25 return -ETIMEDOUT; in mt7615_efuse_read()
50 if (is_mt7663(&dev->mt76)) in mt7615_efuse_init()
57 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
58 dev->mt76.otp.size = len; in mt7615_efuse_init()
59 if (!dev->mt76.otp.data) in mt7615_efuse_init()
60 return -ENOMEM; in mt7615_efuse_init()
62 buf = dev->mt76.otp.data; in mt7615_efuse_init()
80 ret = mt76_eeprom_init(&dev->mt76, MT7615_EEPROM_FULL_SIZE); in mt7615_eeprom_load()
89 u16 val = get_unaligned_le16(dev->eeprom.data); in mt7615_check_eeprom()
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/openbmc/qemu/hw/nvram/
H A Dnpcm7xx_otp.c2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
30 /* 32-bit register indices. */
45 #define FST_RDST BIT(1)
62 * struct NPCM7xxOTPClass - OTP module class.
66 * The two OTP modules (key-storage and fuse-array) have slightly different
84 result |= (((n >> 0) & 1) ^ ((n >> 1) & 1)) << 4; in ecc_encode_nibble()
85 result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5; in ecc_encode_nibble()
86 result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6; in ecc_encode_nibble()
87 result |= (((n >> 1) & 1) ^ ((n >> 3) & 1)) << 7; in ecc_encode_nibble()
96 uint8_t *dst = &s->array[offset]; in npcm7xx_otp_array_write()
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H A Dbcm2835_otp.c2 * BCM2835 One-Time Programmable (OTP) Memory
4 * The OTP implementation is mostly a stub except for the OTP rows
7 * The OTP registers are unimplemented due to lack of documentation.
11 * SPDX-License-Identifier: MIT
19 /* OTP rows are 1-indexed */
22 assert(row <= BCM2835_OTP_ROW_COUNT && row >= 1); in bcm2835_otp_get_row()
24 return s->otp_rows[row - 1]; in bcm2835_otp_get_row()
30 assert(row <= BCM2835_OTP_ROW_COUNT && row >= 1); in bcm2835_otp_set_row()
32 /* Real OTP rows work as e-fuses */ in bcm2835_otp_set_row()
33 s->otp_rows[row - 1] |= value; in bcm2835_otp_set_row()
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/openbmc/linux/drivers/mtd/spi-nor/
H A Dotp.c1 // SPDX-License-Identifier: GPL-2.0
3 * OTP support for SPI NOR flashes
10 #include <linux/mtd/spi-nor.h>
14 #define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len)
15 #define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions)
18 * spi_nor_otp_read_secr() - read security register
27 * an one-time-programmable memory area, consisting of multiple bytes (usually
28 * 256). Thus one "security register" maps to one OTP region.
34 * Return: number of bytes read successfully, -errno otherwise
43 read_opcode = nor->read_opcode; in spi_nor_otp_read_secr()
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Deeprom.c1 // SPDX-License-Identifier: ISC
21 return -ETIMEDOUT; in mt7603_efuse_read()
51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
54 return -ENOMEM; in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
100 MT_EE_TX_POWER_0_START_2G + 1, in mt7603_apply_cal_free_data()
102 MT_EE_TX_POWER_1_START_2G + 1, in mt7603_apply_cal_free_data()
104 struct device_node *np = dev->mt76.dev->of_node; in mt7603_apply_cal_free_data()
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/openbmc/linux/include/linux/mfd/wm831x/
H A Dotp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
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/openbmc/u-boot/board/imgtec/ci20/
H A Dci20.c1 // SPDX-License-Identifier: GPL-2.0+
59 writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); in ci20_mux_eth()
60 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); in ci20_mux_eth()
61 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); in ci20_mux_eth()
62 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); in ci20_mux_eth()
63 writel(0x00000003, gpio_regs + GPIO_PXPENS(1)); in ci20_mux_eth()
90 writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); in ci20_mux_nand()
91 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); in ci20_mux_nand()
92 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); in ci20_mux_nand()
93 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); in ci20_mux_nand()
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/openbmc/u-boot/cmd/
H A Dotp.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <u-boot/sha256.h>
20 #include <u-boot/sha512.h>
21 #include <u-boot/rsa.h>
22 #include <u-boot/rsa-mod-exp.h>
33 #define OTP_REGION_CONF BIT(1)
36 #define OTP_USAGE -1
37 #define OTP_FAILURE -2
40 #define OTP_PROG_SKIP 1
42 #define OTP_KEY_TYPE_RSA_PUB 1
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