1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3  * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
9 #include "iwl-drv.h"
10 #include "iwl-debug.h"
11 #include "iwl-eeprom-read.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
19  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
22  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
52 			IWL_DEBUG_EEPROM(trans->dev,  in iwl_eeprom_acquire_semaphore()
54 					 count+1);  in iwl_eeprom_acquire_semaphore()
72 	IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);  in iwl_eeprom_verify_signature()
79 			return -ENOENT;  in iwl_eeprom_verify_signature()
85 			IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);  in iwl_eeprom_verify_signature()
86 			return -ENOENT;  in iwl_eeprom_verify_signature()
92 			"bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n",  in iwl_eeprom_verify_signature()
93 			nvm_is_otp ? "OTP" : "EEPROM", gp);  in iwl_eeprom_verify_signature()
94 		return -ENOENT;  in iwl_eeprom_verify_signature()
100  * OTP related functions
116 	/* OTP only valid for CP/PP and after */  in iwl_nvm_is_otp()
117 	switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {  in iwl_nvm_is_otp()
120 		return -EIO;  in iwl_nvm_is_otp()
129 			return 1;  in iwl_nvm_is_otp()
149 	 * CSR auto clock gate disable bit -  in iwl_init_otp_access()
150 	 * this is only applicable for HW with OTP shadow RAM  in iwl_init_otp_access()
152 	if (trans->trans_cfg->base_params->shadow_ram_support)  in iwl_init_otp_access()
167 		    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));  in iwl_read_otp_word()
173 		IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);  in iwl_read_otp_word()
181 		/* set the uncorrectable OTP ECC bit for acknowledgment */  in iwl_read_otp_word()
184 		IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");  in iwl_read_otp_word()
185 		return -EINVAL;  in iwl_read_otp_word()
189 		/* set the correctable OTP ECC bit for acknowledgment */  in iwl_read_otp_word()
192 		IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");  in iwl_read_otp_word()
199  * iwl_is_otp_empty: check for empty OTP
207 	/* locate the beginning of OTP link list */  in iwl_is_otp_empty()
210 			IWL_ERR(trans, "OTP is empty\n");  in iwl_is_otp_empty()
214 		IWL_ERR(trans, "Unable to read first block of OTP list.\n");  in iwl_is_otp_empty()
223  * iwl_find_otp_image: find EEPROM image in OTP
224  *   finding the OTP block that contains the EEPROM image.
227  *   If all the available OTP blocks are full, the last block will be the block
241 	/* checking for empty OTP or error */  in iwl_find_otp_image()
243 		return -EINVAL;  in iwl_find_otp_image()
247 	 * until reach the max number of OTP blocks  in iwl_find_otp_image()
248 	 * different devices have different number of OTP blocks  in iwl_find_otp_image()
256 		IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",  in iwl_find_otp_image()
259 			return -EINVAL;  in iwl_find_otp_image()
273 	} while (usedblocks <= trans->trans_cfg->base_params->max_ll_items);  in iwl_find_otp_image()
275 	/* OTP has no valid blocks */  in iwl_find_otp_image()
276 	IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");  in iwl_find_otp_image()
277 	return -EINVAL;  in iwl_find_otp_image()
281  * iwl_read_eeprom - read EEPROM contents
286  * NOTE:  This routine uses the non-debug IO access functions.
300 		return -EINVAL;  in iwl_read_eeprom()
306 	sz = trans->trans_cfg->base_params->eeprom_size;  in iwl_read_eeprom()
307 	IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);  in iwl_read_eeprom()
311 		return -ENOMEM;  in iwl_read_eeprom()
329 			IWL_ERR(trans, "Failed to initialize OTP access.\n");  in iwl_read_eeprom()
341 		if (!trans->trans_cfg->base_params->shadow_ram_support) {  in iwl_read_eeprom()
362 				    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));  in iwl_read_eeprom()
378 	IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",  in iwl_read_eeprom()
379 			 nvm_is_otp ? "OTP" : "EEPROM");  in iwl_read_eeprom()