Lines Matching +full:otp +full:- +full:1
2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
30 /* 32-bit register indices. */
45 #define FST_RDST BIT(1)
62 * struct NPCM7xxOTPClass - OTP module class.
66 * The two OTP modules (key-storage and fuse-array) have slightly different
84 result |= (((n >> 0) & 1) ^ ((n >> 1) & 1)) << 4; in ecc_encode_nibble()
85 result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5; in ecc_encode_nibble()
86 result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6; in ecc_encode_nibble()
87 result |= (((n >> 1) & 1) ^ ((n >> 3) & 1)) << 7; in ecc_encode_nibble()
96 uint8_t *dst = &s->array[offset]; in npcm7xx_otp_array_write()
98 while (len-- > 0) { in npcm7xx_otp_array_write()
106 /* Common register read handler for both OTP classes. */
116 value = s->regs[reg]; in npcm7xx_otp_read()
121 "%s: read from write-only FCTL register\n", in npcm7xx_otp_read()
122 DEVICE(s)->canonical_path); in npcm7xx_otp_read()
127 DEVICE(s)->canonical_path, reg * sizeof(uint32_t)); in npcm7xx_otp_read()
134 /* Read a byte from the OTP array into the data register. */
137 uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR]; in npcm7xx_otp_read_array()
139 s->regs[NPCM7XX_OTP_FDATA] = s->array[FADDR_BYTEADDR(faddr)]; in npcm7xx_otp_read_array()
140 s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY; in npcm7xx_otp_read_array()
143 /* Program a byte from the data register into the OTP array. */
146 uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR]; in npcm7xx_otp_program_array()
148 /* Bits can only go 0->1, never 1->0. */ in npcm7xx_otp_program_array()
149 s->array[FADDR_BYTEADDR(faddr)] |= (1U << FADDR_BITPOS(faddr)); in npcm7xx_otp_program_array()
150 s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY; in npcm7xx_otp_program_array()
161 * and FRDLK (0..7) that are read-only. in npcm7xx_otp_compute_fcfg()
165 /* FDIS and FCFGLK bits are sticky (write 1 to set; can't clear). */ in npcm7xx_otp_compute_fcfg()
167 /* Preserve read-only bits in FPRGLK and FRDLK */ in npcm7xx_otp_compute_fcfg()
169 /* Set all bits that aren't read-only. */ in npcm7xx_otp_compute_fcfg()
175 /* Common register write handler for both OTP classes. */
181 /* RDST is cleared by writing 1 to it. */ in npcm7xx_otp_write()
183 s->regs[NPCM7XX_OTP_FST] &= ~FST_RDST; in npcm7xx_otp_write()
185 /* Preserve read-only and write-one-to-clear bits */ in npcm7xx_otp_write()
187 value |= s->regs[NPCM7XX_OTP_FST] & FST_RO_MASK; in npcm7xx_otp_write()
201 value = s->regs[NPCM7XX_OTP_FDATA]; in npcm7xx_otp_write()
206 value = npcm7xx_otp_compute_fcfg(s->regs[NPCM7XX_OTP_FCFG], value); in npcm7xx_otp_write()
228 if (s->regs[NPCM7XX_OTP_FCTL] == FCTL_PROG_CMD1) { in npcm7xx_otp_write()
236 DEVICE(s)->canonical_path, value); in npcm7xx_otp_write()
246 DEVICE(s)->canonical_path, reg * sizeof(uint32_t)); in npcm7xx_otp_write()
250 s->regs[reg] = value; in npcm7xx_otp_write()
253 /* Register read handler specific to the fuse array OTP module. */
263 * work the same way for both kinds of OTP modules. in npcm7xx_fuse_array_read()
268 /* FUSTRAP is stored as three copies in the OTP array. */ in npcm7xx_fuse_array_read()
271 memcpy(fustrap, &s->array[0], sizeof(fustrap)); in npcm7xx_fuse_array_read()
274 value = (fustrap[0] & fustrap[1]) | (fustrap[0] & fustrap[2]) | in npcm7xx_fuse_array_read()
275 (fustrap[1] & fustrap[2]); in npcm7xx_fuse_array_read()
281 /* Register write handler specific to the fuse array OTP module. */
289 * The Fuse Strap register is read-only. Other registers are handled by in npcm7xx_fuse_array_write()
308 /* Register read handler specific to the key storage OTP module. */
317 * registers work the same way for both kinds of OTP modules. in npcm7xx_key_storage_read()
325 return s->regs[NPCM7XX_OTP_FKEYIND]; in npcm7xx_key_storage_read()
328 /* Register write handler specific to the key storage OTP module. */
337 * registers work the same way for both kinds of OTP modules. in npcm7xx_key_storage_write()
346 s->regs[NPCM7XX_OTP_FKEYIND] = v; in npcm7xx_key_storage_write()
364 memset(s->regs, 0, sizeof(s->regs)); in npcm7xx_otp_enter_reset()
366 s->regs[NPCM7XX_OTP_FST] = 0x00000001; in npcm7xx_otp_enter_reset()
367 s->regs[NPCM7XX_OTP_FCFG] = 0x20000000; in npcm7xx_otp_enter_reset()
376 memset(s->array, 0, sizeof(s->array)); in npcm7xx_otp_realize()
378 memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs", in npcm7xx_otp_realize()
380 sysbus_init_mmio(sbd, &s->mmio); in npcm7xx_otp_realize()
384 .name = "npcm7xx-otp",
401 dc->realize = npcm7xx_otp_realize; in npcm7xx_otp_class_init()
402 dc->vmsd = &vmstate_npcm7xx_otp; in npcm7xx_otp_class_init()
403 rc->phases.enter = npcm7xx_otp_enter_reset; in npcm7xx_otp_class_init()
410 oc->mmio_ops = &npcm7xx_key_storage_ops; in npcm7xx_key_storage_class_init()
417 oc->mmio_ops = &npcm7xx_fuse_array_ops; in npcm7xx_fuse_array_class_init()