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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
4 $id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
13 The Ocelot ethernet switch family contains chips that have an internal CPU
18 The switch family is a multi-port networking switch that supports many
25 - mscc,vsc7512
30 "#address-cells":
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/openbmc/u-boot/arch/mips/dts/
H A Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 model = "Ocelot PCB120 Reference Board";
11 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
14 stdout-path = "serial0:115200n8";
17 gpio-leds {
18 compatible = "gpio-leds";
22 gpios = <&sgpio 44 1>; /* p12.1 */
23 default-state = "off";
28 gpios = <&sgpio 12 1>; /* p12.0 */
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H A Docelot_pcb123.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 model = "Ocelot PCB123 Reference Board";
11 compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
14 stdout-path = "serial0:115200n8";
17 gpio-leds {
18 compatible = "gpio-leds";
22 gpios = <&sgpio 43 1>; /* p11.1 */
23 default-state = "on";
28 gpios = <&sgpio 11 1>; /* p11.0 */
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H A Dmscc,jr2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
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H A Dmscc,ocelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "mscc,ocelot";
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
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H A Dmscc,servalt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
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/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dmscc_sgpio.txt10 - compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
11 - clock: Reference clock used to generate clock divider setting. See
12 mscc,sgpio-frequency property.
13 - reg : Physical base address and length of the controller's registers.
14 - #gpio-cells : Should be two. The first cell is the pin number and the
16 - bit 0 specifies polarity (0 for normal, 1 for inverted)
17 - gpio-controller : Marks the device node as a GPIO controller.
18 - gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base
22 - ngpios: See gpio.txt
23 - mscc,sgpio-frequency: The frequency at which the serial bitstream is
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/openbmc/linux/drivers/mfd/
H A Docelot-core.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Core driver for the Ocelot chip family.
6 * on-chip MIPS processor, or externally via SPI, I2C, PCIe. This core driver is
7 * intended to be the bus-agnostic glue between, for example, the SPI bus and
10 * Copyright 2021-2022 Innovative Advantage Inc.
12 * Author: Colin Foster <colin.foster@in-advantage.com>
22 #include <linux/mfd/ocelot.h>
27 #include <soc/mscc/ocelot.h>
29 #include "ocelot.h"
91 err = regmap_read(ddata->gcb_regmap, REG_GCB_SOFT_RST, &val); in ocelot_gcb_chip_rst_status()
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/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
28 #size-cells = <0>;
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
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/openbmc/linux/arch/mips/boot/dts/mscc/
H A Dserval.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
28 cpuintc: interrupt-controller {
29 #address-cells = <0>;
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "mti,cpu-interrupt-controller";
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/openbmc/u-boot/drivers/gpio/
H A Dmscc_sgpio.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
44 #define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
46 #define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
47 #define MSCC_F_CFG_SIO_PORT_WIDTH(p, x) __F(p->props->port_width, x)
48 #define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
49 #define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x) __F(p->props->clk_freq, x)
50 #define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
51 #define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
52 #define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
81 u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off]; in sgpio_readl()
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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-microchip-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/mfd/ocelot.h>
138 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
139 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
144 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
149 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr()
150 regmap_get_reg_stride(priv->regs); in sgpio_get_addr()
159 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl()
160 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); in sgpio_readl()
171 ret = regmap_write(priv->regs, addr, val); in sgpio_writel()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
4 subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
6 obj-y += core.o pinctrl-utils.o
7 obj-$(CONFIG_PINMUX) += pinmux.o
8 obj-$(CONFIG_PINCONF) += pinconf.o
9 obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
10 obj-$(CONFIG_OF) += devicetree.o
12 obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
13 obj-$(CONFIG_PINCTRL_APPLE_GPIO) += pinctrl-apple-gpio.o
14 obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
66 will be called pinctrl-apple-gpio.
69 bool "Axis ARTPEC-6 pin controller driver"
74 This is the driver for the Axis ARTPEC-6 pin controller. This driver
77 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
86 functionality. This driver supports the pinmux, push-pull and
117 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
150 called pinctrl-cy8c95x0.
153 tristate "TI DA850/OMAP-L138/AM18XX pull-up and pull-down groups"
158 Driver for TI DA850/OMAP-L138/AM18XX pinconf. Used to control
[all …]
/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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H A Dopengrok2.0.log1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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/openbmc/
Dopengrok1.0.log1 2025-03-17 03:00:37.547-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-17 03:00:37.671-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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Dopengrok2.0.log1 2025-03-16 03:00:36.730-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-16 03:00:36.828-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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