| /openbmc/linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | memory.json | 5 …sfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloa…
10 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
15 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
20 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
30 … MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand…
40 …sfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloa…
45 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
50 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
55 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
60 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
[all …]
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| H A D | frontend.json | 5 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
10 … MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand…
55 … MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand…
60 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
65 …e. LMQ merges are not included in this count. i.e. if a load instruction misses on an address that…
85 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
90 …Description": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses."
|
| H A D | marked.json | 15 …sfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloa…
25 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
95 …sfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloa…
120 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
145 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
160 …sfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloa…
200 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
225 …sfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloa…
235 …his event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand…
240 … MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand…
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
6 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
11 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati…
14 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat…
27 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
35 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
46 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
61 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
69 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
77 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
6 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
11 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati…
14 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat…
27 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
35 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
46 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
61 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
69 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
77 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
| H A D | recommended.json | 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
97 "BriefDescription": "L3 Misses (includes Chg2X)",
117 "BriefDescription": "L1 ITLB Misses",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | recommended.json | 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
97 "BriefDescription": "L3 Misses (includes Chg2X)",
117 "BriefDescription": "L1 ITLB Misses",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
19 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
26 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
45 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
54 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
63 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
77 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
81 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
93 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
19 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
26 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
45 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
54 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
63 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
77 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
81 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
93 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
7 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
19 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
26 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
45 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
54 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
63 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
77 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
81 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
93 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | recommended.json | 24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
97 "BriefDescription": "L3 Misses (includes cacheline state change requests)",
153 "BriefDescription": "L1 ITLB Misses",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | memory.json | 40 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
46 …"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 1…
52 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
58 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
64 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pa…
70 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coale…
76 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pa…
82 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pa…
88 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all p…
94 "BriefDescription": "L1 DTLB misses for all page sizes.",
|
| H A D | recommended.json | 23 "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
29 "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
41 "BriefDescription": "All L2 cache misses.",
47 "BriefDescription": "L2 cache misses from L1 instruction cache misses.",
53 "BriefDescription": "L2 cache misses from L1 data cache misses.",
59 "BriefDescription": "L2 cache misses from L2 cache hardware prefetcher.",
71 "BriefDescription": "L2 cache hits from L1 instruction cache misses.",
77 "BriefDescription": "L2 cache hits from L1 data cache misses.",
95 "BriefDescription": "L3 misses (including cacheline state change requests).",
186 "BriefDescription": "L1 instruction TLB misses.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | virtual-memory.json | 10 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de…
17 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag…
33 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
41 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
64 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor…
71 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any pag…
79 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa…
87 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or…
95 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K pa…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | virtual-memory.json | 10 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de…
17 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag…
33 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
41 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
64 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor…
71 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any pag…
79 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa…
87 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or…
95 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K pa…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | virtual-memory.json | 13 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
29 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
42 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
58 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
89 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
92 … "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
97 "BriefDescription": "Misses at all ITLB levels that cause page walks",
100 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
113 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
116 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | virtual-memory.json | 27 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
43 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
56 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
72 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
103 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
106 … "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
111 "BriefDescription": "Misses at all ITLB levels that cause page walks",
114 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
127 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
130 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
18 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
28 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
33 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
47 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
75 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
89 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
99 …is event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
18 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
28 …unts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
33 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
47 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
75 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
89 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
99 …is event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/bonnell/ |
| H A D | virtual-memory.json | 10 "BriefDescription": "DTLB misses due to load operations.",
17 "BriefDescription": "DTLB misses due to store operations.",
24 "BriefDescription": "L0 DTLB misses due to load operations.",
31 "BriefDescription": "L0 DTLB misses due to store operations",
52 "BriefDescription": "ITLB misses.",
54 "EventName": "ITLB.MISSES",
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | l2_cache.json | 4 …e is a unified cache for data and instruction accesses. Accesses are for misses in the first level…
8 …e is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 cac…
20 …e is a unified cache for data and instruction accesses, accesses are for misses in the level 1 cac…
24 …e is a unified cache for data and instruction accesses, accesses are for misses in the level 1 cac…
28 …e is a unified cache for data and instruction accesses, accesses are for misses in the level 1 cac…
32 …e is a unified cache for data and instruction accesses, accesses are for misses in the level 1 cac…
|
| H A D | tlb.json | 4 …nstruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that ar…
8 … 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that ar…
16 …n": "Counts level 1 instruction TLB accesses, whether the access hits or misses in the TLB. This e…
36 …data TLB refills caused by memory read operations. If there are multiple misses in the TLB that ar…
40 …fills caused by data side memory write operations. If there are multiple misses in the TLB that ar…
44 … by memory read operations. This event counts whether the access hits or misses in the TLB. This e…
48 …by memory write operations. This event counts whether the access hits or misses in the TLB. This e…
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | l2_cache.json | 4 …e is a unified cache for data and instruction accesses. Accesses are for misses in the first level…
8 …e is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 cac…
20 …e is a unified cache for data and instruction accesses, accesses are for misses in the level 1 cac…
24 …e is a unified cache for data and instruction accesses, accesses are for misses in the level 1 cac…
28 …e is a unified cache for data and instruction accesses, accesses are for misses in the level 1 cac…
32 …e is a unified cache for data and instruction accesses, accesses are for misses in the level 1 cac…
|
| H A D | tlb.json | 4 …nstruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that ar…
8 … 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that ar…
16 …n": "Counts level 1 instruction TLB accesses, whether the access hits or misses in the TLB. This e…
36 …data TLB refills caused by memory read operations. If there are multiple misses in the TLB that ar…
40 …fills caused by data side memory write operations. If there are multiple misses in the TLB that ar…
44 … by memory read operations. This event counts whether the access hits or misses in the TLB. This e…
48 …by memory write operations. This event counts whether the access hits or misses in the TLB. This e…
|
| /openbmc/linux/tools/perf/pmu-events/arch/test/test_soc/cpu/ |
| H A D | uncore.json | 14 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c…
15 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor …
47 "BriefDescription": "Total cache misses",
48 "PublicDescription": "Total cache misses",
|