1dcfbad10SAndi Kleen[ 2dcfbad10SAndi Kleen { 3dcfbad10SAndi Kleen "BriefDescription": "Load misses in all DTLB levels that cause page walks", 4*4dd25272SIan Rogers "EventCode": "0x08", 5*4dd25272SIan Rogers "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 6*4dd25272SIan Rogers "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 7*4dd25272SIan Rogers "SampleAfterValue": "100003", 8*4dd25272SIan Rogers "UMask": "0x1" 9dcfbad10SAndi Kleen }, 10dcfbad10SAndi Kleen { 11*4dd25272SIan Rogers "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", 12*4dd25272SIan Rogers "EventCode": "0x08", 13*4dd25272SIan Rogers "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", 14*4dd25272SIan Rogers "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", 15*4dd25272SIan Rogers "SampleAfterValue": "100003", 16*4dd25272SIan Rogers "UMask": "0x80" 17*4dd25272SIan Rogers }, 18*4dd25272SIan Rogers { 19*4dd25272SIan Rogers "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", 20*4dd25272SIan Rogers "EventCode": "0x08", 21*4dd25272SIan Rogers "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 22*4dd25272SIan Rogers "PublicDescription": "Number of cache load STLB hits. No page walk.", 23dcfbad10SAndi Kleen "SampleAfterValue": "2000003", 24*4dd25272SIan Rogers "UMask": "0x60" 25dcfbad10SAndi Kleen }, 26dcfbad10SAndi Kleen { 27*4dd25272SIan Rogers "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 28*4dd25272SIan Rogers "EventCode": "0x08", 29*4dd25272SIan Rogers "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", 30*4dd25272SIan Rogers "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 31dcfbad10SAndi Kleen "SampleAfterValue": "2000003", 32*4dd25272SIan Rogers "UMask": "0x40" 33dcfbad10SAndi Kleen }, 34dcfbad10SAndi Kleen { 35*4dd25272SIan Rogers "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 36*4dd25272SIan Rogers "EventCode": "0x08", 37*4dd25272SIan Rogers "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", 38*4dd25272SIan Rogers "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 39*4dd25272SIan Rogers "SampleAfterValue": "2000003", 40*4dd25272SIan Rogers "UMask": "0x20" 41*4dd25272SIan Rogers }, 42*4dd25272SIan Rogers { 43*4dd25272SIan Rogers "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 44*4dd25272SIan Rogers "EventCode": "0x08", 45*4dd25272SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 46*4dd25272SIan Rogers "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", 47*4dd25272SIan Rogers "SampleAfterValue": "100003", 48*4dd25272SIan Rogers "UMask": "0xe" 49*4dd25272SIan Rogers }, 50*4dd25272SIan Rogers { 51*4dd25272SIan Rogers "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 52*4dd25272SIan Rogers "EventCode": "0x08", 53dcfbad10SAndi Kleen "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 54dcfbad10SAndi Kleen "SampleAfterValue": "2000003", 55*4dd25272SIan Rogers "UMask": "0x8" 56dcfbad10SAndi Kleen }, 57dcfbad10SAndi Kleen { 58*4dd25272SIan Rogers "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", 59dcfbad10SAndi Kleen "EventCode": "0x08", 60*4dd25272SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 61*4dd25272SIan Rogers "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", 62dcfbad10SAndi Kleen "SampleAfterValue": "2000003", 63*4dd25272SIan Rogers "UMask": "0x4" 64*4dd25272SIan Rogers }, 65*4dd25272SIan Rogers { 66*4dd25272SIan Rogers "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", 67*4dd25272SIan Rogers "EventCode": "0x08", 68*4dd25272SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 69*4dd25272SIan Rogers "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", 70*4dd25272SIan Rogers "SampleAfterValue": "2000003", 71*4dd25272SIan Rogers "UMask": "0x2" 72*4dd25272SIan Rogers }, 73*4dd25272SIan Rogers { 74dcfbad10SAndi Kleen "BriefDescription": "Cycles when PMH is busy with page walks", 75*4dd25272SIan Rogers "EventCode": "0x08", 76*4dd25272SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", 77*4dd25272SIan Rogers "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", 78dcfbad10SAndi Kleen "SampleAfterValue": "2000003", 79*4dd25272SIan Rogers "UMask": "0x10" 80dcfbad10SAndi Kleen }, 81dcfbad10SAndi Kleen { 82dcfbad10SAndi Kleen "BriefDescription": "Store misses in all DTLB levels that cause page walks", 83*4dd25272SIan Rogers "EventCode": "0x49", 84*4dd25272SIan Rogers "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 85*4dd25272SIan Rogers "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", 86dcfbad10SAndi Kleen "SampleAfterValue": "100003", 87*4dd25272SIan Rogers "UMask": "0x1" 88dcfbad10SAndi Kleen }, 89dcfbad10SAndi Kleen { 90*4dd25272SIan Rogers "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", 91*4dd25272SIan Rogers "EventCode": "0x49", 92*4dd25272SIan Rogers "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", 93*4dd25272SIan Rogers "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", 94dcfbad10SAndi Kleen "SampleAfterValue": "100003", 95*4dd25272SIan Rogers "UMask": "0x80" 96dcfbad10SAndi Kleen }, 97dcfbad10SAndi Kleen { 98*4dd25272SIan Rogers "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", 99*4dd25272SIan Rogers "EventCode": "0x49", 100*4dd25272SIan Rogers "EventName": "DTLB_STORE_MISSES.STLB_HIT", 101*4dd25272SIan Rogers "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", 102*4dd25272SIan Rogers "SampleAfterValue": "100003", 103*4dd25272SIan Rogers "UMask": "0x60" 104*4dd25272SIan Rogers }, 105*4dd25272SIan Rogers { 106*4dd25272SIan Rogers "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 107*4dd25272SIan Rogers "EventCode": "0x49", 108*4dd25272SIan Rogers "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", 109*4dd25272SIan Rogers "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 110*4dd25272SIan Rogers "SampleAfterValue": "100003", 111*4dd25272SIan Rogers "UMask": "0x40" 112*4dd25272SIan Rogers }, 113*4dd25272SIan Rogers { 114*4dd25272SIan Rogers "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 115*4dd25272SIan Rogers "EventCode": "0x49", 116*4dd25272SIan Rogers "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", 117*4dd25272SIan Rogers "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 118*4dd25272SIan Rogers "SampleAfterValue": "100003", 119*4dd25272SIan Rogers "UMask": "0x20" 120*4dd25272SIan Rogers }, 121*4dd25272SIan Rogers { 122*4dd25272SIan Rogers "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", 123*4dd25272SIan Rogers "EventCode": "0x49", 124*4dd25272SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 125*4dd25272SIan Rogers "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", 126*4dd25272SIan Rogers "SampleAfterValue": "100003", 127*4dd25272SIan Rogers "UMask": "0xe" 128*4dd25272SIan Rogers }, 129*4dd25272SIan Rogers { 130*4dd25272SIan Rogers "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", 131*4dd25272SIan Rogers "EventCode": "0x49", 132dcfbad10SAndi Kleen "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 133dcfbad10SAndi Kleen "SampleAfterValue": "100003", 134*4dd25272SIan Rogers "UMask": "0x8" 135dcfbad10SAndi Kleen }, 136dcfbad10SAndi Kleen { 137*4dd25272SIan Rogers "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", 138*4dd25272SIan Rogers "EventCode": "0x49", 139*4dd25272SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 140*4dd25272SIan Rogers "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", 141ca3a2d05SAndi Kleen "SampleAfterValue": "100003", 142*4dd25272SIan Rogers "UMask": "0x4" 143ca3a2d05SAndi Kleen }, 144ca3a2d05SAndi Kleen { 145*4dd25272SIan Rogers "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", 146*4dd25272SIan Rogers "EventCode": "0x49", 147*4dd25272SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 148*4dd25272SIan Rogers "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", 149dcfbad10SAndi Kleen "SampleAfterValue": "100003", 150*4dd25272SIan Rogers "UMask": "0x2" 151*4dd25272SIan Rogers }, 152*4dd25272SIan Rogers { 153dcfbad10SAndi Kleen "BriefDescription": "Cycles when PMH is busy with page walks", 154dcfbad10SAndi Kleen "EventCode": "0x49", 155*4dd25272SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_DURATION", 156*4dd25272SIan Rogers "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", 157dcfbad10SAndi Kleen "SampleAfterValue": "100003", 158*4dd25272SIan Rogers "UMask": "0x10" 159dcfbad10SAndi Kleen }, 160dcfbad10SAndi Kleen { 161*4dd25272SIan Rogers "BriefDescription": "Cycle count for an Extended Page table walk.", 162dcfbad10SAndi Kleen "EventCode": "0x4f", 163dcfbad10SAndi Kleen "EventName": "EPT.WALK_CYCLES", 164dcfbad10SAndi Kleen "SampleAfterValue": "2000003", 165*4dd25272SIan Rogers "UMask": "0x10" 166dcfbad10SAndi Kleen }, 167dcfbad10SAndi Kleen { 168*4dd25272SIan Rogers "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 169*4dd25272SIan Rogers "EventCode": "0xae", 170*4dd25272SIan Rogers "EventName": "ITLB.ITLB_FLUSH", 171*4dd25272SIan Rogers "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", 172dcfbad10SAndi Kleen "SampleAfterValue": "100003", 173*4dd25272SIan Rogers "UMask": "0x1" 174*4dd25272SIan Rogers }, 175*4dd25272SIan Rogers { 176dcfbad10SAndi Kleen "BriefDescription": "Misses at all ITLB levels that cause page walks", 177*4dd25272SIan Rogers "EventCode": "0x85", 178*4dd25272SIan Rogers "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 179*4dd25272SIan Rogers "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", 180dcfbad10SAndi Kleen "SampleAfterValue": "100003", 181*4dd25272SIan Rogers "UMask": "0x1" 182dcfbad10SAndi Kleen }, 183dcfbad10SAndi Kleen { 184*4dd25272SIan Rogers "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", 185*4dd25272SIan Rogers "EventCode": "0x85", 186*4dd25272SIan Rogers "EventName": "ITLB_MISSES.STLB_HIT", 187*4dd25272SIan Rogers "PublicDescription": "ITLB misses that hit STLB. No page walk.", 188dcfbad10SAndi Kleen "SampleAfterValue": "100003", 189*4dd25272SIan Rogers "UMask": "0x60" 190dcfbad10SAndi Kleen }, 191dcfbad10SAndi Kleen { 192*4dd25272SIan Rogers "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", 193*4dd25272SIan Rogers "EventCode": "0x85", 194*4dd25272SIan Rogers "EventName": "ITLB_MISSES.STLB_HIT_2M", 195*4dd25272SIan Rogers "PublicDescription": "ITLB misses that hit STLB (2M).", 196*4dd25272SIan Rogers "SampleAfterValue": "100003", 197*4dd25272SIan Rogers "UMask": "0x40" 198*4dd25272SIan Rogers }, 199*4dd25272SIan Rogers { 200*4dd25272SIan Rogers "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", 201*4dd25272SIan Rogers "EventCode": "0x85", 202*4dd25272SIan Rogers "EventName": "ITLB_MISSES.STLB_HIT_4K", 203*4dd25272SIan Rogers "PublicDescription": "ITLB misses that hit STLB (4K).", 204*4dd25272SIan Rogers "SampleAfterValue": "100003", 205*4dd25272SIan Rogers "UMask": "0x20" 206*4dd25272SIan Rogers }, 207*4dd25272SIan Rogers { 208*4dd25272SIan Rogers "BriefDescription": "Misses in all ITLB levels that cause completed page walks", 209*4dd25272SIan Rogers "EventCode": "0x85", 210*4dd25272SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED", 211*4dd25272SIan Rogers "PublicDescription": "Completed page walks in ITLB of any page size.", 212*4dd25272SIan Rogers "SampleAfterValue": "100003", 213*4dd25272SIan Rogers "UMask": "0xe" 214*4dd25272SIan Rogers }, 215*4dd25272SIan Rogers { 216*4dd25272SIan Rogers "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", 217*4dd25272SIan Rogers "EventCode": "0x85", 218dcfbad10SAndi Kleen "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", 219dcfbad10SAndi Kleen "SampleAfterValue": "100003", 220*4dd25272SIan Rogers "UMask": "0x8" 221dcfbad10SAndi Kleen }, 222dcfbad10SAndi Kleen { 223*4dd25272SIan Rogers "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 224*4dd25272SIan Rogers "EventCode": "0x85", 225*4dd25272SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 226*4dd25272SIan Rogers "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", 227ca3a2d05SAndi Kleen "SampleAfterValue": "100003", 228*4dd25272SIan Rogers "UMask": "0x4" 229ca3a2d05SAndi Kleen }, 230ca3a2d05SAndi Kleen { 231*4dd25272SIan Rogers "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 232*4dd25272SIan Rogers "EventCode": "0x85", 233*4dd25272SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 234*4dd25272SIan Rogers "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", 235dcfbad10SAndi Kleen "SampleAfterValue": "100003", 236*4dd25272SIan Rogers "UMask": "0x2" 237*4dd25272SIan Rogers }, 238*4dd25272SIan Rogers { 239dcfbad10SAndi Kleen "BriefDescription": "Cycles when PMH is busy with page walks", 240dcfbad10SAndi Kleen "EventCode": "0x85", 241*4dd25272SIan Rogers "EventName": "ITLB_MISSES.WALK_DURATION", 242*4dd25272SIan Rogers "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", 243dcfbad10SAndi Kleen "SampleAfterValue": "100003", 244*4dd25272SIan Rogers "UMask": "0x10" 245dcfbad10SAndi Kleen }, 246dcfbad10SAndi Kleen { 247dcfbad10SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in the L1+FB", 248*4dd25272SIan Rogers "EventCode": "0xBC", 249*4dd25272SIan Rogers "EventName": "PAGE_WALKER_LOADS.DTLB_L1", 250*4dd25272SIan Rogers "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", 251*4dd25272SIan Rogers "SampleAfterValue": "2000003", 252*4dd25272SIan Rogers "UMask": "0x11" 253dcfbad10SAndi Kleen }, 254dcfbad10SAndi Kleen { 255dcfbad10SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in the L2", 256*4dd25272SIan Rogers "EventCode": "0xBC", 257*4dd25272SIan Rogers "EventName": "PAGE_WALKER_LOADS.DTLB_L2", 258*4dd25272SIan Rogers "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", 259*4dd25272SIan Rogers "SampleAfterValue": "2000003", 260*4dd25272SIan Rogers "UMask": "0x12" 261dcfbad10SAndi Kleen }, 262dcfbad10SAndi Kleen { 263dcfbad10SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", 264*4dd25272SIan Rogers "Errata": "HSD25", 265*4dd25272SIan Rogers "EventCode": "0xBC", 266*4dd25272SIan Rogers "EventName": "PAGE_WALKER_LOADS.DTLB_L3", 267*4dd25272SIan Rogers "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", 268*4dd25272SIan Rogers "SampleAfterValue": "2000003", 269*4dd25272SIan Rogers "UMask": "0x14" 270dcfbad10SAndi Kleen }, 271dcfbad10SAndi Kleen { 272dcfbad10SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in Memory", 273ca3a2d05SAndi Kleen "Errata": "HSD25", 274*4dd25272SIan Rogers "EventCode": "0xBC", 275*4dd25272SIan Rogers "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", 276*4dd25272SIan Rogers "PublicDescription": "Number of DTLB page walker loads from memory.", 277ca3a2d05SAndi Kleen "SampleAfterValue": "2000003", 278*4dd25272SIan Rogers "UMask": "0x18" 279ca3a2d05SAndi Kleen }, 280ca3a2d05SAndi Kleen { 281*4dd25272SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", 282dcfbad10SAndi Kleen "EventCode": "0xBC", 283ca3a2d05SAndi Kleen "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", 284ca3a2d05SAndi Kleen "SampleAfterValue": "2000003", 285*4dd25272SIan Rogers "UMask": "0x41" 286ca3a2d05SAndi Kleen }, 287ca3a2d05SAndi Kleen { 288*4dd25272SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", 289*4dd25272SIan Rogers "EventCode": "0xBC", 290ca3a2d05SAndi Kleen "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", 291ca3a2d05SAndi Kleen "SampleAfterValue": "2000003", 292*4dd25272SIan Rogers "UMask": "0x42" 293ca3a2d05SAndi Kleen }, 294ca3a2d05SAndi Kleen { 295*4dd25272SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", 296*4dd25272SIan Rogers "EventCode": "0xBC", 297ca3a2d05SAndi Kleen "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", 298ca3a2d05SAndi Kleen "SampleAfterValue": "2000003", 299*4dd25272SIan Rogers "UMask": "0x44" 300ca3a2d05SAndi Kleen }, 301ca3a2d05SAndi Kleen { 302*4dd25272SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", 303*4dd25272SIan Rogers "EventCode": "0xBC", 304dcfbad10SAndi Kleen "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", 305dcfbad10SAndi Kleen "SampleAfterValue": "2000003", 306*4dd25272SIan Rogers "UMask": "0x48" 307dcfbad10SAndi Kleen }, 308dcfbad10SAndi Kleen { 309*4dd25272SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", 310*4dd25272SIan Rogers "EventCode": "0xBC", 311ca3a2d05SAndi Kleen "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", 312ca3a2d05SAndi Kleen "SampleAfterValue": "2000003", 313*4dd25272SIan Rogers "UMask": "0x81" 314ca3a2d05SAndi Kleen }, 315ca3a2d05SAndi Kleen { 316*4dd25272SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 317*4dd25272SIan Rogers "EventCode": "0xBC", 318ca3a2d05SAndi Kleen "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", 319ca3a2d05SAndi Kleen "SampleAfterValue": "2000003", 320*4dd25272SIan Rogers "UMask": "0x82" 321ca3a2d05SAndi Kleen }, 322ca3a2d05SAndi Kleen { 323*4dd25272SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 324*4dd25272SIan Rogers "EventCode": "0xBC", 325ca3a2d05SAndi Kleen "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", 326ca3a2d05SAndi Kleen "SampleAfterValue": "2000003", 327*4dd25272SIan Rogers "UMask": "0x84" 328ca3a2d05SAndi Kleen }, 329ca3a2d05SAndi Kleen { 330*4dd25272SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", 331*4dd25272SIan Rogers "EventCode": "0xBC", 332dcfbad10SAndi Kleen "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", 333dcfbad10SAndi Kleen "SampleAfterValue": "2000003", 334*4dd25272SIan Rogers "UMask": "0x88" 335dcfbad10SAndi Kleen }, 336dcfbad10SAndi Kleen { 337*4dd25272SIan Rogers "BriefDescription": "Number of ITLB page walker hits in the L1+FB", 338*4dd25272SIan Rogers "EventCode": "0xBC", 339*4dd25272SIan Rogers "EventName": "PAGE_WALKER_LOADS.ITLB_L1", 340*4dd25272SIan Rogers "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", 341*4dd25272SIan Rogers "SampleAfterValue": "2000003", 342*4dd25272SIan Rogers "UMask": "0x21" 343*4dd25272SIan Rogers }, 344*4dd25272SIan Rogers { 345*4dd25272SIan Rogers "BriefDescription": "Number of ITLB page walker hits in the L2", 346*4dd25272SIan Rogers "EventCode": "0xBC", 347*4dd25272SIan Rogers "EventName": "PAGE_WALKER_LOADS.ITLB_L2", 348*4dd25272SIan Rogers "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", 349*4dd25272SIan Rogers "SampleAfterValue": "2000003", 350*4dd25272SIan Rogers "UMask": "0x22" 351*4dd25272SIan Rogers }, 352*4dd25272SIan Rogers { 353*4dd25272SIan Rogers "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", 354*4dd25272SIan Rogers "Errata": "HSD25", 355*4dd25272SIan Rogers "EventCode": "0xBC", 356*4dd25272SIan Rogers "EventName": "PAGE_WALKER_LOADS.ITLB_L3", 357*4dd25272SIan Rogers "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", 358*4dd25272SIan Rogers "SampleAfterValue": "2000003", 359*4dd25272SIan Rogers "UMask": "0x24" 360*4dd25272SIan Rogers }, 361*4dd25272SIan Rogers { 362*4dd25272SIan Rogers "BriefDescription": "Number of ITLB page walker hits in Memory", 363*4dd25272SIan Rogers "Errata": "HSD25", 364*4dd25272SIan Rogers "EventCode": "0xBC", 365*4dd25272SIan Rogers "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", 366*4dd25272SIan Rogers "PublicDescription": "Number of ITLB page walker loads from memory.", 367*4dd25272SIan Rogers "SampleAfterValue": "2000003", 368*4dd25272SIan Rogers "UMask": "0x28" 369*4dd25272SIan Rogers }, 370*4dd25272SIan Rogers { 371dcfbad10SAndi Kleen "BriefDescription": "DTLB flush attempts of the thread-specific entries", 372*4dd25272SIan Rogers "EventCode": "0xBD", 373*4dd25272SIan Rogers "EventName": "TLB_FLUSH.DTLB_THREAD", 374*4dd25272SIan Rogers "PublicDescription": "DTLB flush attempts of the thread-specific entries.", 375*4dd25272SIan Rogers "SampleAfterValue": "100003", 376*4dd25272SIan Rogers "UMask": "0x1" 377dcfbad10SAndi Kleen }, 378dcfbad10SAndi Kleen { 379dcfbad10SAndi Kleen "BriefDescription": "STLB flush attempts", 380*4dd25272SIan Rogers "EventCode": "0xBD", 381*4dd25272SIan Rogers "EventName": "TLB_FLUSH.STLB_ANY", 382*4dd25272SIan Rogers "PublicDescription": "Count number of STLB flush attempts.", 383*4dd25272SIan Rogers "SampleAfterValue": "100003", 384*4dd25272SIan Rogers "UMask": "0x20" 385dcfbad10SAndi Kleen } 386dcfbad10SAndi Kleen] 387