1ede00740SAndi Kleen[ 2ede00740SAndi Kleen { 3ede00740SAndi Kleen "BriefDescription": "Load misses in all DTLB levels that cause page walks", 4*f16c3236SIan Rogers "EventCode": "0x08", 5ede00740SAndi Kleen "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 6ede00740SAndi Kleen "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 7ede00740SAndi Kleen "SampleAfterValue": "100003", 8*f16c3236SIan Rogers "UMask": "0x1" 9ede00740SAndi Kleen }, 10ede00740SAndi Kleen { 11ede00740SAndi Kleen "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", 12*f16c3236SIan Rogers "EventCode": "0x08", 13ede00740SAndi Kleen "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", 14ede00740SAndi Kleen "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", 15ede00740SAndi Kleen "SampleAfterValue": "100003", 16*f16c3236SIan Rogers "UMask": "0x80" 17ede00740SAndi Kleen }, 18ede00740SAndi Kleen { 19*f16c3236SIan Rogers "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", 20*f16c3236SIan Rogers "EventCode": "0x08", 21*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 22*f16c3236SIan Rogers "PublicDescription": "Number of cache load STLB hits. No page walk.", 23*f16c3236SIan Rogers "SampleAfterValue": "2000003", 24*f16c3236SIan Rogers "UMask": "0x60" 25*f16c3236SIan Rogers }, 26*f16c3236SIan Rogers { 27*f16c3236SIan Rogers "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 28*f16c3236SIan Rogers "EventCode": "0x08", 29*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", 30*f16c3236SIan Rogers "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 31*f16c3236SIan Rogers "SampleAfterValue": "2000003", 32*f16c3236SIan Rogers "UMask": "0x40" 33*f16c3236SIan Rogers }, 34*f16c3236SIan Rogers { 35*f16c3236SIan Rogers "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 36*f16c3236SIan Rogers "EventCode": "0x08", 37*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", 38*f16c3236SIan Rogers "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 39*f16c3236SIan Rogers "SampleAfterValue": "2000003", 40*f16c3236SIan Rogers "UMask": "0x20" 41*f16c3236SIan Rogers }, 42*f16c3236SIan Rogers { 43*f16c3236SIan Rogers "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 44*f16c3236SIan Rogers "EventCode": "0x08", 45*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 46*f16c3236SIan Rogers "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", 47*f16c3236SIan Rogers "SampleAfterValue": "100003", 48*f16c3236SIan Rogers "UMask": "0xe" 49*f16c3236SIan Rogers }, 50*f16c3236SIan Rogers { 51*f16c3236SIan Rogers "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 52*f16c3236SIan Rogers "EventCode": "0x08", 53*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 54*f16c3236SIan Rogers "SampleAfterValue": "2000003", 55*f16c3236SIan Rogers "UMask": "0x8" 56*f16c3236SIan Rogers }, 57*f16c3236SIan Rogers { 58*f16c3236SIan Rogers "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", 59*f16c3236SIan Rogers "EventCode": "0x08", 60*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 61*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", 62*f16c3236SIan Rogers "SampleAfterValue": "2000003", 63*f16c3236SIan Rogers "UMask": "0x4" 64*f16c3236SIan Rogers }, 65*f16c3236SIan Rogers { 66*f16c3236SIan Rogers "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", 67*f16c3236SIan Rogers "EventCode": "0x08", 68*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 69*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", 70*f16c3236SIan Rogers "SampleAfterValue": "2000003", 71*f16c3236SIan Rogers "UMask": "0x2" 72*f16c3236SIan Rogers }, 73*f16c3236SIan Rogers { 74*f16c3236SIan Rogers "BriefDescription": "Cycles when PMH is busy with page walks", 75*f16c3236SIan Rogers "EventCode": "0x08", 76*f16c3236SIan Rogers "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", 77*f16c3236SIan Rogers "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", 78*f16c3236SIan Rogers "SampleAfterValue": "2000003", 79*f16c3236SIan Rogers "UMask": "0x10" 80*f16c3236SIan Rogers }, 81*f16c3236SIan Rogers { 82ede00740SAndi Kleen "BriefDescription": "Store misses in all DTLB levels that cause page walks", 83*f16c3236SIan Rogers "EventCode": "0x49", 84ede00740SAndi Kleen "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 85ede00740SAndi Kleen "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", 86ede00740SAndi Kleen "SampleAfterValue": "100003", 87*f16c3236SIan Rogers "UMask": "0x1" 88ede00740SAndi Kleen }, 89ede00740SAndi Kleen { 90ede00740SAndi Kleen "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", 91*f16c3236SIan Rogers "EventCode": "0x49", 92ede00740SAndi Kleen "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", 93ede00740SAndi Kleen "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", 94ede00740SAndi Kleen "SampleAfterValue": "100003", 95*f16c3236SIan Rogers "UMask": "0x80" 96ede00740SAndi Kleen }, 97ede00740SAndi Kleen { 98*f16c3236SIan Rogers "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", 99*f16c3236SIan Rogers "EventCode": "0x49", 100*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.STLB_HIT", 101*f16c3236SIan Rogers "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", 102ede00740SAndi Kleen "SampleAfterValue": "100003", 103*f16c3236SIan Rogers "UMask": "0x60" 104ede00740SAndi Kleen }, 105ede00740SAndi Kleen { 106*f16c3236SIan Rogers "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 107*f16c3236SIan Rogers "EventCode": "0x49", 108*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", 109*f16c3236SIan Rogers "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 110ede00740SAndi Kleen "SampleAfterValue": "100003", 111*f16c3236SIan Rogers "UMask": "0x40" 112ede00740SAndi Kleen }, 113ede00740SAndi Kleen { 114*f16c3236SIan Rogers "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 115*f16c3236SIan Rogers "EventCode": "0x49", 116*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", 117*f16c3236SIan Rogers "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 118ede00740SAndi Kleen "SampleAfterValue": "100003", 119*f16c3236SIan Rogers "UMask": "0x20" 120ede00740SAndi Kleen }, 121ede00740SAndi Kleen { 122*f16c3236SIan Rogers "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", 123*f16c3236SIan Rogers "EventCode": "0x49", 124*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 125*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", 126ede00740SAndi Kleen "SampleAfterValue": "100003", 127*f16c3236SIan Rogers "UMask": "0xe" 128ede00740SAndi Kleen }, 129ede00740SAndi Kleen { 130*f16c3236SIan Rogers "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", 131*f16c3236SIan Rogers "EventCode": "0x49", 132*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 133032c16b2SAndi Kleen "SampleAfterValue": "100003", 134*f16c3236SIan Rogers "UMask": "0x8" 135032c16b2SAndi Kleen }, 136032c16b2SAndi Kleen { 137*f16c3236SIan Rogers "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", 138*f16c3236SIan Rogers "EventCode": "0x49", 139*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 140*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", 141*f16c3236SIan Rogers "SampleAfterValue": "100003", 142*f16c3236SIan Rogers "UMask": "0x4" 143*f16c3236SIan Rogers }, 144*f16c3236SIan Rogers { 145*f16c3236SIan Rogers "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", 146*f16c3236SIan Rogers "EventCode": "0x49", 147*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 148*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", 149*f16c3236SIan Rogers "SampleAfterValue": "100003", 150*f16c3236SIan Rogers "UMask": "0x2" 151*f16c3236SIan Rogers }, 152*f16c3236SIan Rogers { 153ede00740SAndi Kleen "BriefDescription": "Cycles when PMH is busy with page walks", 154*f16c3236SIan Rogers "EventCode": "0x49", 155*f16c3236SIan Rogers "EventName": "DTLB_STORE_MISSES.WALK_DURATION", 156*f16c3236SIan Rogers "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", 157ede00740SAndi Kleen "SampleAfterValue": "100003", 158*f16c3236SIan Rogers "UMask": "0x10" 159ede00740SAndi Kleen }, 160ede00740SAndi Kleen { 161*f16c3236SIan Rogers "BriefDescription": "Cycle count for an Extended Page table walk.", 162*f16c3236SIan Rogers "EventCode": "0x4f", 163*f16c3236SIan Rogers "EventName": "EPT.WALK_CYCLES", 164*f16c3236SIan Rogers "SampleAfterValue": "2000003", 165*f16c3236SIan Rogers "UMask": "0x10" 166ede00740SAndi Kleen }, 167ede00740SAndi Kleen { 168ede00740SAndi Kleen "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 169*f16c3236SIan Rogers "EventCode": "0xae", 170ede00740SAndi Kleen "EventName": "ITLB.ITLB_FLUSH", 171ede00740SAndi Kleen "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", 172ede00740SAndi Kleen "SampleAfterValue": "100003", 173*f16c3236SIan Rogers "UMask": "0x1" 174ede00740SAndi Kleen }, 175ede00740SAndi Kleen { 176*f16c3236SIan Rogers "BriefDescription": "Misses at all ITLB levels that cause page walks", 177*f16c3236SIan Rogers "EventCode": "0x85", 178*f16c3236SIan Rogers "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 179*f16c3236SIan Rogers "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", 180*f16c3236SIan Rogers "SampleAfterValue": "100003", 181*f16c3236SIan Rogers "UMask": "0x1" 182*f16c3236SIan Rogers }, 183*f16c3236SIan Rogers { 184*f16c3236SIan Rogers "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", 185*f16c3236SIan Rogers "EventCode": "0x85", 186*f16c3236SIan Rogers "EventName": "ITLB_MISSES.STLB_HIT", 187*f16c3236SIan Rogers "PublicDescription": "ITLB misses that hit STLB. No page walk.", 188*f16c3236SIan Rogers "SampleAfterValue": "100003", 189*f16c3236SIan Rogers "UMask": "0x60" 190*f16c3236SIan Rogers }, 191*f16c3236SIan Rogers { 192*f16c3236SIan Rogers "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", 193*f16c3236SIan Rogers "EventCode": "0x85", 194*f16c3236SIan Rogers "EventName": "ITLB_MISSES.STLB_HIT_2M", 195*f16c3236SIan Rogers "PublicDescription": "ITLB misses that hit STLB (2M).", 196*f16c3236SIan Rogers "SampleAfterValue": "100003", 197*f16c3236SIan Rogers "UMask": "0x40" 198*f16c3236SIan Rogers }, 199*f16c3236SIan Rogers { 200*f16c3236SIan Rogers "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", 201*f16c3236SIan Rogers "EventCode": "0x85", 202*f16c3236SIan Rogers "EventName": "ITLB_MISSES.STLB_HIT_4K", 203*f16c3236SIan Rogers "PublicDescription": "ITLB misses that hit STLB (4K).", 204*f16c3236SIan Rogers "SampleAfterValue": "100003", 205*f16c3236SIan Rogers "UMask": "0x20" 206*f16c3236SIan Rogers }, 207*f16c3236SIan Rogers { 208*f16c3236SIan Rogers "BriefDescription": "Misses in all ITLB levels that cause completed page walks", 209*f16c3236SIan Rogers "EventCode": "0x85", 210*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED", 211*f16c3236SIan Rogers "PublicDescription": "Completed page walks in ITLB of any page size.", 212*f16c3236SIan Rogers "SampleAfterValue": "100003", 213*f16c3236SIan Rogers "UMask": "0xe" 214*f16c3236SIan Rogers }, 215*f16c3236SIan Rogers { 216*f16c3236SIan Rogers "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", 217*f16c3236SIan Rogers "EventCode": "0x85", 218*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", 219*f16c3236SIan Rogers "SampleAfterValue": "100003", 220*f16c3236SIan Rogers "UMask": "0x8" 221*f16c3236SIan Rogers }, 222*f16c3236SIan Rogers { 223*f16c3236SIan Rogers "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 224*f16c3236SIan Rogers "EventCode": "0x85", 225*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 226*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", 227*f16c3236SIan Rogers "SampleAfterValue": "100003", 228*f16c3236SIan Rogers "UMask": "0x4" 229*f16c3236SIan Rogers }, 230*f16c3236SIan Rogers { 231*f16c3236SIan Rogers "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 232*f16c3236SIan Rogers "EventCode": "0x85", 233*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 234*f16c3236SIan Rogers "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", 235*f16c3236SIan Rogers "SampleAfterValue": "100003", 236*f16c3236SIan Rogers "UMask": "0x2" 237*f16c3236SIan Rogers }, 238*f16c3236SIan Rogers { 239*f16c3236SIan Rogers "BriefDescription": "Cycles when PMH is busy with page walks", 240*f16c3236SIan Rogers "EventCode": "0x85", 241*f16c3236SIan Rogers "EventName": "ITLB_MISSES.WALK_DURATION", 242*f16c3236SIan Rogers "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", 243*f16c3236SIan Rogers "SampleAfterValue": "100003", 244*f16c3236SIan Rogers "UMask": "0x10" 245*f16c3236SIan Rogers }, 246*f16c3236SIan Rogers { 247ede00740SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in the L1+FB", 248*f16c3236SIan Rogers "EventCode": "0xBC", 249ede00740SAndi Kleen "EventName": "PAGE_WALKER_LOADS.DTLB_L1", 250ede00740SAndi Kleen "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", 251ede00740SAndi Kleen "SampleAfterValue": "2000003", 252*f16c3236SIan Rogers "UMask": "0x11" 253ede00740SAndi Kleen }, 254ede00740SAndi Kleen { 255ede00740SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in the L2", 256*f16c3236SIan Rogers "EventCode": "0xBC", 257ede00740SAndi Kleen "EventName": "PAGE_WALKER_LOADS.DTLB_L2", 258ede00740SAndi Kleen "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", 259ede00740SAndi Kleen "SampleAfterValue": "2000003", 260*f16c3236SIan Rogers "UMask": "0x12" 261ede00740SAndi Kleen }, 262ede00740SAndi Kleen { 263ede00740SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", 264ede00740SAndi Kleen "Errata": "HSD25", 265*f16c3236SIan Rogers "EventCode": "0xBC", 266*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.DTLB_L3", 267ede00740SAndi Kleen "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", 268ede00740SAndi Kleen "SampleAfterValue": "2000003", 269*f16c3236SIan Rogers "UMask": "0x14" 270ede00740SAndi Kleen }, 271ede00740SAndi Kleen { 272ede00740SAndi Kleen "BriefDescription": "Number of DTLB page walker hits in Memory", 273ede00740SAndi Kleen "Errata": "HSD25", 274*f16c3236SIan Rogers "EventCode": "0xBC", 275*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", 276ede00740SAndi Kleen "PublicDescription": "Number of DTLB page walker loads from memory.", 277ede00740SAndi Kleen "SampleAfterValue": "2000003", 278*f16c3236SIan Rogers "UMask": "0x18" 279ede00740SAndi Kleen }, 280ede00740SAndi Kleen { 281*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", 282ede00740SAndi Kleen "EventCode": "0xBC", 283*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", 284*f16c3236SIan Rogers "SampleAfterValue": "2000003", 285*f16c3236SIan Rogers "UMask": "0x41" 286*f16c3236SIan Rogers }, 287*f16c3236SIan Rogers { 288*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", 289*f16c3236SIan Rogers "EventCode": "0xBC", 290*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", 291*f16c3236SIan Rogers "SampleAfterValue": "2000003", 292*f16c3236SIan Rogers "UMask": "0x42" 293*f16c3236SIan Rogers }, 294*f16c3236SIan Rogers { 295*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", 296*f16c3236SIan Rogers "EventCode": "0xBC", 297*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", 298*f16c3236SIan Rogers "SampleAfterValue": "2000003", 299*f16c3236SIan Rogers "UMask": "0x44" 300*f16c3236SIan Rogers }, 301*f16c3236SIan Rogers { 302*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", 303*f16c3236SIan Rogers "EventCode": "0xBC", 304*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", 305*f16c3236SIan Rogers "SampleAfterValue": "2000003", 306*f16c3236SIan Rogers "UMask": "0x48" 307*f16c3236SIan Rogers }, 308*f16c3236SIan Rogers { 309*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", 310*f16c3236SIan Rogers "EventCode": "0xBC", 311*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", 312*f16c3236SIan Rogers "SampleAfterValue": "2000003", 313*f16c3236SIan Rogers "UMask": "0x81" 314*f16c3236SIan Rogers }, 315*f16c3236SIan Rogers { 316*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 317*f16c3236SIan Rogers "EventCode": "0xBC", 318*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", 319*f16c3236SIan Rogers "SampleAfterValue": "2000003", 320*f16c3236SIan Rogers "UMask": "0x82" 321*f16c3236SIan Rogers }, 322*f16c3236SIan Rogers { 323*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 324*f16c3236SIan Rogers "EventCode": "0xBC", 325*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", 326*f16c3236SIan Rogers "SampleAfterValue": "2000003", 327*f16c3236SIan Rogers "UMask": "0x84" 328*f16c3236SIan Rogers }, 329*f16c3236SIan Rogers { 330*f16c3236SIan Rogers "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", 331*f16c3236SIan Rogers "EventCode": "0xBC", 332*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", 333*f16c3236SIan Rogers "SampleAfterValue": "2000003", 334*f16c3236SIan Rogers "UMask": "0x88" 335*f16c3236SIan Rogers }, 336*f16c3236SIan Rogers { 337032c16b2SAndi Kleen "BriefDescription": "Number of ITLB page walker hits in the L1+FB", 338*f16c3236SIan Rogers "EventCode": "0xBC", 339032c16b2SAndi Kleen "EventName": "PAGE_WALKER_LOADS.ITLB_L1", 340032c16b2SAndi Kleen "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", 341032c16b2SAndi Kleen "SampleAfterValue": "2000003", 342*f16c3236SIan Rogers "UMask": "0x21" 343032c16b2SAndi Kleen }, 344032c16b2SAndi Kleen { 345032c16b2SAndi Kleen "BriefDescription": "Number of ITLB page walker hits in the L2", 346*f16c3236SIan Rogers "EventCode": "0xBC", 347032c16b2SAndi Kleen "EventName": "PAGE_WALKER_LOADS.ITLB_L2", 348032c16b2SAndi Kleen "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", 349032c16b2SAndi Kleen "SampleAfterValue": "2000003", 350*f16c3236SIan Rogers "UMask": "0x22" 351032c16b2SAndi Kleen }, 352032c16b2SAndi Kleen { 353032c16b2SAndi Kleen "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", 354032c16b2SAndi Kleen "Errata": "HSD25", 355*f16c3236SIan Rogers "EventCode": "0xBC", 356*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.ITLB_L3", 357032c16b2SAndi Kleen "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", 358032c16b2SAndi Kleen "SampleAfterValue": "2000003", 359*f16c3236SIan Rogers "UMask": "0x24" 360032c16b2SAndi Kleen }, 361032c16b2SAndi Kleen { 362ede00740SAndi Kleen "BriefDescription": "Number of ITLB page walker hits in Memory", 363ede00740SAndi Kleen "Errata": "HSD25", 364*f16c3236SIan Rogers "EventCode": "0xBC", 365*f16c3236SIan Rogers "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", 366ede00740SAndi Kleen "PublicDescription": "Number of ITLB page walker loads from memory.", 367ede00740SAndi Kleen "SampleAfterValue": "2000003", 368*f16c3236SIan Rogers "UMask": "0x28" 369ede00740SAndi Kleen }, 370ede00740SAndi Kleen { 371ede00740SAndi Kleen "BriefDescription": "DTLB flush attempts of the thread-specific entries", 372*f16c3236SIan Rogers "EventCode": "0xBD", 373ede00740SAndi Kleen "EventName": "TLB_FLUSH.DTLB_THREAD", 374ede00740SAndi Kleen "PublicDescription": "DTLB flush attempts of the thread-specific entries.", 375ede00740SAndi Kleen "SampleAfterValue": "100003", 376*f16c3236SIan Rogers "UMask": "0x1" 377ede00740SAndi Kleen }, 378ede00740SAndi Kleen { 379ede00740SAndi Kleen "BriefDescription": "STLB flush attempts", 380*f16c3236SIan Rogers "EventCode": "0xBD", 381ede00740SAndi Kleen "EventName": "TLB_FLUSH.STLB_ANY", 382ede00740SAndi Kleen "PublicDescription": "Count number of STLB flush attempts.", 383ede00740SAndi Kleen "SampleAfterValue": "100003", 384*f16c3236SIan Rogers "UMask": "0x20" 385ede00740SAndi Kleen } 386ede00740SAndi Kleen] 387