1*65844828SSandipan Das[ 2*65844828SSandipan Das { 3*65844828SSandipan Das "EventName": "ls_bad_status2.stli_other", 4*65844828SSandipan Das "EventCode": "0x24", 5*65844828SSandipan Das "BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).", 6*65844828SSandipan Das "UMask": "0x02" 7*65844828SSandipan Das }, 8*65844828SSandipan Das { 9*65844828SSandipan Das "EventName": "ls_dispatch.ld_dispatch", 10*65844828SSandipan Das "EventCode": "0x29", 11*65844828SSandipan Das "BriefDescription": "Number of memory load operations dispatched to the load-store unit.", 12*65844828SSandipan Das "UMask": "0x01" 13*65844828SSandipan Das }, 14*65844828SSandipan Das { 15*65844828SSandipan Das "EventName": "ls_dispatch.store_dispatch", 16*65844828SSandipan Das "EventCode": "0x29", 17*65844828SSandipan Das "BriefDescription": "Number of memory store operations dispatched to the load-store unit.", 18*65844828SSandipan Das "UMask": "0x02" 19*65844828SSandipan Das }, 20*65844828SSandipan Das { 21*65844828SSandipan Das "EventName": "ls_dispatch.ld_st_dispatch", 22*65844828SSandipan Das "EventCode": "0x29", 23*65844828SSandipan Das "BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.", 24*65844828SSandipan Das "UMask": "0x04" 25*65844828SSandipan Das }, 26*65844828SSandipan Das { 27*65844828SSandipan Das "EventName": "ls_stlf", 28*65844828SSandipan Das "EventCode": "0x35", 29*65844828SSandipan Das "BriefDescription": "Store-to-load-forward (STLF) hits." 30*65844828SSandipan Das }, 31*65844828SSandipan Das { 32*65844828SSandipan Das "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full", 33*65844828SSandipan Das "EventCode": "0x37", 34*65844828SSandipan Das "BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.", 35*65844828SSandipan Das "UMask": "0x01" 36*65844828SSandipan Das }, 37*65844828SSandipan Das { 38*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit", 39*65844828SSandipan Das "EventCode": "0x45", 40*65844828SSandipan Das "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.", 41*65844828SSandipan Das "UMask": "0x01" 42*65844828SSandipan Das }, 43*65844828SSandipan Das { 44*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit", 45*65844828SSandipan Das "EventCode": "0x45", 46*65844828SSandipan Das "BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.", 47*65844828SSandipan Das "UMask": "0x02" 48*65844828SSandipan Das }, 49*65844828SSandipan Das { 50*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit", 51*65844828SSandipan Das "EventCode": "0x45", 52*65844828SSandipan Das "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.", 53*65844828SSandipan Das "UMask": "0x04" 54*65844828SSandipan Das }, 55*65844828SSandipan Das { 56*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit", 57*65844828SSandipan Das "EventCode": "0x45", 58*65844828SSandipan Das "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.", 59*65844828SSandipan Das "UMask": "0x08" 60*65844828SSandipan Das }, 61*65844828SSandipan Das { 62*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss", 63*65844828SSandipan Das "EventCode": "0x45", 64*65844828SSandipan Das "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.", 65*65844828SSandipan Das "UMask": "0x10" 66*65844828SSandipan Das }, 67*65844828SSandipan Das { 68*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss", 69*65844828SSandipan Das "EventCode": "0x45", 70*65844828SSandipan Das "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.", 71*65844828SSandipan Das "UMask": "0x20" 72*65844828SSandipan Das }, 73*65844828SSandipan Das { 74*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss", 75*65844828SSandipan Das "EventCode": "0x45", 76*65844828SSandipan Das "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.", 77*65844828SSandipan Das "UMask": "0x40" 78*65844828SSandipan Das }, 79*65844828SSandipan Das { 80*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss", 81*65844828SSandipan Das "EventCode": "0x45", 82*65844828SSandipan Das "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.", 83*65844828SSandipan Das "UMask": "0x80" 84*65844828SSandipan Das }, 85*65844828SSandipan Das { 86*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.all_l2_miss", 87*65844828SSandipan Das "EventCode": "0x45", 88*65844828SSandipan Das "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.", 89*65844828SSandipan Das "UMask": "0xf0" 90*65844828SSandipan Das }, 91*65844828SSandipan Das { 92*65844828SSandipan Das "EventName": "ls_l1_d_tlb_miss.all", 93*65844828SSandipan Das "EventCode": "0x45", 94*65844828SSandipan Das "BriefDescription": "L1 DTLB misses for all page sizes.", 95*65844828SSandipan Das "UMask": "0xff" 96*65844828SSandipan Das }, 97*65844828SSandipan Das { 98*65844828SSandipan Das "EventName": "ls_misal_loads.ma64", 99*65844828SSandipan Das "EventCode": "0x47", 100*65844828SSandipan Das "BriefDescription": "64B misaligned (cacheline crossing) loads.", 101*65844828SSandipan Das "UMask": "0x01" 102*65844828SSandipan Das }, 103*65844828SSandipan Das { 104*65844828SSandipan Das "EventName": "ls_misal_loads.ma4k", 105*65844828SSandipan Das "EventCode": "0x47", 106*65844828SSandipan Das "BriefDescription": "4kB misaligned (page crossing) loads.", 107*65844828SSandipan Das "UMask": "0x02" 108*65844828SSandipan Das }, 109*65844828SSandipan Das { 110*65844828SSandipan Das "EventName": "ls_tlb_flush.all", 111*65844828SSandipan Das "EventCode": "0x78", 112*65844828SSandipan Das "BriefDescription": "All TLB Flushes.", 113*65844828SSandipan Das "UMask": "0xff" 114*65844828SSandipan Das }, 115*65844828SSandipan Das { 116*65844828SSandipan Das "EventName": "bp_l1_tlb_miss_l2_tlb_hit", 117*65844828SSandipan Das "EventCode": "0x84", 118*65844828SSandipan Das "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB." 119*65844828SSandipan Das }, 120*65844828SSandipan Das { 121*65844828SSandipan Das "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k", 122*65844828SSandipan Das "EventCode": "0x85", 123*65844828SSandipan Das "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.", 124*65844828SSandipan Das "UMask": "0x01" 125*65844828SSandipan Das }, 126*65844828SSandipan Das { 127*65844828SSandipan Das "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m", 128*65844828SSandipan Das "EventCode": "0x85", 129*65844828SSandipan Das "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.", 130*65844828SSandipan Das "UMask": "0x02" 131*65844828SSandipan Das }, 132*65844828SSandipan Das { 133*65844828SSandipan Das "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g", 134*65844828SSandipan Das "EventCode": "0x85", 135*65844828SSandipan Das "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.", 136*65844828SSandipan Das "UMask": "0x04" 137*65844828SSandipan Das }, 138*65844828SSandipan Das { 139*65844828SSandipan Das "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k", 140*65844828SSandipan Das "EventCode": "0x85", 141*65844828SSandipan Das "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.", 142*65844828SSandipan Das "UMask": "0x08" 143*65844828SSandipan Das }, 144*65844828SSandipan Das { 145*65844828SSandipan Das "EventName": "bp_l1_tlb_miss_l2_tlb_miss.all", 146*65844828SSandipan Das "EventCode": "0x85", 147*65844828SSandipan Das "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.", 148*65844828SSandipan Das "UMask": "0x0f" 149*65844828SSandipan Das }, 150*65844828SSandipan Das { 151*65844828SSandipan Das "EventName": "bp_l1_tlb_fetch_hit.if4k", 152*65844828SSandipan Das "EventCode": "0x94", 153*65844828SSandipan Das "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.", 154*65844828SSandipan Das "UMask": "0x01" 155*65844828SSandipan Das }, 156*65844828SSandipan Das { 157*65844828SSandipan Das "EventName": "bp_l1_tlb_fetch_hit.if2m", 158*65844828SSandipan Das "EventCode": "0x94", 159*65844828SSandipan Das "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.", 160*65844828SSandipan Das "UMask": "0x02" 161*65844828SSandipan Das }, 162*65844828SSandipan Das { 163*65844828SSandipan Das "EventName": "bp_l1_tlb_fetch_hit.if1g", 164*65844828SSandipan Das "EventCode": "0x94", 165*65844828SSandipan Das "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.", 166*65844828SSandipan Das "UMask": "0x04" 167*65844828SSandipan Das }, 168*65844828SSandipan Das { 169*65844828SSandipan Das "EventName": "bp_l1_tlb_fetch_hit.all", 170*65844828SSandipan Das "EventCode": "0x94", 171*65844828SSandipan Das "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.", 172*65844828SSandipan Das "UMask": "0x07" 173*65844828SSandipan Das } 174*65844828SSandipan Das] 175