132daa5d7SKajol Jain[ 232daa5d7SKajol Jain { 38fc4e4aaSKajol Jain "EventCode": "0x1C040", 432daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC1", 532daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 632daa5d7SKajol Jain }, 732daa5d7SKajol Jain { 88fc4e4aaSKajol Jain "EventCode": "0x1C056", 932daa5d7SKajol Jain "EventName": "PM_DERAT_MISS_4K", 1032daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 1132daa5d7SKajol Jain }, 1232daa5d7SKajol Jain { 138fc4e4aaSKajol Jain "EventCode": "0x1C058", 1432daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_16G", 1532daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 1632daa5d7SKajol Jain }, 1732daa5d7SKajol Jain { 188fc4e4aaSKajol Jain "EventCode": "0x1C05C", 1932daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_2M", 2032daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 2132daa5d7SKajol Jain }, 2232daa5d7SKajol Jain { 238fc4e4aaSKajol Jain "EventCode": "0x10062", 2432daa5d7SKajol Jain "EventName": "PM_LD_L3MISS_PEND_CYC", 253286f88fSKajol Jain "BriefDescription": "Cycles in which an L3 miss was pending for this thread." 2632daa5d7SKajol Jain }, 2732daa5d7SKajol Jain { 288fc4e4aaSKajol Jain "EventCode": "0x2001A", 2932daa5d7SKajol Jain "EventName": "PM_ITLB_HIT", 3032daa5d7SKajol Jain "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches." 3132daa5d7SKajol Jain }, 3232daa5d7SKajol Jain { 338fc4e4aaSKajol Jain "EventCode": "0x2003E", 3432daa5d7SKajol Jain "EventName": "PM_PTESYNC_FIN", 3532daa5d7SKajol Jain "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time." 3632daa5d7SKajol Jain }, 3732daa5d7SKajol Jain { 388fc4e4aaSKajol Jain "EventCode": "0x2C040", 3932daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC2", 4032daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 4132daa5d7SKajol Jain }, 4232daa5d7SKajol Jain { 438fc4e4aaSKajol Jain "EventCode": "0x2C054", 4432daa5d7SKajol Jain "EventName": "PM_DERAT_MISS_64K", 4532daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 4632daa5d7SKajol Jain }, 4732daa5d7SKajol Jain { 488fc4e4aaSKajol Jain "EventCode": "0x2C056", 4932daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_4K", 5032daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 5132daa5d7SKajol Jain }, 5232daa5d7SKajol Jain { 53*426c804bSKajol Jain "EventCode": "0x2C05A", 54*426c804bSKajol Jain "EventName": "PM_DERAT_MISS_1G", 55*426c804bSKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 56*426c804bSKajol Jain }, 57*426c804bSKajol Jain { 588fc4e4aaSKajol Jain "EventCode": "0x200F6", 5932daa5d7SKajol Jain "EventName": "PM_DERAT_MISS", 6032daa5d7SKajol Jain "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 6132daa5d7SKajol Jain }, 6232daa5d7SKajol Jain { 63*426c804bSKajol Jain "EventCode": "0x34044", 64*426c804bSKajol Jain "EventName": "PM_DERAT_MISS_PREF", 65*426c804bSKajol Jain "BriefDescription": "DERAT miss (TLB access) while servicing a data prefetch." 66*426c804bSKajol Jain }, 67*426c804bSKajol Jain { 688fc4e4aaSKajol Jain "EventCode": "0x3C040", 6932daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC3", 7032daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 7132daa5d7SKajol Jain }, 7232daa5d7SKajol Jain { 738fc4e4aaSKajol Jain "EventCode": "0x3C054", 7432daa5d7SKajol Jain "EventName": "PM_DERAT_MISS_16M", 7532daa5d7SKajol Jain "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 7632daa5d7SKajol Jain }, 7732daa5d7SKajol Jain { 788fc4e4aaSKajol Jain "EventCode": "0x3C056", 7932daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_64K", 8032daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 8132daa5d7SKajol Jain }, 8232daa5d7SKajol Jain { 838fc4e4aaSKajol Jain "EventCode": "0x3C058", 8432daa5d7SKajol Jain "EventName": "PM_LARX_FIN", 8532daa5d7SKajol Jain "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock." 8632daa5d7SKajol Jain }, 8732daa5d7SKajol Jain { 888fc4e4aaSKajol Jain "EventCode": "0x300FC", 8932daa5d7SKajol Jain "EventName": "PM_DTLB_MISS", 903286f88fSKajol Jain "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. This event only counts for demand misses." 9132daa5d7SKajol Jain }, 9232daa5d7SKajol Jain { 938fc4e4aaSKajol Jain "EventCode": "0x4003E", 9432daa5d7SKajol Jain "EventName": "PM_LD_CMPL", 953286f88fSKajol Jain "BriefDescription": "Load instruction completed." 9632daa5d7SKajol Jain }, 9732daa5d7SKajol Jain { 988fc4e4aaSKajol Jain "EventCode": "0x4C040", 9932daa5d7SKajol Jain "EventName": "PM_XFER_FROM_SRC_PMC4", 10032daa5d7SKajol Jain "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads." 10132daa5d7SKajol Jain }, 10232daa5d7SKajol Jain { 1038fc4e4aaSKajol Jain "EventCode": "0x4C056", 10432daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_16M", 10532daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 10632daa5d7SKajol Jain }, 10732daa5d7SKajol Jain { 1088fc4e4aaSKajol Jain "EventCode": "0x4C05A", 10932daa5d7SKajol Jain "EventName": "PM_DTLB_MISS_1G", 11032daa5d7SKajol Jain "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches." 11132daa5d7SKajol Jain } 11232daa5d7SKajol Jain] 113