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/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Difu.json3 "PublicDescription": "I-Cache miss on an access from the prefetch block",
6 "BriefDescription": "I-Cache miss on an access from the prefetch block"
9 …"PublicDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l…
12 …"BriefDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l …
15 …"PublicDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 p…
18 …"BriefDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 pr…
21 … "PublicDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor",
24 "BriefDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor"
27 "PublicDescription": "Micro-predictor hit with immediate redirect",
30 "BriefDescription": "Micro-predictor hit with immediate redirect"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Dcache.json111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
129 "PublicDescription": "Level 1 PLD TLB refill",
132 "BriefDescription": "Level 1 PLD TLB refill"
135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa…
138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar…
141 "PublicDescription": "Level 1 TLB flush",
144 "BriefDescription": "Level 1 TLB flush"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A Dmetrics.json12 "BriefDescription": "Core-to-uncore bus utilization",
89 "BriefDescription": "Giga-floating point operations per second",
156 … "BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)",
162 "MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))",
163 "BriefDescription": "Of all the micro-operations issued, what proportion are lost",
169 "MetricExpr": "1 - OP_RETIRED / OP_SPEC",
170 …"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed…
191 …"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss…
205 "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss",
212 …s the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication o…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
H A Dpipeline.json10 … DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre…
20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p…
25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc…
40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A Dmetrics.json4 …"MetricExpr": "(100 * ((STALL_SLOT_BACKEND / (CPU_CYCLES * #slots)) - ((BR_MIS_PRED * 3) / CPU_CYC…
15 …0 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (((STALL_SLOT) if (strcmp_cpuid_str(0x410fd493) | strcmp…
48 …"BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions e…
55 …s the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication o…
57 "ScaleUnit": "1per TLB access"
61 …mp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT_FRONTEND - CPU_CYCLES)) / (CPU_CYCLES * #slots)) - …
87 …"BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instruc…
94 … instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication o…
96 "ScaleUnit": "1per TLB access"
115 …1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indicat…
[all …]
/openbmc/linux/arch/powerpc/platforms/8xx/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
42 bool "Analogue & Micro Adder 875"
45 This enables support for the Analogue & Micro Adder 875
56 menu "Freescale Ethernet driver platform-specific options"
76 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
77 (often 2-nd UART) will not work if this is enabled.
83 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
84 (often 1-nd UART) will not work if this is enabled.
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/
H A Dcommon-and-microarch.json15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
129 "PublicDescription": "Attributable Level 1 data cache write-back",
132 "BriefDescription": "Attributable Level 1 data cache write-back"
147 "PublicDescription": "Attributable Level 2 data cache write-back",
150 "BriefDescription": "Attributable Level 2 data cache write-back"
219 "PublicDescription": "Attributable Level 1 data or unified TLB access",
222 "BriefDescription": "Attributable Level 1 data or unified TLB access"
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dperf_event_v6.c1 // SPDX-License-Identifier: GPL-2.0
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
19 * - disable the counter's interrupt generation (each counter has it's
24 * - enable the counter's interrupt generation.
25 * - set the new event type.
30 * ignoring that counter. When re-enabling, we have to reset the value and
104 * The ARM performance counters can count micro DTLB misses, micro ITLB
105 * misses and main TLB misses. There isn't an event for TLB misses, so
106 * use the micro misses here and if users want the main TLB misses they
167 * The ARM performance counters can count micro DTLB misses, micro ITLB
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/openbmc/linux/tools/perf/Documentation/
H A Dperf-arm-spe.txt1 perf-arm-spe(1)
5 ----
6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools
9 --------
11 'perf record' -e arm_spe//
14 -----------
17 events down to individual instructions. Rather than being interrupt-driven, it picks an
33 architectural instructions or all micro-ops. Sampling happens at a programmable interval. The
35 sample. This minimum interval is used by the driver if no interval is specified. A pseudo-random
62 ----------------
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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Drenesas,ipmmu-vmsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VMSA-Compatible IOMMU
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 connected to the IPMMU through a port called micro-TLB.
20 - items:
21 - enum:
22 - renesas,ipmmu-r8a73a4 # R-Mobile APE6
[all …]
H A Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
21 here, there must be a corresponding entry in clock-names
[all …]
/openbmc/linux/arch/mips/mm/
H A Dtlb-funcs.S6 * Micro-assembler generated tlb handler functions.
10 * Based on mm/page-funcs.c
12 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
/openbmc/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Djkt-metrics.json4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
75 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
80 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dsnb-metrics.json4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
75 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
80 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
[all …]
/openbmc/libcper/include/libcper/sections/
H A Dcper-section-generic.h19 (const char *[]){ "Unknown", "Cache Error", "TLB Error", "Bus Error", \
20 "Micro-Architectural Error" }
/openbmc/linux/drivers/edac/
H A Dmce_amd.c1 // SPDX-License-Identifier: GPL-2.0-only
71 "PFB non-cacheable bit parity error",
101 "Link-defined sync error packets detected on HT link",
151 "Level 1 TLB parity error",
164 "Level 2 TLB parity error",
174 "An ECC error was detected on a data cache read-modify-write by a store",
179 "An ECC error was detected on an EMEM read-modify-write by a store",
180 "A parity error was detected in an L1 TLB entry by any access",
181 "A parity error was detected in an L2 TLB entry by any access",
200 "IC Microtag or Full Tag Multi-hit Error",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A Drecommended.json4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
119 "MetricGroup": "tlb"
148 "BriefDescription": "Micro-ops Dispatched",
160 "BriefDescription": "Micro-ops Retired"
168 "ScaleUnit": "3e-5MiB"
177 "ScaleUnit": "6.1e-5MiB"
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Drecommended.json4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
119 "MetricGroup": "tlb"
148 "BriefDescription": "Micro-ops Dispatched",
160 "BriefDescription": "Micro-ops Retired"
168 "ScaleUnit": "3e-5MiB"
177 "ScaleUnit": "6.1e-5MiB"
/openbmc/linux/arch/arc/mm/
H A Dtlbex.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a seperate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
14 * entry, so that it doesn't knock out it's I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Dhsx-metrics.json4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
79 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
86 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
105 …plies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Dskl-metrics.json4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
95 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Dicx-metrics.json4 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
18 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
25 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
58 …This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
65 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
72 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
85 …plies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
92 …ted instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
240 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Dclx-metrics.json4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
79 …This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
86 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
93 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Dskx-metrics.json4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
79 …This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
86 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
93 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Dbdx-metrics.json4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
79 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
86 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
105 …plies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
[all …]

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