128bc0ddbSAndi Kleen[ 228bc0ddbSAndi Kleen { 35c3f73c1SIan Rogers "BriefDescription": "C2 residency percent per package", 45c3f73c1SIan Rogers "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", 528bc0ddbSAndi Kleen "MetricGroup": "Power", 65c3f73c1SIan Rogers "MetricName": "C2_Pkg_Residency", 75c3f73c1SIan Rogers "ScaleUnit": "100%" 8e85af8a6SIan Rogers }, 9e85af8a6SIan Rogers { 1061ec07f5SHaiyan Song "BriefDescription": "C3 residency percent per core", 11e85af8a6SIan Rogers "MetricExpr": "cstate_core@c3\\-residency@ / TSC", 1228bc0ddbSAndi Kleen "MetricGroup": "Power", 13e85af8a6SIan Rogers "MetricName": "C3_Core_Residency", 14e85af8a6SIan Rogers "ScaleUnit": "100%" 1528bc0ddbSAndi Kleen }, 1628bc0ddbSAndi Kleen { 1761ec07f5SHaiyan Song "BriefDescription": "C3 residency percent per package", 18e85af8a6SIan Rogers "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", 1928bc0ddbSAndi Kleen "MetricGroup": "Power", 20e85af8a6SIan Rogers "MetricName": "C3_Pkg_Residency", 21e85af8a6SIan Rogers "ScaleUnit": "100%" 2228bc0ddbSAndi Kleen }, 2328bc0ddbSAndi Kleen { 245c3f73c1SIan Rogers "BriefDescription": "C6 residency percent per core", 255c3f73c1SIan Rogers "MetricExpr": "cstate_core@c6\\-residency@ / TSC", 265c3f73c1SIan Rogers "MetricGroup": "Power", 275c3f73c1SIan Rogers "MetricName": "C6_Core_Residency", 285c3f73c1SIan Rogers "ScaleUnit": "100%" 295c3f73c1SIan Rogers }, 305c3f73c1SIan Rogers { 3161ec07f5SHaiyan Song "BriefDescription": "C6 residency percent per package", 32e85af8a6SIan Rogers "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", 3328bc0ddbSAndi Kleen "MetricGroup": "Power", 34e85af8a6SIan Rogers "MetricName": "C6_Pkg_Residency", 35e85af8a6SIan Rogers "ScaleUnit": "100%" 3628bc0ddbSAndi Kleen }, 3728bc0ddbSAndi Kleen { 385c3f73c1SIan Rogers "BriefDescription": "C7 residency percent per core", 395c3f73c1SIan Rogers "MetricExpr": "cstate_core@c7\\-residency@ / TSC", 405c3f73c1SIan Rogers "MetricGroup": "Power", 415c3f73c1SIan Rogers "MetricName": "C7_Core_Residency", 425c3f73c1SIan Rogers "ScaleUnit": "100%" 435c3f73c1SIan Rogers }, 445c3f73c1SIan Rogers { 4561ec07f5SHaiyan Song "BriefDescription": "C7 residency percent per package", 46e85af8a6SIan Rogers "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", 4728bc0ddbSAndi Kleen "MetricGroup": "Power", 48e85af8a6SIan Rogers "MetricName": "C7_Pkg_Residency", 49e85af8a6SIan Rogers "ScaleUnit": "100%" 505c3f73c1SIan Rogers }, 515c3f73c1SIan Rogers { 525c3f73c1SIan Rogers "BriefDescription": "Uncore frequency per die [GHZ]", 53*e08d2ae9SIan Rogers "MetricExpr": "tma_info_system_socket_clks / #num_dies / duration_time / 1e9", 545c3f73c1SIan Rogers "MetricGroup": "SoC", 555c3f73c1SIan Rogers "MetricName": "UNCORE_FREQ" 565c3f73c1SIan Rogers }, 575c3f73c1SIan Rogers { 585c3f73c1SIan Rogers "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", 595c3f73c1SIan Rogers "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", 605c3f73c1SIan Rogers "MetricGroup": "smi", 615c3f73c1SIan Rogers "MetricName": "smi_cycles", 625c3f73c1SIan Rogers "MetricThreshold": "smi_cycles > 0.1", 635c3f73c1SIan Rogers "ScaleUnit": "100%" 645c3f73c1SIan Rogers }, 655c3f73c1SIan Rogers { 665c3f73c1SIan Rogers "BriefDescription": "Number of SMI interrupts.", 675c3f73c1SIan Rogers "MetricExpr": "msr@smi@", 685c3f73c1SIan Rogers "MetricGroup": "smi", 695c3f73c1SIan Rogers "MetricName": "smi_num", 705c3f73c1SIan Rogers "ScaleUnit": "1SMI#" 715c3f73c1SIan Rogers }, 725c3f73c1SIan Rogers { 735c3f73c1SIan Rogers "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", 745c3f73c1SIan Rogers "MetricConstraint": "NO_GROUP_EVENTS_NMI", 755c3f73c1SIan Rogers "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", 765c3f73c1SIan Rogers "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 775c3f73c1SIan Rogers "MetricName": "tma_backend_bound", 785c3f73c1SIan Rogers "MetricThreshold": "tma_backend_bound > 0.2", 79ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL1", 805c3f73c1SIan Rogers "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", 815c3f73c1SIan Rogers "ScaleUnit": "100%" 825c3f73c1SIan Rogers }, 835c3f73c1SIan Rogers { 845c3f73c1SIan Rogers "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", 85*e08d2ae9SIan Rogers "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots", 865c3f73c1SIan Rogers "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 875c3f73c1SIan Rogers "MetricName": "tma_bad_speculation", 885c3f73c1SIan Rogers "MetricThreshold": "tma_bad_speculation > 0.15", 89ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL1", 905c3f73c1SIan Rogers "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 915c3f73c1SIan Rogers "ScaleUnit": "100%" 925c3f73c1SIan Rogers }, 935c3f73c1SIan Rogers { 945c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", 955c3f73c1SIan Rogers "MetricConstraint": "NO_GROUP_EVENTS", 965c3f73c1SIan Rogers "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", 975c3f73c1SIan Rogers "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 985c3f73c1SIan Rogers "MetricName": "tma_branch_mispredicts", 995c3f73c1SIan Rogers "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 100ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL2", 101*e08d2ae9SIan Rogers "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers", 1025c3f73c1SIan Rogers "ScaleUnit": "100%" 1035c3f73c1SIan Rogers }, 1045c3f73c1SIan Rogers { 1055c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", 106*e08d2ae9SIan Rogers "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_thread_clks", 1075c3f73c1SIan Rogers "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", 1085c3f73c1SIan Rogers "MetricName": "tma_branch_resteers", 1095c3f73c1SIan Rogers "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 1105c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", 1115c3f73c1SIan Rogers "ScaleUnit": "100%" 1125c3f73c1SIan Rogers }, 1135c3f73c1SIan Rogers { 1145c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", 1155c3f73c1SIan Rogers "MetricConstraint": "NO_GROUP_EVENTS", 1165c3f73c1SIan Rogers "MetricExpr": "tma_backend_bound - tma_memory_bound", 1175c3f73c1SIan Rogers "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 1185c3f73c1SIan Rogers "MetricName": "tma_core_bound", 1195c3f73c1SIan Rogers "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 120ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL2", 1215c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 1225c3f73c1SIan Rogers "ScaleUnit": "100%" 1235c3f73c1SIan Rogers }, 1245c3f73c1SIan Rogers { 1255c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", 126*e08d2ae9SIan Rogers "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks", 1275c3f73c1SIan Rogers "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", 1285c3f73c1SIan Rogers "MetricName": "tma_divider", 1295c3f73c1SIan Rogers "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", 1305c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", 1315c3f73c1SIan Rogers "ScaleUnit": "100%" 1325c3f73c1SIan Rogers }, 1335c3f73c1SIan Rogers { 1345c3f73c1SIan Rogers "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", 1355c3f73c1SIan Rogers "MetricConstraint": "NO_GROUP_EVENTS_SMT", 136*e08d2ae9SIan Rogers "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks", 1375c3f73c1SIan Rogers "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", 1385c3f73c1SIan Rogers "MetricName": "tma_dram_bound", 1395c3f73c1SIan Rogers "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", 1405c3f73c1SIan Rogers "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", 1415c3f73c1SIan Rogers "ScaleUnit": "100%" 1425c3f73c1SIan Rogers }, 1435c3f73c1SIan Rogers { 1445c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", 145*e08d2ae9SIan Rogers "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks", 1465c3f73c1SIan Rogers "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", 1475c3f73c1SIan Rogers "MetricName": "tma_dsb_switches", 1485c3f73c1SIan Rogers "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 149*e08d2ae9SIan Rogers "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_lcp", 1505c3f73c1SIan Rogers "ScaleUnit": "100%" 1515c3f73c1SIan Rogers }, 1525c3f73c1SIan Rogers { 1535c3f73c1SIan Rogers "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", 154*e08d2ae9SIan Rogers "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_thread_clks", 1555c3f73c1SIan Rogers "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", 1565c3f73c1SIan Rogers "MetricName": "tma_dtlb_load", 1575c3f73c1SIan Rogers "MetricThreshold": "tma_dtlb_load > 0.1", 1585c3f73c1SIan Rogers "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", 1595c3f73c1SIan Rogers "ScaleUnit": "100%" 1605c3f73c1SIan Rogers }, 1615c3f73c1SIan Rogers { 1625c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", 1635c3f73c1SIan Rogers "MetricExpr": "tma_frontend_bound - tma_fetch_latency", 1645c3f73c1SIan Rogers "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 1655c3f73c1SIan Rogers "MetricName": "tma_fetch_bandwidth", 166*e08d2ae9SIan Rogers "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 4 > 0.35", 167ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL2", 168*e08d2ae9SIan Rogers "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_frontend_dsb_coverage, tma_lcp", 1695c3f73c1SIan Rogers "ScaleUnit": "100%" 1705c3f73c1SIan Rogers }, 1715c3f73c1SIan Rogers { 1725c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", 173*e08d2ae9SIan Rogers "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_thread_slots", 1745c3f73c1SIan Rogers "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 1755c3f73c1SIan Rogers "MetricName": "tma_fetch_latency", 1765c3f73c1SIan Rogers "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 177ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL2", 1785c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", 1795c3f73c1SIan Rogers "ScaleUnit": "100%" 1805c3f73c1SIan Rogers }, 1815c3f73c1SIan Rogers { 1825c3f73c1SIan Rogers "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", 1835c3f73c1SIan Rogers "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", 1845c3f73c1SIan Rogers "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", 1855c3f73c1SIan Rogers "MetricName": "tma_fp_arith", 1865c3f73c1SIan Rogers "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", 1875c3f73c1SIan Rogers "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", 1885c3f73c1SIan Rogers "ScaleUnit": "100%" 1895c3f73c1SIan Rogers }, 1905c3f73c1SIan Rogers { 1915c3f73c1SIan Rogers "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", 1925c3f73c1SIan Rogers "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_DISPATCHED.THREAD", 1935c3f73c1SIan Rogers "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", 1945c3f73c1SIan Rogers "MetricName": "tma_fp_scalar", 1955c3f73c1SIan Rogers "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", 1965c3f73c1SIan Rogers "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2", 1975c3f73c1SIan Rogers "ScaleUnit": "100%" 1985c3f73c1SIan Rogers }, 1995c3f73c1SIan Rogers { 2005c3f73c1SIan Rogers "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", 2015c3f73c1SIan Rogers "MetricExpr": "(FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_DISPATCHED.THREAD", 2025c3f73c1SIan Rogers "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", 2035c3f73c1SIan Rogers "MetricName": "tma_fp_vector", 2045c3f73c1SIan Rogers "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", 2055c3f73c1SIan Rogers "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2", 2065c3f73c1SIan Rogers "ScaleUnit": "100%" 2075c3f73c1SIan Rogers }, 2085c3f73c1SIan Rogers { 2095c3f73c1SIan Rogers "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", 210*e08d2ae9SIan Rogers "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots", 2115c3f73c1SIan Rogers "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", 2125c3f73c1SIan Rogers "MetricName": "tma_frontend_bound", 2135c3f73c1SIan Rogers "MetricThreshold": "tma_frontend_bound > 0.15", 214ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL1", 2155c3f73c1SIan Rogers "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", 2165c3f73c1SIan Rogers "ScaleUnit": "100%" 2175c3f73c1SIan Rogers }, 2185c3f73c1SIan Rogers { 2195c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", 2205c3f73c1SIan Rogers "MetricExpr": "tma_microcode_sequencer", 2215c3f73c1SIan Rogers "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 2225c3f73c1SIan Rogers "MetricName": "tma_heavy_operations", 2235c3f73c1SIan Rogers "MetricThreshold": "tma_heavy_operations > 0.1", 224ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL2", 2255c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 2265c3f73c1SIan Rogers "ScaleUnit": "100%" 2275c3f73c1SIan Rogers }, 2285c3f73c1SIan Rogers { 2295c3f73c1SIan Rogers "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", 230*e08d2ae9SIan Rogers "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_thread_clks))", 2315c3f73c1SIan Rogers "MetricGroup": "SMT", 232*e08d2ae9SIan Rogers "MetricName": "tma_info_core_core_clks" 2335c3f73c1SIan Rogers }, 2345c3f73c1SIan Rogers { 2355c3f73c1SIan Rogers "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", 236*e08d2ae9SIan Rogers "MetricExpr": "INST_RETIRED.ANY / tma_info_core_core_clks", 2375c3f73c1SIan Rogers "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", 238*e08d2ae9SIan Rogers "MetricName": "tma_info_core_coreipc" 2395c3f73c1SIan Rogers }, 2405c3f73c1SIan Rogers { 2415c3f73c1SIan Rogers "BriefDescription": "Floating Point Operations Per Cycle", 242*e08d2ae9SIan Rogers "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / tma_info_core_core_clks", 2435c3f73c1SIan Rogers "MetricGroup": "Flops;Ret", 244*e08d2ae9SIan Rogers "MetricName": "tma_info_core_flopc" 2455c3f73c1SIan Rogers }, 2465c3f73c1SIan Rogers { 2475c3f73c1SIan Rogers "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", 2485c3f73c1SIan Rogers "MetricExpr": "UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)", 2495c3f73c1SIan Rogers "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", 250*e08d2ae9SIan Rogers "MetricName": "tma_info_core_ilp" 251*e08d2ae9SIan Rogers }, 252*e08d2ae9SIan Rogers { 253*e08d2ae9SIan Rogers "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", 254*e08d2ae9SIan Rogers "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", 255*e08d2ae9SIan Rogers "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", 256*e08d2ae9SIan Rogers "MetricName": "tma_info_frontend_dsb_coverage", 257*e08d2ae9SIan Rogers "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35", 258*e08d2ae9SIan Rogers "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_lcp" 2595c3f73c1SIan Rogers }, 2605c3f73c1SIan Rogers { 2615c3f73c1SIan Rogers "BriefDescription": "Total number of retired Instructions", 2625c3f73c1SIan Rogers "MetricExpr": "INST_RETIRED.ANY", 2635c3f73c1SIan Rogers "MetricGroup": "Summary;TmaL1;tma_L1_group", 264*e08d2ae9SIan Rogers "MetricName": "tma_info_inst_mix_instructions", 2655c3f73c1SIan Rogers "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" 2665c3f73c1SIan Rogers }, 2675c3f73c1SIan Rogers { 2685c3f73c1SIan Rogers "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", 2695c3f73c1SIan Rogers "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", 2705c3f73c1SIan Rogers "MetricGroup": "Pipeline;Ret", 271*e08d2ae9SIan Rogers "MetricName": "tma_info_pipeline_retire" 2725c3f73c1SIan Rogers }, 2735c3f73c1SIan Rogers { 274*e08d2ae9SIan Rogers "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", 275*e08d2ae9SIan Rogers "MetricExpr": "tma_info_system_turbo_utilization * TSC / 1e9 / duration_time", 276*e08d2ae9SIan Rogers "MetricGroup": "Power;Summary", 277*e08d2ae9SIan Rogers "MetricName": "tma_info_system_average_frequency" 278*e08d2ae9SIan Rogers }, 279*e08d2ae9SIan Rogers { 280*e08d2ae9SIan Rogers "BriefDescription": "Average CPU Utilization", 281*e08d2ae9SIan Rogers "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", 282*e08d2ae9SIan Rogers "MetricGroup": "HPC;Summary", 283*e08d2ae9SIan Rogers "MetricName": "tma_info_system_cpu_utilization" 284*e08d2ae9SIan Rogers }, 285*e08d2ae9SIan Rogers { 286*e08d2ae9SIan Rogers "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", 287*e08d2ae9SIan Rogers "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", 288*e08d2ae9SIan Rogers "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", 289*e08d2ae9SIan Rogers "MetricName": "tma_info_system_dram_bw_use", 290*e08d2ae9SIan Rogers "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_mem_bandwidth" 291*e08d2ae9SIan Rogers }, 292*e08d2ae9SIan Rogers { 293*e08d2ae9SIan Rogers "BriefDescription": "Giga Floating Point Operations Per Second", 294*e08d2ae9SIan Rogers "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time", 295*e08d2ae9SIan Rogers "MetricGroup": "Cor;Flops;HPC", 296*e08d2ae9SIan Rogers "MetricName": "tma_info_system_gflops", 297*e08d2ae9SIan Rogers "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." 298*e08d2ae9SIan Rogers }, 299*e08d2ae9SIan Rogers { 300*e08d2ae9SIan Rogers "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", 301*e08d2ae9SIan Rogers "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", 302*e08d2ae9SIan Rogers "MetricGroup": "Branches;OS", 303*e08d2ae9SIan Rogers "MetricName": "tma_info_system_ipfarbranch", 304*e08d2ae9SIan Rogers "MetricThreshold": "tma_info_system_ipfarbranch < 1e6" 305*e08d2ae9SIan Rogers }, 306*e08d2ae9SIan Rogers { 307*e08d2ae9SIan Rogers "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", 308*e08d2ae9SIan Rogers "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", 309*e08d2ae9SIan Rogers "MetricGroup": "OS", 310*e08d2ae9SIan Rogers "MetricName": "tma_info_system_kernel_cpi" 311*e08d2ae9SIan Rogers }, 312*e08d2ae9SIan Rogers { 313*e08d2ae9SIan Rogers "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", 314*e08d2ae9SIan Rogers "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", 315*e08d2ae9SIan Rogers "MetricGroup": "OS", 316*e08d2ae9SIan Rogers "MetricName": "tma_info_system_kernel_utilization", 317*e08d2ae9SIan Rogers "MetricThreshold": "tma_info_system_kernel_utilization > 0.05" 318*e08d2ae9SIan Rogers }, 319*e08d2ae9SIan Rogers { 320*e08d2ae9SIan Rogers "BriefDescription": "Average number of parallel data read requests to external memory", 321*e08d2ae9SIan Rogers "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@", 322*e08d2ae9SIan Rogers "MetricGroup": "Mem;MemoryBW;SoC", 323*e08d2ae9SIan Rogers "MetricName": "tma_info_system_mem_parallel_reads", 324*e08d2ae9SIan Rogers "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" 325*e08d2ae9SIan Rogers }, 326*e08d2ae9SIan Rogers { 327*e08d2ae9SIan Rogers "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", 328*e08d2ae9SIan Rogers "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (tma_info_system_socket_clks / duration_time)", 329*e08d2ae9SIan Rogers "MetricGroup": "Mem;MemoryLat;SoC", 330*e08d2ae9SIan Rogers "MetricName": "tma_info_system_mem_read_latency", 331*e08d2ae9SIan Rogers "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" 3325c3f73c1SIan Rogers }, 3335c3f73c1SIan Rogers { 3345c3f73c1SIan Rogers "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", 3355c3f73c1SIan Rogers "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", 3365c3f73c1SIan Rogers "MetricGroup": "SMT", 337*e08d2ae9SIan Rogers "MetricName": "tma_info_system_smt_2t_utilization" 3385c3f73c1SIan Rogers }, 3395c3f73c1SIan Rogers { 3405c3f73c1SIan Rogers "BriefDescription": "Socket actual clocks when any core is active on that socket", 3415c3f73c1SIan Rogers "MetricExpr": "cbox_0@event\\=0x0@", 3425c3f73c1SIan Rogers "MetricGroup": "SoC", 343*e08d2ae9SIan Rogers "MetricName": "tma_info_system_socket_clks" 3445c3f73c1SIan Rogers }, 3455c3f73c1SIan Rogers { 3465c3f73c1SIan Rogers "BriefDescription": "Average Frequency Utilization relative nominal frequency", 347*e08d2ae9SIan Rogers "MetricExpr": "tma_info_thread_clks / CPU_CLK_UNHALTED.REF_TSC", 3485c3f73c1SIan Rogers "MetricGroup": "Power", 349*e08d2ae9SIan Rogers "MetricName": "tma_info_system_turbo_utilization" 350*e08d2ae9SIan Rogers }, 351*e08d2ae9SIan Rogers { 352*e08d2ae9SIan Rogers "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", 353*e08d2ae9SIan Rogers "MetricExpr": "CPU_CLK_UNHALTED.THREAD", 354*e08d2ae9SIan Rogers "MetricGroup": "Pipeline", 355*e08d2ae9SIan Rogers "MetricName": "tma_info_thread_clks" 356*e08d2ae9SIan Rogers }, 357*e08d2ae9SIan Rogers { 358*e08d2ae9SIan Rogers "BriefDescription": "Cycles Per Instruction (per Logical Processor)", 359*e08d2ae9SIan Rogers "MetricExpr": "1 / tma_info_thread_ipc", 360*e08d2ae9SIan Rogers "MetricGroup": "Mem;Pipeline", 361*e08d2ae9SIan Rogers "MetricName": "tma_info_thread_cpi" 362*e08d2ae9SIan Rogers }, 363*e08d2ae9SIan Rogers { 364*e08d2ae9SIan Rogers "BriefDescription": "The ratio of Executed- by Issued-Uops", 365*e08d2ae9SIan Rogers "MetricExpr": "UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY", 366*e08d2ae9SIan Rogers "MetricGroup": "Cor;Pipeline", 367*e08d2ae9SIan Rogers "MetricName": "tma_info_thread_execute_per_issue", 368*e08d2ae9SIan Rogers "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." 369*e08d2ae9SIan Rogers }, 370*e08d2ae9SIan Rogers { 371*e08d2ae9SIan Rogers "BriefDescription": "Instructions Per Cycle (per Logical Processor)", 372*e08d2ae9SIan Rogers "MetricExpr": "INST_RETIRED.ANY / tma_info_thread_clks", 373*e08d2ae9SIan Rogers "MetricGroup": "Ret;Summary", 374*e08d2ae9SIan Rogers "MetricName": "tma_info_thread_ipc" 375*e08d2ae9SIan Rogers }, 376*e08d2ae9SIan Rogers { 377*e08d2ae9SIan Rogers "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", 378*e08d2ae9SIan Rogers "MetricExpr": "4 * tma_info_core_core_clks", 379*e08d2ae9SIan Rogers "MetricGroup": "TmaL1;tma_L1_group", 380*e08d2ae9SIan Rogers "MetricName": "tma_info_thread_slots" 3815c3f73c1SIan Rogers }, 3825c3f73c1SIan Rogers { 3835c3f73c1SIan Rogers "BriefDescription": "Uops Per Instruction", 3845c3f73c1SIan Rogers "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", 3855c3f73c1SIan Rogers "MetricGroup": "Pipeline;Ret;Retire", 386*e08d2ae9SIan Rogers "MetricName": "tma_info_thread_uoppi", 387*e08d2ae9SIan Rogers "MetricThreshold": "tma_info_thread_uoppi > 1.05" 3885c3f73c1SIan Rogers }, 3895c3f73c1SIan Rogers { 3905c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 391*e08d2ae9SIan Rogers "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_thread_clks", 3925c3f73c1SIan Rogers "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", 3935c3f73c1SIan Rogers "MetricName": "tma_itlb_misses", 3945c3f73c1SIan Rogers "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 3955c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", 3965c3f73c1SIan Rogers "ScaleUnit": "100%" 3975c3f73c1SIan Rogers }, 3985c3f73c1SIan Rogers { 3995c3f73c1SIan Rogers "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", 4005c3f73c1SIan Rogers "MetricConstraint": "NO_GROUP_EVENTS_SMT", 401*e08d2ae9SIan Rogers "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_thread_clks", 4025c3f73c1SIan Rogers "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", 4035c3f73c1SIan Rogers "MetricName": "tma_l3_bound", 4045c3f73c1SIan Rogers "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", 4055c3f73c1SIan Rogers "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", 4065c3f73c1SIan Rogers "ScaleUnit": "100%" 4075c3f73c1SIan Rogers }, 4085c3f73c1SIan Rogers { 4095c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", 410*e08d2ae9SIan Rogers "MetricExpr": "ILD_STALL.LCP / tma_info_thread_clks", 4115c3f73c1SIan Rogers "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", 4125c3f73c1SIan Rogers "MetricName": "tma_lcp", 4135c3f73c1SIan Rogers "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 414*e08d2ae9SIan Rogers "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage", 4155c3f73c1SIan Rogers "ScaleUnit": "100%" 4165c3f73c1SIan Rogers }, 4175c3f73c1SIan Rogers { 4185c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", 4195c3f73c1SIan Rogers "MetricExpr": "tma_retiring - tma_heavy_operations", 4205c3f73c1SIan Rogers "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 4215c3f73c1SIan Rogers "MetricName": "tma_light_operations", 4225c3f73c1SIan Rogers "MetricThreshold": "tma_light_operations > 0.6", 423ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL2", 4245c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 4255c3f73c1SIan Rogers "ScaleUnit": "100%" 4265c3f73c1SIan Rogers }, 4275c3f73c1SIan Rogers { 4285c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", 4295c3f73c1SIan Rogers "MetricConstraint": "NO_GROUP_EVENTS", 4305c3f73c1SIan Rogers "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", 4315c3f73c1SIan Rogers "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 4325c3f73c1SIan Rogers "MetricName": "tma_machine_clears", 4335c3f73c1SIan Rogers "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 434ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL2", 4355c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 4365c3f73c1SIan Rogers "ScaleUnit": "100%" 4375c3f73c1SIan Rogers }, 4385c3f73c1SIan Rogers { 4395c3f73c1SIan Rogers "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", 440*e08d2ae9SIan Rogers "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / tma_info_thread_clks", 4415c3f73c1SIan Rogers "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", 4425c3f73c1SIan Rogers "MetricName": "tma_mem_bandwidth", 4435c3f73c1SIan Rogers "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 444*e08d2ae9SIan Rogers "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_info_system_dram_bw_use", 4455c3f73c1SIan Rogers "ScaleUnit": "100%" 4465c3f73c1SIan Rogers }, 4475c3f73c1SIan Rogers { 4485c3f73c1SIan Rogers "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", 449*e08d2ae9SIan Rogers "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", 4505c3f73c1SIan Rogers "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", 4515c3f73c1SIan Rogers "MetricName": "tma_mem_latency", 4525c3f73c1SIan Rogers "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 4535c3f73c1SIan Rogers "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: ", 4545c3f73c1SIan Rogers "ScaleUnit": "100%" 4555c3f73c1SIan Rogers }, 4565c3f73c1SIan Rogers { 4575c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", 4585c3f73c1SIan Rogers "MetricConstraint": "NO_GROUP_EVENTS", 459*e08d2ae9SIan Rogers "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", 4605c3f73c1SIan Rogers "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 4615c3f73c1SIan Rogers "MetricName": "tma_memory_bound", 4625c3f73c1SIan Rogers "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 463ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL2", 4645c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 4655c3f73c1SIan Rogers "ScaleUnit": "100%" 4665c3f73c1SIan Rogers }, 4675c3f73c1SIan Rogers { 4685c3f73c1SIan Rogers "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", 469*e08d2ae9SIan Rogers "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots", 4705c3f73c1SIan Rogers "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", 4715c3f73c1SIan Rogers "MetricName": "tma_microcode_sequencer", 4725c3f73c1SIan Rogers "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", 4735c3f73c1SIan Rogers "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", 4745c3f73c1SIan Rogers "ScaleUnit": "100%" 4755c3f73c1SIan Rogers }, 4765c3f73c1SIan Rogers { 4775c3f73c1SIan Rogers "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", 478*e08d2ae9SIan Rogers "MetricExpr": "3 * IDQ.MS_SWITCHES / tma_info_thread_clks", 4795c3f73c1SIan Rogers "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", 4805c3f73c1SIan Rogers "MetricName": "tma_ms_switches", 4815c3f73c1SIan Rogers "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 4825c3f73c1SIan Rogers "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", 4835c3f73c1SIan Rogers "ScaleUnit": "100%" 4845c3f73c1SIan Rogers }, 4855c3f73c1SIan Rogers { 4865c3f73c1SIan Rogers "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", 4875c3f73c1SIan Rogers "MetricConstraint": "NO_GROUP_EVENTS", 488*e08d2ae9SIan Rogers "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / tma_info_thread_clks", 4895c3f73c1SIan Rogers "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", 4905c3f73c1SIan Rogers "MetricName": "tma_ports_utilization", 4915c3f73c1SIan Rogers "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", 4925c3f73c1SIan Rogers "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", 4935c3f73c1SIan Rogers "ScaleUnit": "100%" 4945c3f73c1SIan Rogers }, 4955c3f73c1SIan Rogers { 4965c3f73c1SIan Rogers "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", 497*e08d2ae9SIan Rogers "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", 4985c3f73c1SIan Rogers "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", 4995c3f73c1SIan Rogers "MetricName": "tma_retiring", 5005c3f73c1SIan Rogers "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 501ccc66c60SIan Rogers "MetricgroupNoGroup": "TopdownL1", 5025c3f73c1SIan Rogers "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", 5035c3f73c1SIan Rogers "ScaleUnit": "100%" 5045c3f73c1SIan Rogers }, 5055c3f73c1SIan Rogers { 5065c3f73c1SIan Rogers "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", 507*e08d2ae9SIan Rogers "MetricExpr": "RESOURCE_STALLS.SB / tma_info_thread_clks", 5085c3f73c1SIan Rogers "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", 5095c3f73c1SIan Rogers "MetricName": "tma_store_bound", 5105c3f73c1SIan Rogers "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", 5115c3f73c1SIan Rogers "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", 5125c3f73c1SIan Rogers "ScaleUnit": "100%" 5135c3f73c1SIan Rogers }, 5145c3f73c1SIan Rogers { 5155c3f73c1SIan Rogers "BriefDescription": "This metric serves as an approximation of legacy x87 usage", 5165c3f73c1SIan Rogers "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_DISPATCHED.THREAD", 5175c3f73c1SIan Rogers "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", 5185c3f73c1SIan Rogers "MetricName": "tma_x87_use", 5195c3f73c1SIan Rogers "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", 5205c3f73c1SIan Rogers "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", 5215c3f73c1SIan Rogers "ScaleUnit": "100%" 52228bc0ddbSAndi Kleen } 52328bc0ddbSAndi Kleen] 524