| /openbmc/u-boot/include/ |
| H A D | mailbox.h | 10 * A mailbox is a hardware mechanism for transferring small fixed-size messages
14 * Data transfer is optional; a mailbox may consist solely of a notification
16 * FIFOs, rather than via RAM-based buffers. The mailbox API generally
20 * A mailbox channel is a bi-directional mechanism that can send a message or
23 * messages is defined by the mailbox implementation, or the remote entity with
26 * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider
27 * will often implement multiple separate mailbox channels, since the hardware
28 * it manages often has this capability. mailbox-uclass.h describes the
29 * interface which mailbox providers must implement.
31 * Mailbox consumers/clients generate and send, or receive and process,
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| H A D | mailbox-uclass.h | 9 /* See mailbox.h for background documentation. */
11 #include <mailbox.h>
16 * struct mbox_ops - The functions that a mailbox driver must implement.
20 * of_xlate - Translate a client's device-tree (OF) mailbox specifier.
22 * The mailbox core calls this function as the first step in
25 * If this function pointer is set to NULL, the mailbox core will use
29 * At present, the mailbox API solely supports device-tree. If this
34 * @args: The mailbox specifier values from device tree.
42 * The mailbox core calls this function as the second step in
61 * send - Send a message over a mailbox channel
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| /openbmc/u-boot/doc/device-tree-bindings/mailbox/ |
| H A D | mailbox.txt | 1 * Generic Mailbox Controller and client driver bindings
3 Generic binding to provide a way for Mailbox controller drivers to
4 assign appropriate mailbox channel to client drivers.
6 * Mailbox Controller
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
19 * Mailbox Client
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
31 mboxes = <&mailbox 0 &mailbox 1>;
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| /openbmc/openbmc/meta-yadro/recipes-phosphor/dbus/phosphor-dbus-interfaces/ |
| H A D | 0001-Add-boot-initiator-mailbox-interface.patch | 4 Subject: [PATCH] Add boot initiator mailbox interface
6 Add the xyz.openbmc_project.Control.Boot.Mailbox interface to allow
9 Option Parameters' parameter 7 'Boot initiator mailbox'.
16 .../Control/Boot/Mailbox/meson.build | 14 +++++
18 .../Control/Boot/Mailbox.interface.yaml | 63 +++++++++++++++++++
20 create mode 100644 gen/xyz/openbmc_project/Control/Boot/Mailbox/meson.build
21 create mode 100644 xyz/openbmc_project/Control/Boot/Mailbox.interface.yaml
23 …git a/gen/xyz/openbmc_project/Control/Boot/Mailbox/meson.build b/gen/xyz/openbmc_project/Control/B…
27 +++ b/gen/xyz/openbmc_project/Control/Boot/Mailbox/meson.build
32 + input: [ meson.source_root() / 'xyz/openbmc_project/Control/Boot/Mailbox.interface.yaml', ],
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/uw-imap/uw-imap/ |
| H A D | uw-imap-fix-incompatible-pointer-types.patch | 43 - utime (stream->mailbox,tp);
44 + utime (stream->mailbox, (const struct utimbuf *)tp);
48 @@ -1075,7 +1075,7 @@ long mbx_copy (MAILSTREAM *stream,char *sequence,char *mailbox,long options)
57 @@ -1213,7 +1213,7 @@ long mbx_append (MAILSTREAM *stream,char *mailbox,append_t af,void *data)
70 - utime (stream->mailbox,tp);
71 + utime (stream->mailbox, (const struct utimbuf *)tp);
74 mail_exists (stream,nmsgs); /* notify upper level of new mailbox size */
79 - utime (stream->mailbox,tp);
80 + utime (stream->mailbox, (const struct utimbuf *)tp);
82 /* notify upper level of new mailbox size */
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| H A D | 0001-Fix-Wincompatible-function-pointer-types.patch | 30 @@ -103,8 +103,8 @@ long mh_copy (MAILSTREAM *stream,char *sequence,char *mailbox,
32 long mh_append (MAILSTREAM *stream,char *mailbox,append_t af,void *data);
41 @@ -1194,7 +1194,7 @@ long mh_append (MAILSTREAM *stream,char *mailbox,append_t af,void *data)
63 @@ -125,7 +125,7 @@ long mix_unsubscribe (MAILSTREAM *stream,char *mailbox);
64 long mix_create (MAILSTREAM *stream,char *mailbox);
65 long mix_delete (MAILSTREAM *stream,char *mailbox);
114 @@ -98,8 +98,8 @@ long mx_append (MAILSTREAM *stream,char *mailbox,append_t af,void *data);
147 @@ -76,8 +76,8 @@ long news_create (MAILSTREAM *stream,char *mailbox);
148 long news_delete (MAILSTREAM *stream,char *mailbox);
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| /openbmc/u-boot/drivers/mailbox/ |
| H A D | Kconfig | 1 menu "Mailbox Controller Support"
4 bool "Enable mailbox controllers using Driver Model"
7 Enable support for the mailbox driver class. Mailboxes provide the
14 bool "Enable the sandbox mailbox test driver"
17 Enable support for a test mailbox implementation, which simply echos
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| H A D | k3-sec-proxy.c | 15 #include <mailbox-uclass.h>
72 * @chan: Mailbox Channel
100 * @chan: Mailbox channel
103 * Translates the phandle args and fills up the Mailbox channel from client.
132 * k3_sec_proxy_request() - Request for mailbox channel
143 * k3_sec_proxy_free() - Free the mailbox channel
193 * k3_sec_proxy_send() - Send data via mailbox channel
255 * k3_sec_proxy_recv() - Receive data via mailbox channel
339 * @spm: Mailbox instance for which threads needs to be initialized
365 * @dev: corresponding mailbox device
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| H A D | mailbox-uclass.c | 8 #include <mailbox.h>
9 #include <mailbox-uclass.h>
135 UCLASS_DRIVER(mailbox) = {
137 .name = "mailbox",
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| /openbmc/openbmc/meta-yadro/recipes-phosphor/ipmi/phosphor-ipmi-host/ |
| H A D | 0002-Add-support-for-boot-initiator-mailbox.patch | 4 Subject: [PATCH] Add support for boot initiator mailbox
7 (boot initiator mailbox). The format of mailbox is
10 of the mailbox data regardless of the content.
38 +constexpr auto bootMboxIntf = "xyz.openbmc_project.Control.Boot.Mailbox";
60 +// Check if Boot Mailbox is supported.
83 + log<level::ERR>("Error getting Boot/Mailbox/Supported",
112 + log<level::ERR>("Error getting Boot/Mailbox/IANAEnterpriseNumber",
141 + log<level::ERR>("Error getting Boot/Mailbox/Data",
169 + log<level::ERR>("Error setting Boot/Mailbox/Data",
189 + // Only allow reading the boot initiator mailbox if Mailbox is supported
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| /openbmc/u-boot/doc/device-tree-bindings/firmware/ |
| H A D | nvidia,tegra186-bpmp.txt | 16 - mboxes : The phandle of mailbox controller and the mailbox specifier.
23 This node is a mailbox consumer. See the following files for details of
24 the mailbox subsystem, and the specifiers implemented by the relevant
27 - .../mailbox/mailbox.txt
28 - .../mailbox/nvidia,tegra186-hsp.txt
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| H A D | ti,sci.txt | 29 "rx" - Mailbox corresponding to receive path
30 "tx" - Mailbox corresponding to transmit path
33 property should contain a phandle to the mailbox controller device
35 sub-mailbox child node to be used for communication.
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| /openbmc/smbios-mdr/src/ |
| H A D | sst_mailbox.cpp | 27 * Local accesses to the OS Mailbox require the package to pop up to PC2. Also
28 * provides PCode OS Mailbox routine.
98 // PCode OS Mailbox interface register locations
139 throw PECIError("Failed to write mailbox reg"); in wrMailboxReg()
172 throw PECIError("Failed to read mailbox reg"); in rdMailboxReg()
180 * Send command on PCode OS Mailbox interface.
184 * @param[in] inputData Data to put in mailbox. Is always written, but
188 * mailbox-level response status. If null, a
191 * @return Data returned in mailbox. Value is undefined if command is a
198 // The simple mailbox algorithm just says to wait until the busy bit in sendPECIOSMailboxCmd()
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| /openbmc/docs/designs/oem/google/ |
| H A D | root_of_trust.md | 42 - Mailbox API
49 "#RootOfTrust.Mailbox": {
50 "target": "/redfish/v1/RootsOfTrust/0/Actions.Mailbox",
51 "@Redfish.ActionInfo": "/redfish/v1/RootsOfTrust/0/Actions.Mailbox"
64 - name: Mailbox
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| /openbmc/qemu/hw/cxl/ |
| H A D | meson.build | 5 'cxl-mailbox-utils.c',
9 'switch-mailbox-cci.c',
|
| H A D | switch-mailbox-cci.c | 4 * Emulation of a CXL Switch Mailbox CCI PCIe function.
86 * CXL Switch Mailbox CCI - DID assigned for emulation only. in cswmbcci_class_init()
92 dc->desc = "CXL Switch Mailbox CCI"; in cswmbcci_class_init()
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| /openbmc/u-boot/arch/arm/mach-aspeed/ast2600/ |
| H A D | platform.S | 14 * SMP mailbox
19 * | mailbox insn. for |
23 * | mailbox ready |
143 /* reset SMP mailbox as early as possible */
165 /* hold cpuN until SMP mailbox is ready */
176 * for relocated SMP mailbox insn. use
352 /* relocate SMP mailbox insn. for cpuN to poll for go signal */
372 /* notify cpuN mailbox is ready */
383 * insn. inside mailbox to poll SMP go signal.
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| /openbmc/qemu/hw/misc/ |
| H A D | bcm2835_mbox.c | 26 /* Mailbox status register */
30 #define ARM_MS_LEVEL 0x400000FF /* Max. value depends on mailbox depth */
32 /* MAILBOX config/status register */
43 #define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
44 #define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
45 #define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
216 /* Mailbox full */ in bcm2835_mbox_write()
217 qemu_log_mask(LOG_GUEST_ERROR, "%s: mailbox full\n", __func__); in bcm2835_mbox_write()
255 /* vmstate of a single mailbox */
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| /openbmc/qemu/include/hw/cxl/ |
| H A D | cxl_device.h | 24 * mailbox is implemented which means that the offset of the start of the
25 * mailbox payload (n) is given by
26 * n = m + sizeof(mailbox registers) + sizeof(device registers).
38 * | | Mailbox Payload |
43 * ^ | Mailbox Registers |
52 * | | Mailbox Capability Header |
83 /* CXL r3.1 Figure 8-13: Mailbox Registers */
241 /* CXL r3.1 Section 8.2.8.4: Mailbox Registers */
243 MemoryRegion mailbox; member
321 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
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| /openbmc/u-boot/arch/arm/mach-socfpga/ |
| H A D | reset_manager.c | 29 puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); in reset_cpu()
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| /openbmc/openbmc/poky/meta/recipes-multimedia/gstreamer/gstreamer1.0-plugins-base/ |
| H A D | 0003-viv-fb-Make-sure-config.h-is-included.patch | 2 From: Carlos Rafael Giani <crg7475@mailbox.org>
10 Signed-off-by: Carlos Rafael Giani <crg7475@mailbox.org>
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| /openbmc/u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | mailbox_s10.h | 79 /* Mailbox command list */
91 /* Mailbox registers */
98 #define MBOX_STATUS 0x2c /* mailbox status */
110 /* Macros for specifying number of arguments in mailbox command */
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| /openbmc/phosphor-mboxd/Documentation/ |
| H A D | mbox_protocol.md | 18 mailbox registers present on the Aspeed 2400 and 2500 chips.
34 the host and the BMC via the Aspeed mailbox registers. This protocol is used
69 The host uses the mailbox registers to send "commands" to the BMC, which
123 The Aspeed mailbox consists of 16 (8 bit) data registers see Layout for their
124 use. Mailbox interrupt enabling, masking and triggering is done using a pair
167 mailbox data register 0, and generate a sequence number (see Sequence Numbers)
168 to write to mailbox register data 1. After these two values, any
177 of the mailbox and perform the necessary action before responding. On
180 mailbox data register 13 is a valid response code (see Responses). The
188 mailbox data register 15 (or otherwise poll on bit 7 of mailbox status
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| /openbmc/qemu/include/hw/pci/ |
| H A D | pcie_doe.h | 41 /* Write Data Mailbox Register - r6.0 7.9.24.5 */
44 /* Read Data Mailbox Register - 7.9.xx.6 */
103 /* Mailbox position indicator */
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| /openbmc/u-boot/arch/arm/mach-bcm283x/include/mach/ |
| H A D | mbox.h | 16 * using the SoC's mailbox hardware module.
18 * The mailbox hardware supports passing 32-bit values back and forth.
26 * The property mailbox channel passes messages that contain the (16-byte
29 * passed back to the ARM CPU as the response mailbox message to indicate
38 /* Raw mailbox HW */
64 /* Property mailbox buffer structures */
|