1c1418172SChia-Wei, Wang// SPDX-License-Identifier: GPL-2.0 2b9553986Sryan_chen/* 3c1418172SChia-Wei, Wang * Copyright (C) ASPEED Technology Inc. 4f4934d27SChia-Wei, Wang * Chia-Wei Wang <chiawei_wang@aspeedtech.com> 5b9553986Sryan_chen */ 6b9553986Sryan_chen 7b9553986Sryan_chen#include <config.h> 8b9553986Sryan_chen#include <version.h> 9b9553986Sryan_chen#include <asm/secure.h> 10b9553986Sryan_chen#include <asm/armv7.h> 11093f01f6SChia-Wei, Wang#include <linux/linkage.h> 12b9553986Sryan_chen 1389c9042eSChia-Wei, Wang/* 1489c9042eSChia-Wei, Wang * SMP mailbox 15*660853d9SChia-Wei Wang * +----------------------+ 0x40 16*660853d9SChia-Wei Wang * | cpuN sec_entrypoint | 17*660853d9SChia-Wei Wang * +----------------------+ 0x3c 1889c9042eSChia-Wei, Wang * | | 1989c9042eSChia-Wei, Wang * | mailbox insn. for | 20*660853d9SChia-Wei Wang * | cpuN GO sign polling | 2189c9042eSChia-Wei, Wang * | | 22*660853d9SChia-Wei Wang * +----------------------+ 0x10 23*660853d9SChia-Wei Wang * | mailbox ready | 24*660853d9SChia-Wei Wang * +----------------------+ 0x0c 25*660853d9SChia-Wei Wang * | reserved | 26*660853d9SChia-Wei Wang * +----------------------+ 0x08 2789c9042eSChia-Wei, Wang * | cpuN GO signal | 28*660853d9SChia-Wei Wang * +----------------------+ 0x04 29*660853d9SChia-Wei Wang * | cpuN ns_entrypoint | 30*660853d9SChia-Wei Wang * +----------------------+ SCU180 3189c9042eSChia-Wei, Wang */ 32b9553986Sryan_chen 33*660853d9SChia-Wei Wang#define SCU_BASE 0x1e6e2000 34*660853d9SChia-Wei Wang#define SCU_PROT_KEY1 (SCU_BASE) 35*660853d9SChia-Wei Wang#define SCU_PROT_KEY2 (SCU_BASE + 0x010) 36*660853d9SChia-Wei Wang#define SCU_REV_ID (SCU_BASE + 0x014) 37*660853d9SChia-Wei Wang#define SCU_SYSRST_CTRL (SCU_BASE + 0x040) 38*660853d9SChia-Wei Wang#define SCU_SYSRST_CTRL_CLR (SCU_BASE + 0x044) 39*660853d9SChia-Wei Wang#define SCU_SYSRST_EVENT (SCU_BASE + 0x064) 40*660853d9SChia-Wei Wang#define SCU_CLK_STOP_CTRL_CLR (SCU_BASE + 0x084) 41*660853d9SChia-Wei Wang#define SCU_DEBUG_CTRL (SCU_BASE + 0x0c8) 42*660853d9SChia-Wei Wang#define SCU_DEBUG_CTRL2 (SCU_BASE + 0x0d8) 43*660853d9SChia-Wei Wang#define SCU_SMP_NS_EP (SCU_BASE + 0x180) 44*660853d9SChia-Wei Wang#define SCU_SMP_GO (SCU_BASE + 0x184) 45*660853d9SChia-Wei Wang#define SCU_SMP_READY (SCU_BASE + 0x18c) 46*660853d9SChia-Wei Wang#define SCU_SMP_POLLINSN (SCU_BASE + 0x190) 47*660853d9SChia-Wei Wang#define SCU_SMP_S_EP (SCU_BASE + 0x1bc) 48*660853d9SChia-Wei Wang#define SCU_HPLL_PARAM (SCU_BASE + 0x200) 49*660853d9SChia-Wei Wang#define SCU_HPLL_PARAM_EXT (SCU_BASE + 0x204) 50*660853d9SChia-Wei Wang#define SCU_USB_MULTI_FUNC (SCU_BASE + 0x440) 51*660853d9SChia-Wei Wang#define SCU_HW_STRAP1 (SCU_BASE + 0x500) 52*660853d9SChia-Wei Wang#define SCU_HW_STRAP2 (SCU_BASE + 0x510) 53*660853d9SChia-Wei Wang#define SCU_HW_STRAP3 (SCU_BASE + 0x51c) 54*660853d9SChia-Wei Wang#define SCU_CA7_PARITY_CHK (SCU_BASE + 0x820) 55*660853d9SChia-Wei Wang#define SCU_CA7_PARITY_CLR (SCU_BASE + 0x824) 56*660853d9SChia-Wei Wang#define SCU_MMIO_DEC_SET (SCU_BASE + 0xc24) 57b9553986Sryan_chen 58*660853d9SChia-Wei Wang#define FMC_BASE 0x1e620000 59*660853d9SChia-Wei Wang#define FMC_CE0_CTRL (FMC_BASE + 0x010) 60*660853d9SChia-Wei Wang#define FMC_SW_RST_CTRL (FMC_BASE + 0x050) 61*660853d9SChia-Wei Wang#define FMC_WDT1_CTRL_MODE (FMC_BASE + 0x060) 62*660853d9SChia-Wei Wang#define FMC_WDT2_CTRL_MODE (FMC_BASE + 0x064) 63168dc2c1SChia-Wei, Wang 64*660853d9SChia-Wei Wang#define GPIO_BASE 0x1e780000 65*660853d9SChia-Wei Wang#define GPIOYZ_DATA_VALUE (GPIO_BASE + 0x1e0) 667bc7f5eeSChia-Wei, Wang 67*660853d9SChia-Wei Wang#define SEC_BASE 0x1e6f2000 68*660853d9SChia-Wei Wang#define SEC_VAULT_KEY_CTRL (SEC_BASE + 0x80c) 694912aa48SChia-Wei, Wang 70168dc2c1SChia-Wei, Wang#define REV_ID_AST2600A0 0x05000303 71455b879aSChia-Wei, Wang#define REV_ID_AST2600A1 0x05010303 72a792272aSChia-Wei, Wang#define REV_ID_AST2620A1 0x05010203 73168dc2c1SChia-Wei, Wang 7455825c55SChia-Wei, Wang.macro scu_unlock 75*660853d9SChia-Wei Wang movw r0, #0xa8a8 7655825c55SChia-Wei, Wang movt r0, #0x1688 @; magic key to unlock SCU 7755825c55SChia-Wei, Wang 78*660853d9SChia-Wei Wang ldr r1, =SCU_PROT_KEY1 7955825c55SChia-Wei, Wang str r0, [r1] 80*660853d9SChia-Wei Wang ldr r1, =SCU_PROT_KEY2 8155825c55SChia-Wei, Wang str r0, [r1] 8255825c55SChia-Wei, Wang.endm 83168dc2c1SChia-Wei, Wang 8446a48bbeSChia-Wei, Wang.macro timer_init 85f4934d27SChia-Wei, Wang#ifdef CONFIG_FPGA_ASPEED 86159f55f0SDylan Hung movw r0, #0x6c00 87159f55f0SDylan Hung movt r0, #0x02dc 88f4934d27SChia-Wei, Wang#else 89*660853d9SChia-Wei Wang ldr r0, =SCU_REV_ID 903e3987f1SChia-Wei, Wang ldr r0, [r0] 913e3987f1SChia-Wei, Wang 923e3987f1SChia-Wei, Wang ldr r1, =REV_ID_AST2600A0 933e3987f1SChia-Wei, Wang cmp r0, r1 943e3987f1SChia-Wei, Wang 95f3b4be0aSChia-Wei, Wang beq timer_init_a0 96f3b4be0aSChia-Wei, Wang 97*660853d9SChia-Wei Wang ldr r1, =SCU_HW_STRAP1 98f3b4be0aSChia-Wei, Wang ldr r1, [r1] 99f3b4be0aSChia-Wei, Wang and r1, #0x700 100f3b4be0aSChia-Wei, Wang lsr r1, #0x8 101f3b4be0aSChia-Wei, Wang 102f3b4be0aSChia-Wei, Wang cmp r1, #0x0 103f3b4be0aSChia-Wei, Wang movweq r0, #0x8c00 104f3b4be0aSChia-Wei, Wang movteq r0, #0x4786 105f3b4be0aSChia-Wei, Wang 106f3b4be0aSChia-Wei, Wang cmp r1, #0x1 107f3b4be0aSChia-Wei, Wang movweq r0, #0x1000 108f3b4be0aSChia-Wei, Wang movteq r0, #0x5f5e 109f3b4be0aSChia-Wei, Wang 110f3b4be0aSChia-Wei, Wang cmp r1, #0x2 111f3b4be0aSChia-Wei, Wang movweq r0, #0x8c00 112f3b4be0aSChia-Wei, Wang movteq r0, #0x4786 113f3b4be0aSChia-Wei, Wang 114f3b4be0aSChia-Wei, Wang cmp r1, #0x3 115f3b4be0aSChia-Wei, Wang movweq r0, #0x1000 116f3b4be0aSChia-Wei, Wang movteq r0, #0x5f5e 117f3b4be0aSChia-Wei, Wang 118f3b4be0aSChia-Wei, Wang cmp r1, #0x4 119f3b4be0aSChia-Wei, Wang movwge r0, #0x0800 120f3b4be0aSChia-Wei, Wang movtge r0, #0x2faf 121f3b4be0aSChia-Wei, Wang 122f3b4be0aSChia-Wei, Wang b timer_init_out 123f3b4be0aSChia-Wei, Wang 124f3b4be0aSChia-Wei, Wangtimer_init_a0: 125f3b4be0aSChia-Wei, Wang movweq r0, #0x32c0 1263e3987f1SChia-Wei, Wang movteq r0, #0x4013 127f3b4be0aSChia-Wei, Wang 128f3b4be0aSChia-Wei, Wangtimer_init_out: 129f4934d27SChia-Wei, Wang#endif 130f4934d27SChia-Wei, Wang mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ 131f4934d27SChia-Wei, Wang.endm 132f4934d27SChia-Wei, Wang 133f4934d27SChia-Wei, Wang 134b9553986Sryan_chen.globl lowlevel_init 13589c9042eSChia-Wei, Wang 136b9553986Sryan_chenlowlevel_init: 13789c9042eSChia-Wei, Wang#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 13889c9042eSChia-Wei, Wang mov pc, lr 13989c9042eSChia-Wei, Wang#else 14046a48bbeSChia-Wei, Wang /* setup ARM arch timer frequency */ 14146a48bbeSChia-Wei, Wang timer_init 142f4934d27SChia-Wei, Wang 14355825c55SChia-Wei, Wang /* reset SMP mailbox as early as possible */ 14455825c55SChia-Wei, Wang mov r0, #0x0 145*660853d9SChia-Wei Wang ldr r1, =SCU_SMP_READY 14655825c55SChia-Wei, Wang str r0, [r1] 14755825c55SChia-Wei, Wang 148c3f3abd8SChia-Wei, Wang /* set ACTLR.SMP to enable cache use */ 149c3f3abd8SChia-Wei, Wang mrc p15, 0, r0, c1, c0, 1 150f4934d27SChia-Wei, Wang orr r0, #0x40 151c3f3abd8SChia-Wei, Wang mcr p15, 0, r0, c1, c0, 1 152c3f3abd8SChia-Wei, Wang 15389c9042eSChia-Wei, Wang /* 15489c9042eSChia-Wei, Wang * we treat cpu0 as the primary core and 15589c9042eSChia-Wei, Wang * put secondary core (cpuN) to sleep 15689c9042eSChia-Wei, Wang */ 157b9553986Sryan_chen mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register 158*660853d9SChia-Wei Wang ands r0, #0xff @; Mask off, leaving the CPU ID field 159*660853d9SChia-Wei Wang movw r4, #0xab00 160*660853d9SChia-Wei Wang movt r4, #0xabba 161*660853d9SChia-Wei Wang orr r4, r0 162b9553986Sryan_chen 16389c9042eSChia-Wei, Wang beq do_primary_core_setup 164b9553986Sryan_chen 165*660853d9SChia-Wei Wang /* hold cpuN until SMP mailbox is ready */ 166*660853d9SChia-Wei Wangpoll_smp_mbox_ready: 16789c9042eSChia-Wei, Wang wfe 168*660853d9SChia-Wei Wang ldr r0, =SCU_SMP_READY 169575fda89SJohnny Huang ldr r0, [r0] 170*660853d9SChia-Wei Wang movw r1, #0xcafe 171*660853d9SChia-Wei Wang movt r1, #0xbabe 172575fda89SJohnny Huang cmp r1, r0 173*660853d9SChia-Wei Wang bne poll_smp_mbox_ready 174b9553986Sryan_chen 175*660853d9SChia-Wei Wang /* 176*660853d9SChia-Wei Wang * for relocated SMP mailbox insn. use 177*660853d9SChia-Wei Wang * r4 = per-cpu go sign value 178*660853d9SChia-Wei Wang * r5 = SCU_SMP_GO 179*660853d9SChia-Wei Wang * r6 = SCU_SMP_NS_EP 180*660853d9SChia-Wei Wang * r7 = SCU_SMP_S_EP 181*660853d9SChia-Wei Wang */ 182*660853d9SChia-Wei Wang ldr r5, =SCU_SMP_GO 183*660853d9SChia-Wei Wang ldr r6, =SCU_SMP_NS_EP 184*660853d9SChia-Wei Wang ldr r7, =SCU_SMP_S_EP 185b9553986Sryan_chen 18689c9042eSChia-Wei, Wang /* no return */ 187*660853d9SChia-Wei Wang ldr pc, =SCU_SMP_POLLINSN 188b0a2e3f1SChia-Wei, Wang 18989c9042eSChia-Wei, Wangdo_primary_core_setup: 19046a48bbeSChia-Wei, Wang /* unlock system control unit */ 19146a48bbeSChia-Wei, Wang scu_unlock 19246a48bbeSChia-Wei, Wang 193b52afd2eSChia-Wei, Wang /* identify AST2600 A0/A1 */ 194*660853d9SChia-Wei Wang ldr r0, =SCU_REV_ID 19546a48bbeSChia-Wei, Wang ldr r0, [r0] 19646a48bbeSChia-Wei, Wang 19746a48bbeSChia-Wei, Wang ldr r1, =REV_ID_AST2600A0 19846a48bbeSChia-Wei, Wang cmp r0, r1 19946a48bbeSChia-Wei, Wang 20046a48bbeSChia-Wei, Wang bne 0f 20146a48bbeSChia-Wei, Wang 202b52afd2eSChia-Wei, Wang /* tune up CPU clocks (A0 only) */ 203*660853d9SChia-Wei Wang ldr r0, =SCU_HW_STRAP1 20446a48bbeSChia-Wei, Wang ldr r1, [r0] 20546a48bbeSChia-Wei, Wang bic r1, #0x1800 20646a48bbeSChia-Wei, Wang orr r1, #0x1000 20746a48bbeSChia-Wei, Wang str r1, [r0] 20846a48bbeSChia-Wei, Wang 209*660853d9SChia-Wei Wang ldr r0, =SCU_HPLL_PARAM 210c843e21aSDylan Hung movw r1, #0x4080 21146a48bbeSChia-Wei, Wang movt r1, #0x1000 21246a48bbeSChia-Wei, Wang str r1, [r0] 21346a48bbeSChia-Wei, Wang 214*660853d9SChia-Wei Wang ldr r0, =SCU_HPLL_PARAM_EXT 21546a48bbeSChia-Wei, Wang mov r1, #0x47 21646a48bbeSChia-Wei, Wang str r1, [r0] 21746a48bbeSChia-Wei, Wang 21846a48bbeSChia-Wei, Wangwait_lock: 21946a48bbeSChia-Wei, Wang ldr r1, [r0] 22046a48bbeSChia-Wei, Wang tst r1, #0x80000000 22146a48bbeSChia-Wei, Wang beq wait_lock 22246a48bbeSChia-Wei, Wang 223b52afd2eSChia-Wei, Wang /* skip A1 only area */ 224455b879aSChia-Wei, Wang b 2f 2254912aa48SChia-Wei, Wang 22646a48bbeSChia-Wei, Wang0: 227455b879aSChia-Wei, Wang /* identify AST2600/AST2620 A1 */ 228*660853d9SChia-Wei Wang ldr r0, =SCU_REV_ID 229455b879aSChia-Wei, Wang ldr r0, [r0] 230455b879aSChia-Wei, Wang 231455b879aSChia-Wei, Wang ldr r1, =REV_ID_AST2600A1 232455b879aSChia-Wei, Wang cmp r0, r1 233455b879aSChia-Wei, Wang beq 1f 234455b879aSChia-Wei, Wang 235455b879aSChia-Wei, Wang ldr r1, =REV_ID_AST2620A1 236455b879aSChia-Wei, Wang cmp r0, r1 237455b879aSChia-Wei, Wang bne 2f 238455b879aSChia-Wei, Wang 239455b879aSChia-Wei, Wang1: 240b339e5deSJohnny Huang /* LPC/eSPI mode selection by SW (AST2600/AST2620 A1 only) */ 241*660853d9SChia-Wei Wang ldr r0, =GPIOYZ_DATA_VALUE 242b339e5deSJohnny Huang ldr r0, [r0] 243b339e5deSJohnny Huang tst r0, #0x1000 244b339e5deSJohnny Huang beq 2f 245b339e5deSJohnny Huang 246b339e5deSJohnny Huang /* switch to LPC mode if GPIOZ[4]=1 */ 247*660853d9SChia-Wei Wang ldr r0, =SCU_HW_STRAP2 248b339e5deSJohnny Huang ldr r1, [r0] 249b339e5deSJohnny Huang orr r1, #0x40 250b339e5deSJohnny Huang str r1, [r0] 251b339e5deSJohnny Huang 252455b879aSChia-Wei, Wang2: 253fa031c2eSNeal Liu /* Enable Vault Key Write Protection */ 254fa031c2eSNeal Liu mov r0, #0x2 255*660853d9SChia-Wei Wang ldr r1, =SEC_VAULT_KEY_CTRL 256fa031c2eSNeal Liu str r0, [r1] 257fa031c2eSNeal Liu 258f90dc5e4SRyan Chen /* PCIeRC/E2M8 power-on reset comes from SCU040 259cb65c219Sryan_chen It need set SCU040[18] high to reset PCIeRC/E2M 260cb65c219Sryan_chen when AC power-on */ 261*660853d9SChia-Wei Wang ldr r0, =SCU_SYSRST_EVENT 262cb65c219Sryan_chen ldr r1, [r0] 263cb65c219Sryan_chen tst r1, #0x1 264cb65c219Sryan_chen beq 3f 265*660853d9SChia-Wei Wang ldr r0, =SCU_SYSRST_CTRL 266f90dc5e4SRyan Chen movw r1, #0x0000 267f90dc5e4SRyan Chen movt r1, #0x0004 268f90dc5e4SRyan Chen str r1, [r0] 269cb65c219Sryan_chen3: 270e0543804SChin-Ting Kuo /* Fix UART1 route problem on A3 */ 271e0543804SChin-Ting Kuo ldr r0, =0x1e789098 272e0543804SChin-Ting Kuo movw r1, #0x0a30 273e0543804SChin-Ting Kuo movt r1, #0x0000 274e0543804SChin-Ting Kuo str r1, [r0] 275e0543804SChin-Ting Kuo 276e0543804SChin-Ting Kuo ldr r0, =0x1e78909c 277e0543804SChin-Ting Kuo movw r1, #0x0000 278e0543804SChin-Ting Kuo movt r1, #0x0000 279e0543804SChin-Ting Kuo str r1, [r0] 280e0543804SChin-Ting Kuo 2813d56f5ccSChia-Wei, Wang /* MMIO decode setting */ 282*660853d9SChia-Wei Wang ldr r0, =SCU_MMIO_DEC_SET 2833d56f5ccSChia-Wei, Wang mov r1, #0x2000 2843d56f5ccSChia-Wei, Wang str r1, [r0] 2853d56f5ccSChia-Wei, Wang 2862fe590b1SChia-Wei, Wang /* enable cache & SRAM parity check */ 2872fe590b1SChia-Wei, Wang mov r0, #0 288*660853d9SChia-Wei Wang ldr r1, =SCU_CA7_PARITY_CLR 2892fe590b1SChia-Wei, Wang str r0, [r1] 2902fe590b1SChia-Wei, Wang 291ece7b5c3SChia-Wei, Wang mov r0, #0x1 292*660853d9SChia-Wei Wang ldr r1, =SCU_CA7_PARITY_CHK 2932fe590b1SChia-Wei, Wang str r0, [r1] 2942fe590b1SChia-Wei, Wang 2955aceacf1SNeal Liu /* Select USB2.0 Device mode as USB port B */ 2965aceacf1SNeal Liu ldr r0, =0x10000000 297*660853d9SChia-Wei Wang ldr r1, =SCU_USB_MULTI_FUNC 2985aceacf1SNeal Liu str r0, [r1] 2995aceacf1SNeal Liu 30025d399cfSNeal Liu /* enable USB port B PHY clk */ 30125d399cfSNeal Liu mov r0, #0x80 302*660853d9SChia-Wei Wang ldr r1, =SCU_CLK_STOP_CTRL_CLR 30325d399cfSNeal Liu str r0, [r1] 30425d399cfSNeal Liu 305c7e2afdbSChia-Wei, Wang#if 0 306*660853d9SChia-Wei Wang ldr r1, =FMC_WDT2_CTRL_MODE 3077bc7f5eeSChia-Wei, Wang str r0, [r1] 308c7e2afdbSChia-Wei, Wang#endif 3095e1aee82SChin-Ting Kuo 310ae9cbc84SChin-Ting Kuo /* do not fill FMC50[1] if boot from eMMC */ 311*660853d9SChia-Wei Wang ldr r0, =SCU_HW_STRAP1 312ae9cbc84SChin-Ting Kuo ldr r1, [r0] 313ae9cbc84SChin-Ting Kuo ands r1, #0x04 314ae9cbc84SChin-Ting Kuo bne skip_fill_wip_bit 315ae9cbc84SChin-Ting Kuo 3165e1aee82SChin-Ting Kuo /* fill FMC50[1] for waiting WIP idle */ 3175e1aee82SChin-Ting Kuo mov r0, #0x02 318*660853d9SChia-Wei Wang ldr r1, =FMC_SW_RST_CTRL 3195e1aee82SChin-Ting Kuo str r0, [r1] 320ae9cbc84SChin-Ting Kuoskip_fill_wip_bit: 3215e1aee82SChin-Ting Kuo 32251b227c8SChin-Ting Kuo#if !defined(CONFIG_ASPEED_DEFAULT_SPI_FREQUENCY) 323c8efa848SChia-Wei, Wang /* tune up SPI clock */ 324e220f03cSChin-Ting Kuo movw r0, #0x0600 325e220f03cSChin-Ting Kuo movt r0, #0x0000 326*660853d9SChia-Wei Wang ldr r1, =FMC_CE0_CTRL 327ccf0e0d7Sryan_chen str r0, [r1] 32851b227c8SChin-Ting Kuo#endif 329b9553986Sryan_chen 330e220f03cSChin-Ting Kuo /* disable FMC WDT for SPI address mode detection */ 331e220f03cSChin-Ting Kuo mov r0, #0 332*660853d9SChia-Wei Wang ldr r1, =FMC_WDT1_CTRL_MODE 333e220f03cSChin-Ting Kuo str r0, [r1] 334e220f03cSChin-Ting Kuo 3353a78e3f8SChia-Wei Wang /* disable backdoor for A1/A2 to align A3 design */ 336*660853d9SChia-Wei Wang ldr r0, =SCU_HW_STRAP3 337e436a12eSChia-Wei Wang ldr r0, [r0] 338e436a12eSChia-Wei Wang tst r0, #0x1 339e436a12eSChia-Wei Wang 340*660853d9SChia-Wei Wang ldr r0, =SCU_DEBUG_CTRL 341e436a12eSChia-Wei Wang movwne r1, #0x0ffd 342e436a12eSChia-Wei Wang movweq r1, #0x0fff 3433a78e3f8SChia-Wei Wang movt r1, #0x0000 3440be96a7fSryan_chen str r1, [r0] 3450be96a7fSryan_chen 346*660853d9SChia-Wei Wang ldr r0, =SCU_DEBUG_CTRL2 347e436a12eSChia-Wei Wang movne r1, #0xf7 348e436a12eSChia-Wei Wang moveq r1, #0xff 3490be96a7fSryan_chen str r1, [r0] 3500be96a7fSryan_chen 351*660853d9SChia-Wei Wangrelocate_smp_mbox_start: 352*660853d9SChia-Wei Wang /* relocate SMP mailbox insn. for cpuN to poll for go signal */ 353*660853d9SChia-Wei Wang adrl r0, smp_mbox_insn 354*660853d9SChia-Wei Wang adrl r1, smp_mbox_insn_end 355*660853d9SChia-Wei Wang ldr r2, =SCU_SMP_POLLINSN 35689c9042eSChia-Wei, Wang 357*660853d9SChia-Wei Wangrelocate_smp_mbox_insn: 35889c9042eSChia-Wei, Wang ldr r3, [r0], #0x4 35989c9042eSChia-Wei, Wang str r3, [r2], #0x4 36089c9042eSChia-Wei, Wang cmp r0, r1 361*660853d9SChia-Wei Wang bne relocate_smp_mbox_insn 36289c9042eSChia-Wei, Wang 363*660853d9SChia-Wei Wang /* reset SMP go sign and entrypoints */ 36455825c55SChia-Wei, Wang mov r0, #0 365*660853d9SChia-Wei Wang ldr r1, =SCU_SMP_GO 366*660853d9SChia-Wei Wang str r0, [r1] 367*660853d9SChia-Wei Wang ldr r1, =SCU_SMP_NS_EP 368*660853d9SChia-Wei Wang str r0, [r1] 369*660853d9SChia-Wei Wang ldr r1, =SCU_SMP_S_EP 37055825c55SChia-Wei, Wang str r0, [r1] 37155825c55SChia-Wei, Wang 37289c9042eSChia-Wei, Wang /* notify cpuN mailbox is ready */ 373*660853d9SChia-Wei Wang movw r0, #0xcafe 374*660853d9SChia-Wei Wang movt r0, #0xbabe 375*660853d9SChia-Wei Wang ldr r1, =SCU_SMP_READY 37655825c55SChia-Wei, Wang str r0, [r1] 37789c9042eSChia-Wei, Wang sev 378b9553986Sryan_chen 379b9553986Sryan_chen /* back to arch calling code */ 380b9553986Sryan_chen mov pc, lr 381b9553986Sryan_chen 38289c9042eSChia-Wei, Wang/* 38389c9042eSChia-Wei, Wang * insn. inside mailbox to poll SMP go signal. 38489c9042eSChia-Wei, Wang * 38589c9042eSChia-Wei, Wang * Note that as this code will be relocated, any 38689c9042eSChia-Wei, Wang * pc-relative assembly should NOT be used. 38789c9042eSChia-Wei, Wang */ 388*660853d9SChia-Wei Wangsmp_mbox_insn: 38989c9042eSChia-Wei, Wang /* 390*660853d9SChia-Wei Wang * r4 = per-cpu go sign value 391*660853d9SChia-Wei Wang * r5 = SCU_SMP_GO 392*660853d9SChia-Wei Wang * r6 = SCU_SMP_NS_EP 393*660853d9SChia-Wei Wang * r7 = SCU_SMP_S_EP 39489c9042eSChia-Wei, Wang */ 395*660853d9SChia-Wei Wangpoll_smp_mbox_go: 396b9553986Sryan_chen wfe 397*660853d9SChia-Wei Wang ldr r0, [r5] 398*660853d9SChia-Wei Wang cmp r0, r4 399*660853d9SChia-Wei Wang bne poll_smp_mbox_go 400b9553986Sryan_chen 401*660853d9SChia-Wei Wang /* go to secure world if secure entrypoint is specified */ 402*660853d9SChia-Wei Wang ldr r3, [r7] 403*660853d9SChia-Wei Wang cmp r3, #0 404*660853d9SChia-Wei Wang beq 1f 40589c9042eSChia-Wei, Wang 406*660853d9SChia-Wei Wang ldr lr, [r6] 407*660853d9SChia-Wei Wang mov pc, r3 408*660853d9SChia-Wei Wang1: 409*660853d9SChia-Wei Wang ldr pc, [r6] 410*660853d9SChia-Wei Wang 411*660853d9SChia-Wei Wangsmp_mbox_insn_end: 41289c9042eSChia-Wei, Wang /* should never reach */ 41389c9042eSChia-Wei, Wang b . 41489c9042eSChia-Wei, Wang 41589c9042eSChia-Wei, Wang#endif 416