phosphor-mboxd/Documentation/mbox_protocol.md

18 mailbox registers present on the Aspeed 2400 and 2500 chips.
34 the host and the BMC via the Aspeed mailbox registers. This protocol is used
69 The host uses the mailbox registers to send "commands" to the BMC, which
123 The Aspeed mailbox consists of 16 (8 bit) data registers see Layout for their
124 use. Mailbox interrupt enabling, masking and triggering is done using a pair
167 mailbox data register 0, and generate a sequence number (see Sequence Numbers)
168 to write to mailbox register data 1. After these two values, any
177 of the mailbox and perform the necessary action before responding. On
180 mailbox data register 13 is a valid response code (see Responses). The
188 mailbox data register 15 (or otherwise poll on bit 7 of mailbox status
190 mailbox data register 15 to determine the event code which was set by the
440 		pre mailbox protocol. Final behavior is still TBD.
652 		Args 0:	Bits in the BMC status byte (mailbox data
655 		*clears the bits in mailbox data register 15*
658 		supplied in mailbox register 15.