Lines Matching full:mailbox
24 * mailbox is implemented which means that the offset of the start of the
25 * mailbox payload (n) is given by
26 * n = m + sizeof(mailbox registers) + sizeof(device registers).
38 * | | Mailbox Payload |
43 * ^ | Mailbox Registers |
52 * | | Mailbox Capability Header |
83 /* CXL r3.1 Figure 8-13: Mailbox Registers */
241 /* CXL r3.1 Section 8.2.8.4: Mailbox Registers */
243 MemoryRegion mailbox; member
321 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
368 /* CXL r3.1 Section 8.2.8.4.3: Mailbox Capabilities Register */
377 /* CXL r3.1 Section 8.2.8.4.4: Mailbox Control Register */
389 /* CXL r3.1 Section 8.2.8.4.6: Mailbox Status Register */
591 CXLCCI cci; /* Primary PCI mailbox CCI */
674 #define TYPE_CXL_SWITCH_MAILBOX_CCI "cxl-switch-mailbox-cci"