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/openbmc/qemu/include/hw/misc/
H A Daspeed_scu.h9 * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
84 * arch/arm/mach-aspeed/include/mach/regs-scu.h
86 * Copyright (C) 2012-2020 ASPEED Technology Inc.
103 * 25:23 APB PCLK divider selection
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2600.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include <dt-bindings/clock/ast2600-clock.h>
16 #include <dt-bindings/reset/ast2600-reset.h>
19 * SCU 80 & 90 clock stop control for MAC controllers
27 * MAC Clock Delay settings
133 * Clock divider/multiplier configuration struct.
134 * For H-PLL and M-PLL the formula is
136 * M - Numerator
137 * N - Denumerator
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H A Dclk_ast2500.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include <dt-bindings/clock/ast2500-clock.h>
16 #include <dt-bindings/reset/ast2500-reset.h>
19 * MAC Clock Delay settings, taken from Aspeed SDK
35 * Clock divider/multiplier configuration struct.
36 * For H-PLL and M-PLL the formula is
38 * M - Numerator
39 * N - Denumerator
40 * P - Post Divider
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/openbmc/linux/drivers/clk/
H A Dclk-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
17 * struct aspeed_gate_data - Aspeed gated clocks
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35 * @hw: handle between common and hardware-specific interfaces
38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
40 * @flags: hardware-specific flags
59 * struct aspeed_reset - Aspeed reset controller
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H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-venice-gw74xx.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
30 stdout-path = &uart2;
38 gpio-keys {
39 compatible = "gpio-keys";
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H A Dimx8mm-venice-gw7901.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
30 stdout-path = &uart2;
38 gpio-keys {
39 compatible = "gpio-keys";
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H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
27 stdout-path = &uart2;
36 compatible = "fixed-clock";
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/openbmc/linux/arch/arm64/boot/dts/apm/
H A Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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H A Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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/openbmc/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/lpc32xx-clock.h>
244 LPC32XX_CLK_DEFINE(MAC, "mac", 0x0, LPC32XX_CLK_HCLK),
253 * divider register does not contain information about selected rate.
393 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_enable()
395 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy) in clk_mask_enable()
396 return -EBUSY; in clk_mask_enable()
398 return regmap_update_bits(clk_regmap, clk->reg, in clk_mask_enable()
399 clk->enable_mask, clk->enable); in clk_mask_enable()
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/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0+ */
19 u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */
31 u32 hclkdiv_ctrl; /* HCLK Divider Control Register */
49 u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */
72 /* HCLK Divider Control Register bits */
78 #define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2)
116 #define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1)
119 /* Ethernet MAC Clock Control Register bits */
144 #define CLK_UART(n) (1 << ((n) - 3))
/openbmc/linux/drivers/net/ethernet/actions/
H A Dowl-emac.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Actions Semi Owl SoCs Ethernet MAC driver
12 #define OWL_EMAC_DRVNAME "owl-emac"
49 #define OWL_EMAC_VAL_MAC_CSR5_TS_DATA 0x03 /* Transferring data HOST -> FIFO */
55 #define OWL_EMAC_VAL_MAC_CSR5_RS_DATA 0x07 /* Transferring data FIFO -> HOST */
59 #define OWL_EMAC_BIT_MAC_CSR5_GTE BIT(11) /* General-purpose timer expiration */
98 #define OWL_EMAC_BIT_MAC_CSR7_GTE BIT(11) /* General-purpose timer overflow */
125 #define OWL_EMAC_MSK_MAC_CSR10_CLKDIV GENMASK(30, 28) /* Clock divider */
133 #define OWL_EMAC_VAL_MAC_CSR10_OPCODE_CDS 0x03 /* Clock divider set */
140 /* General-purpose timer and interrupt mitigation control register */
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/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
12 "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
66 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_suspend()
68 return reset_control_assert(mgbe->rst_mac); in tegra_mgbe_suspend()
77 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
81 err = reset_control_deassert(mgbe->rst_mac); in tegra_mgbe_resume()
86 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); in tegra_mgbe_resume()
89 writel(mgbe->iommu_sid, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); in tegra_mgbe_resume()
91 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); in tegra_mgbe_resume()
93 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_resume()
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/openbmc/linux/include/linux/
H A Dstmmac.h1 /* SPDX-License-Identifier: GPL-2.0-only */
51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
161 /* FPE link-partner hand-shaking mPacket type */
227 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
231 * mac_interface is the MAC-side interface, which may be the same
234 * MAC and PCS, and phy_interface describes the interface mode
238 /* phy_interface is the PHY-side interface - the interface used by
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddevices.c1 // SPDX-License-Identifier: GPL-2.0+
26 clrbits_le32(&ctrl->loop, in lpc32xx_uart_init()
33 setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id)); in lpc32xx_uart_init()
36 clrsetbits_le32(&ctrl->clkmode, in lpc32xx_uart_init()
40 /* Bypass pre-divider of UART clock */ in lpc32xx_uart_init()
42 &clk->u3clk + (uart_id - 3)); in lpc32xx_uart_init()
83 writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl); in lpc32xx_dma_init()
88 /* Enable MAC interface */ in lpc32xx_mac_init()
95 &clk->macclk_ctrl); in lpc32xx_mac_init()
101 writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl); in lpc32xx_mlc_nand_init()
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/openbmc/linux/drivers/net/ethernet/rdc/
H A Dr6040.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RDC R6040 Fast Ethernet MAC support
7 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
8 * Copyright (C) 2007-2012 Florian Fainelli <f.fainelli@gmail.com>
43 /* RDC MAC I/O Size */
46 /* MAX RDC MAC */
49 /* MAC registers */
57 #define MAC_RST 0x0001 /* Reset the MAC */
62 #define TM2TX 0x0001 /* Trigger MAC to transmit */
66 #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
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/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria10.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 tick-timer = &timer2;
26 u-boot,dm-pre-reloc;
30 #address-cells = <1>;
31 #size-cells = <0>;
32 enable-method = "altr,socfpga-a10-smp";
35 compatible = "arm,cortex-a9";
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H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
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/openbmc/linux/drivers/net/dsa/b53/
H A Db53_regs.h5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
101 /* Power-down mode control */
121 * Override Ports 0-7 State on devices with xMII interfaces (8 bit)
236 /* Ingress mirror divider register (16 bit) */
240 /* Ingress mirror MAC address register (48 bit) */
246 /* Egress mirror divider register (16 bit) */
249 /* Egress mirror MAC address register (48 bit) */
300 /* MAC Address Index Register (48 bit) */
306 /* ARL Table MAC/VID Entry N Registers (64 bit)
344 /* ARL Search MAC/VID Result (64 bit) */
/openbmc/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
284 __raw_writel(val, eth->base + reg); in mtk_w32()
289 return __raw_readl(eth->base + reg); in mtk_r32()
315 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c2 * Copyright © 2006-2007 Intel Corporation
65 int divider; member
108 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_lvds_get_hw_state()
113 wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain); in intel_lvds_get_hw_state()
117 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); in intel_lvds_get_hw_state()
119 intel_display_power_put(i915, encoder->power_domain, wakeref); in intel_lvds_get_hw_state()
127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_config()
131 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
133 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
143 crtc_state->hw.adjusted_mode.flags |= flags; in intel_lvds_get_config()
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