| /openbmc/u-boot/board/freescale/b4860qds/ |
| H A D | eth_b4860qds.c | 40 * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
73 * Lanes: A,B,C,D: SGMII in initialize_lane_to_slot()
74 * Lanes: E,F: Aur in initialize_lane_to_slot()
75 * Lanes: G,H: SRIO in initialize_lane_to_slot()
81 * Lanes: A,B: SGMII in initialize_lane_to_slot()
82 * Lanes: C,D: SRIO2 in initialize_lane_to_slot()
83 * Lanes: E,F,G,H: XAUI2 in initialize_lane_to_slot()
89 * Lanes: A,B,C,D: SGMII in initialize_lane_to_slot()
90 * Lanes: E,F,G,H: XAUI2 in initialize_lane_to_slot()
96 * Lanes: A,B,C,D: XAUI2 in initialize_lane_to_slot()
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| /openbmc/pldm/host-bmc/dbus/ |
| H A D | pcie_slot.cpp | 20 size_t PCIeSlot::lanes() const in lanes() function in pldm::dbus::PCIeSlot
23 lanes(); in lanes()
26 size_t PCIeSlot::lanes(size_t value) in lanes() function in pldm::dbus::PCIeSlot
29 lanes(value); in lanes()
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| H A D | pcie_slot.hpp | 39 /** Get value of Lanes */
40 size_t lanes() const override;
42 /** Set value of Lanes */
43 size_t lanes(size_t value) override;
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| H A D | pcie_device.hpp | 37 /** Get lanes in use */
40 /** Set lanes in use */
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | tegra210-p2371-2180.dts | 42 nvidia,lanes = "otg-1", "otg-2";
48 nvidia,lanes = "pcie-5", "pcie-6";
54 nvidia,lanes = "pcie-0";
60 nvidia,lanes = "pcie-1", "pcie-2",
67 nvidia,lanes = "sata-0";
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| H A D | tegra186-p2771-0000-500.dts | 19 nvidia,num-lanes = <4>;
24 nvidia,num-lanes = <0>;
29 nvidia,num-lanes = <1>;
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| H A D | tegra186-p2771-0000-000.dts | 19 nvidia,num-lanes = <2>;
24 nvidia,num-lanes = <1>;
29 nvidia,num-lanes = <1>;
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| H A D | imx6dl-sabresd.dts | 16 clock-lanes = <0>;
17 data-lanes = <1 2>;
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| H A D | imx6q-sabresd.dts | 21 clock-lanes = <0>;
22 data-lanes = <1 2>;
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| H A D | fsl-ls2080a.dtsi | 109 num-lanes = <4>;
124 num-lanes = <4>;
139 num-lanes = <8>;
154 num-lanes = <4>;
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| /openbmc/u-boot/drivers/video/ |
| H A D | anx9804.c | 24 * @lanes: Number of displayport lanes to use
28 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) in anx9804_init() argument
85 /* Power up and configure lanes */ in anx9804_init()
103 /* Set data-rate / lanes */ in anx9804_init()
105 i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes); in anx9804_init()
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| H A D | anx9804.h | 19 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
21 static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, in anx9804_init() argument
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| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | fsl_corenet_serdes.c | 63 } lanes[SRDS_MAX_LANES] = { variable
97 return lanes[lane].idx; in serdes_get_lane_idx()
102 return lanes[lane].bank; in serdes_get_bank_by_lane()
110 int bank = lanes[lane].bank; in serdes_lane_enabled()
111 int word = lanes[lane].lpd / 32; in serdes_lane_enabled()
112 int bit = lanes[lane].lpd % 32; in serdes_lane_enabled()
274 * want to enable the bank, whether we actually want to use the lanes or not,
279 * think that the lanes actually are disabled.
287 * If we're asked to disable all lanes, just pretend we're doing in enable_bank()
294 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in in enable_bank()
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| H A D | c29x_serdes.c | 18 u8 lanes[SRDS1_MAX_LANES]; member
64 enum srds_prtcl lane_prtcl = ptr->lanes[lane]; in fsl_serdes_init()
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| /openbmc/u-boot/doc/device-tree-bindings/net/ |
| H A D | ti,dp83867.txt | 11 - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
12 compensate for the board being designed with the lanes swapped.
14 TX/RX lanes.
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| /openbmc/bmcweb/redfish-core/lib/ |
| H A D | pcie_slots.hpp | 65 const size_t* lanes = nullptr; in onPcieSlotGetAllDone() local
71 generation, "Lanes", lanes, "SlotType", slotType, "HotPluggable", in onPcieSlotGetAllDone()
99 if (lanes != nullptr && *lanes != 0) in onPcieSlotGetAllDone()
101 slot["Lanes"] = *lanes; in onPcieSlotGetAllDone()
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | ls1012a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member
42 return ptr->lanes[lane]; in serdes_get_prtcl()
68 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
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| H A D | ls1046a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member
67 return ptr->lanes[lane]; in serdes_get_prtcl()
93 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
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| H A D | ls1043a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member
54 return ptr->lanes[lane]; in serdes_get_prtcl()
80 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
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| H A D | ls1088a_serdes.c | 11 u8 lanes[SRDS_MAX_LANES]; member
94 return ptr->lanes[lane]; in serdes_get_prtcl()
120 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | xusb-padctl-common.c | 68 if (strcmp(name, padctl->socdata->lanes[i].name) == 0) in tegra_xusb_padctl_find_lane()
69 return &padctl->socdata->lanes[i]; in tegra_xusb_padctl_find_lane()
84 len = ofnode_read_string_count(node, "nvidia,lanes"); in tegra_xusb_padctl_group_parse_dt()
86 pr_err("failed to parse \"nvidia,lanes\" property"); in tegra_xusb_padctl_group_parse_dt()
93 ret = ofnode_read_string_index(node, "nvidia,lanes", i, in tegra_xusb_padctl_group_parse_dt()
96 pr_err("failed to read string from \"nvidia,lanes\" property"); in tegra_xusb_padctl_group_parse_dt()
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| /openbmc/u-boot/drivers/video/bridge/ |
| H A D | anx6345.c | 270 u8 chipid, colordepth, lanes, data_rate, c; in anx6345_enable() local
322 /* Power up and configure lanes */ in anx6345_enable()
357 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) { in anx6345_enable()
361 lanes &= DP_MAX_LANE_COUNT_MASK; in anx6345_enable()
362 debug("%s: lanes: %d\n", __func__, (int)lanes); in anx6345_enable()
364 /* Set data-rate / lanes */ in anx6345_enable()
366 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes); in anx6345_enable()
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| /openbmc/u-boot/drivers/pci/ |
| H A D | Kconfig | 96 Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
97 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
98 with a total of 5 lanes. Some boards require this for Ethernet
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| H A D | pci_tegra.c | 380 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes, in tegra_pcie_get_xbar_config() argument
385 switch (lanes) { in tegra_pcie_get_xbar_config()
398 switch (lanes) { in tegra_pcie_get_xbar_config()
417 switch (lanes) { in tegra_pcie_get_xbar_config()
430 switch (lanes) { in tegra_pcie_get_xbar_config()
454 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) in tegra_pcie_parse_port_info() argument
459 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1); in tegra_pcie_parse_port_info()
461 pr_err("failed to parse \"nvidia,num-lanes\" property"); in tegra_pcie_parse_port_info()
465 *lanes = err; in tegra_pcie_parse_port_info()
487 u32 lanes = 0; in tegra_pcie_parse_dt() local
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/ |
| H A D | PCIeSlot.interface.yaml | 12 - name: Lanes
15 The maximum number of PCIe lanes supported by the slot
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