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/openbmc/linux/Documentation/devicetree/bindings/counter/
H A Dinterrupt-counter.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Interrupt counter
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 A generic interrupt counter to measure interrupt frequency. It was developed
17 Interrupts or gpios are required. If both are defined, the interrupt will
22 const: interrupt-counter
31 - compatible
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Damplc_dio200.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
[all …]
H A Damplc_dio200_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
[all …]
H A Ddas16m1.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Comedi driver for CIO-DAS16/M1
7 * COMEDI - Linux Control and Measurement Device Interface
13 * Description: CIO-DAS16/M1
15 * Devices: [Measurement Computing] CIO-DAS16/M1 (das16m1)
18 * This driver supports a single board - the CIO-DAS16/M1. As far as I know,
20 * CIO-DAS16/M1/16 is significantly different.
23 * a hard real-time interrupt (set the TRIG_RT flag in your struct comedi_cmd
25 * pulling the data across the ISA bus. I timed the interrupt handler, and it
28 * time in the interrupt handler.
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/openbmc/u-boot/include/
H A Dfsl_fman.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
18 u32 fmbm_ievr; /* interrupt event register */
19 u32 fmbm_ier; /* interrupt enable register */
20 u32 fmbm_ifr; /* interrupt force register */
35 u32 fmqm_eie; /* error interrupt event register */
36 u32 fmqm_eien; /* error interrupt enable register */
37 u32 fmqm_eif; /* error interrupt force register */
38 u32 fmqm_ie; /* interrupt event register */
39 u32 fmqm_ien; /* interrupt enable register */
[all …]
/openbmc/linux/drivers/counter/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Counter devices
8 select COUNTER
21 menuconfig COUNTER config
22 tristate "Counter support"
24 This enables counter device support through the Generic Counter
26 one or more of the counter device drivers below.
28 if COUNTER
31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
[all …]
H A Dinterrupt-cnt.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/counter.h>
8 #include <linux/interrupt.h>
15 #define INTERRUPT_CNT_NAME "interrupt-cnt"
29 struct counter_device *counter = dev_id; in interrupt_cnt_isr() local
30 struct interrupt_cnt_priv *priv = counter_priv(counter); in interrupt_cnt_isr()
32 atomic_inc(&priv->count); in interrupt_cnt_isr()
34 counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); in interrupt_cnt_isr()
39 static int interrupt_cnt_enable_read(struct counter_device *counter, in interrupt_cnt_enable_read() argument
42 struct interrupt_cnt_priv *priv = counter_priv(counter); in interrupt_cnt_enable_read()
[all …]
/openbmc/linux/drivers/net/wan/
H A Dhd64572.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
36 /* Interrupt Registers */
37 #define IVR 0x60 /* Interrupt Vector Register */
38 #define IMVR 0x64 /* Interrupt Modified Vector Register */
39 #define ITCR 0x68 /* Interrupt Control Register */
40 #define ISR0 0x6c /* Interrupt Status Register 0 */
41 #define ISR1 0x70 /* Interrupt Status Register 1 */
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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_86xx.h19 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
21 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
23 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
25 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
27 uint bptr; /* 0x20 - Boot Page Translation Register */
29 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
31 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
33 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
35 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
37 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dperf_event_v6.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv6 Performance counter handling code.
7 * ARMv6 has 2 configurable performance counters and a single cycle counter.
16 * the event bus. The procedure for disabling a configurable counter is:
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
18 * effectively stops the counter from counting.
19 * - disable the counter's interrupt generation (each counter has it's
20 * own interrupt enable bit).
21 * Once stopped, the counter value can be written as 0 to reset.
23 * To enable a counter:
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/openbmc/linux/arch/mips/kernel/
H A Dcevt-r4k.c7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
10 #include <linux/interrupt.h>
17 #include <asm/cevt-r4k.h>
28 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; in mips_next_event()
33 * calculate_min_delta() - Calculate a good minimum delta for mips_next_event().
67 cnt = read_c0_count() - cnt; in calculate_min_delta()
73 j, ARRAY_SIZE(buf1) - 1); in calculate_min_delta()
74 for (; l > k; --l) in calculate_min_delta()
75 buf1[l] = buf1[l - 1]; in calculate_min_delta()
85 if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) { in calculate_min_delta()
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/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91rm9200.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */
30 #define ATMEL_ID_TC1 18 /* Timer Counter 1 */
31 #define ATMEL_ID_TC2 19 /* Timer Counter 2 */
32 #define ATMEL_ID_TC3 20 /* Timer Counter 3 */
33 #define ATMEL_ID_TC4 21 /* Timer Counter 4 */
34 #define ATMEL_ID_TC5 22 /* Timer Counter 5 */
37 #define ATMEL_ID_IRQ0 25 /* Advanced Interrupt Controller */
38 #define ATMEL_ID_IRQ1 26 /* Advanced Interrupt Controller */
39 #define ATMEL_ID_IRQ2 27 /* Advanced Interrupt Controller */
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/openbmc/linux/drivers/net/ethernet/sun/
H A Dsunbmac.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
44 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
45 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
46 #define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */
47 #define CREG_BMASK 0x1cUL /* BigMAC Error Interrupt Mask*/
52 #define CREG_CCNT 0x30UL /* Collision Counter */
58 #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
63 #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
87 /* 0x004-->0x0fc, reserved */
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/openbmc/linux/drivers/net/ethernet/freescale/
H A Dgianfar.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
27 #include <linux/interrupt.h>
67 #define DRV_NAME "gfar-enet"
92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
95 #define TX_RING_MOD_MASK(size) (size-1)
96 #define RX_RING_MOD_MASK(size) (size-1)
108 * time described by a value of 1 in the interrupt
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/openbmc/qemu/tests/qtest/
H A Dcmsdk-apb-watchdog-test.c20 #include "libqtest-single.h"
56 * IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick
67 .machine = "mps2-an385",
84 hwaddr wdog_base = args->wdog_base; in test_watchdog()
85 int64_t tick = args->tick; in test_watchdog()
86 g_autofree gchar *cmdline = g_strdup_printf("-machine %s", args->machine); in test_watchdog()
108 /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ in test_watchdog()
127 g_autofree gchar *cmdline = g_strdup_printf("-machine %s", args->machine); in test_clock_change()
161 /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ in test_clock_change()
172 /* Tests the counter is not running after reset. */
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/openbmc/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Dpipeline.json21 …counter. This event can approximate elapsed time while the core was not in a halt state. It is cou…
29 …counter. This event can approximate elapsed time while the core was not in a halt state. It is cou…
36 …e the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eigh…
48 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
51 …- an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside…
56 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
60 …- an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside…
72 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
75 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
80 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
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/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
59 /* get rx dma good octet counter */
62 /* get rx dma good packet counter */
65 /* get tx dma good octet counter */
68 /* get tx dma good packet counter */
71 /* get msm rx errors counter register */
74 /* get msm rx unicast frames counter register */
77 /* get msm rx multicast frames counter register */
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - enum:
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/openbmc/linux/drivers/rtc/
H A Drtc-imxdi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
10 * Since the RTC framework performs API locking via rtc->ops_lock the
17 * DIER (DryIce Interrupt Enable Register) are the only exception. These
36 #define DTCMR 0x00 /* Time Counter MSB Reg */
37 #define DTCLR 0x04 /* Time Counter LSB Reg */
41 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
44 #define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
45 #define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
[all …]
/openbmc/linux/include/linux/mfd/
H A Dmotorola-cpcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2007-2009 Motorola, Inc.
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
33 #define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */
34 #define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */
35 #define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */
36 #define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dioc.h20 * All registers are 8-bit wide aligned on 32-bit boundary. Bad things
44 volatile u8 istat0; /* Interrupt status zero */
54 volatile u8 imask0; /* Interrupt mask zero */
56 volatile u8 istat1; /* Interrupt status one */
66 volatile u8 imask1; /* Interrupt mask one */
68 volatile u8 vmeistat; /* VME interrupt status */
70 volatile u8 cmeimask0; /* VME interrupt mask zero */
72 volatile u8 cmeimask1; /* VME interrupt mask one */
81 volatile u8 tcnt0; /* counter 0 */
83 volatile u8 tcnt1; /* counter 1 */
[all …]
/openbmc/linux/drivers/media/pci/cx88/
H A Dcx88-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * cx88x-hw.h - CX2388x register offsets
5 * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
68 #define MO_PCI_INTMSK 0x200040 // PCI interrupt mask
69 #define MO_PCI_INTSTAT 0x200044 // PCI interrupt status
70 #define MO_PCI_INTMSTAT 0x200048 // PCI interrupt masked status
71 #define MO_VID_INTMSK 0x200050 // Video interrupt mask
72 #define MO_VID_INTSTAT 0x200054 // Video interrupt status
73 #define MO_VID_INTMSTAT 0x200058 // Video interrupt masked status
74 #define MO_VID_INTSSTAT 0x20005C // Video interrupt set status
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/openbmc/linux/drivers/perf/
H A Dfsl_imx9_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/interrupt.h>
32 * 32bit counters monitor counter-specific events in addition to counting reference events
75 {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
86 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
106 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
127 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); in ddr_pmu_event_show()
245 PMU_FORMAT_ATTR(event, "config:0-7");
246 PMU_FORMAT_ATTR(counter, "config:8-15");
247 PMU_FORMAT_ATTR(axi_id, "config1:0-17");
[all …]
/openbmc/u-boot/drivers/timer/
H A Dcadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0
15 u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
16 u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
17 u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
18 u32 counter_cntrl1; /* 0xC - Counter Control 1 */
19 u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
20 u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
21 u32 counter_val1; /* 0x18 - Counter Control 1 */
22 u32 counter_val2; /* 0x1C - Counter Control 2 */
23 u32 counter_val3; /* 0x20 - Counter Control 3 */
[all …]
/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Dhubpi.h8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
30 #define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */
65 #define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A)
68 /* Regular Interrupt register checking. */
73 #define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */
74 #define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */
75 #define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */
76 #define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */
82 #define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */
83 #define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */
[all …]

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