Lines Matching +full:interrupt +full:- +full:counter

20  * All registers are 8-bit wide aligned on 32-bit boundary. Bad things
44 	volatile u8 istat0;		/* Interrupt status zero */
54 	volatile u8 imask0;		/* Interrupt mask zero */
56 	volatile u8 istat1;		/* Interrupt status one */
66 	volatile u8 imask1;		/* Interrupt mask one */
68 	volatile u8 vmeistat;		/* VME interrupt status */
70 	volatile u8 cmeimask0;		/* VME interrupt mask zero */
72 	volatile u8 cmeimask1;		/* VME interrupt mask one */
81 	volatile u8 tcnt0;		/* counter 0 */
83 	volatile u8 tcnt1;		/* counter 1 */
85 	volatile u8 tcnt2;		/* counter 2 */
91 #define SGINT_TCWORD_MOS	0x02	/* One-shot IRQ mode. */
100 #define SGINT_TCWORD_CALL	0x30	/* Full counter read/write */
101 #define SGINT_TCWORD_CNT0	0x00	/* Select counter zero */
102 #define SGINT_TCWORD_CNT1	0x40	/* Select counter one */
103 #define SGINT_TCWORD_CNT2	0x80	/* Select counter two */
113  * This is the constant we're using for calibrating the counter.