pci/cx88/cx88-reg.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * cx88x-hw.h - CX2388x register offsets
5  * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
68 #define MO_PCI_INTMSK       0x200040 // PCI interrupt mask
69 #define MO_PCI_INTSTAT      0x200044 // PCI interrupt status
70 #define MO_PCI_INTMSTAT     0x200048 // PCI interrupt masked status
71 #define MO_VID_INTMSK       0x200050 // Video interrupt mask
72 #define MO_VID_INTSTAT      0x200054 // Video interrupt status
73 #define MO_VID_INTMSTAT     0x200058 // Video interrupt masked status
74 #define MO_VID_INTSSTAT     0x20005C // Video interrupt set status
75 #define MO_AUD_INTMSK       0x200060 // Audio interrupt mask
76 #define MO_AUD_INTSTAT      0x200064 // Audio interrupt status
77 #define MO_AUD_INTMSTAT     0x200068 // Audio interrupt masked status
78 #define MO_AUD_INTSSTAT     0x20006C // Audio interrupt set status
79 #define MO_TS_INTMSK        0x200070 // Transport stream interrupt mask
80 #define MO_TS_INTSTAT       0x200074 // Transport stream interrupt status
81 #define MO_TS_INTMSTAT      0x200078 // Transport stream interrupt mask status
82 #define MO_TS_INTSSTAT      0x20007C // Transport stream interrupt set status
83 #define MO_VIP_INTMSK       0x200080 // VIP interrupt mask
84 #define MO_VIP_INTSTAT      0x200084 // VIP interrupt status
85 #define MO_VIP_INTMSTAT     0x200088 // VIP interrupt masked status
86 #define MO_VIP_INTSSTAT     0x20008C // VIP interrupt set status
87 #define MO_GPHST_INTMSK     0x200090 // Host interrupt mask
88 #define MO_GPHST_INTSTAT    0x200094 // Host interrupt status
89 #define MO_GPHST_INTMSTAT   0x200098 // Host interrupt masked status
90 #define MO_GPHST_INTSSTAT   0x20009C // Host interrupt set status
92 // DMA Channels 1-6 belong to SPIPE
96 // DMA Channels 9-20 belong to SPIPE
191 #define MO_FIELD_COUNT      0x310190 // field counter
198 #define MO_VIDY_GPCNT       0x31C020 // {16}RO Video Y general purpose counter
199 #define MO_VIDU_GPCNT       0x31C024 // {16}RO Video U general purpose counter
200 #define MO_VIDV_GPCNT       0x31C028 // {16}RO Video V general purpose counter
201 #define MO_VBI_GPCNT        0x31C02C // {16}RO VBI general purpose counter
205 #define MO_VBI_GPCNTRL      0x31C03C // {2}WO VBI general purpose counter
216 #define MO_AUDD_GPCNT       0x32C020 // {16}RO Audio down general purpose counter
217 #define MO_AUDU_GPCNT       0x32C024 // {16}RO Audio up general purpose counter
218 #define MO_AUDR_GPCNT       0x32C028 // {16}RO Audio RDS general purpose counter
434 #define MO_TS_GPCNT         0x33C020 // {16}RO TS general purpose counter
453 #define MO_VIPD_GPCNT       0x34C020 // {16}RO VIP down general purpose counter
454 #define MO_VIPU_GPCNT       0x34C024 // {16}RO VIP up general purpose counter
464 #define MO_VIP_INTCNTRL     0x34C05C // VIP Interrupt Control
482 #define MO_M2M_XSUM         0x35C028 // {32}RO  M2M XOR-Checksum
485 #define MO_TM_CNT_LDW       0x35C034 // {32}RO  Timer : Counter low dword
486 #define MO_TM_CNT_UW        0x35C038 // {16}RO  Timer : Counter high word
497 #define MO_INT1_MSK         0x35C060 // DMA RISC interrupt mask
498 #define MO_INT1_STAT        0x35C064 // DMA RISC interrupt status
499 #define MO_INT1_MSTAT       0x35C068 // DMA RISC interrupt masked status
528 #define MO_GPHST_MUX16      0x380064 // Host muxed 16-bit transfer parameters
531 #define MO_GPHSTD_GPCNT     0x35C020 // Host down general purpose counter
532 #define MO_GPHSTU_GPCNT     0x35C024 // Host up general purpose counter
577 /* Interrupt mask/status */