Lines Matching +full:interrupt +full:- +full:counter
1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/interrupt.h>
32 * 32bit counters monitor counter-specific events in addition to counting reference events
75 {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
86 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
106 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
127 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); in ddr_pmu_event_show()
245 PMU_FORMAT_ATTR(event, "config:0-7");
246 PMU_FORMAT_ATTR(counter, "config:8-15");
247 PMU_FORMAT_ATTR(axi_id, "config1:0-17");
248 PMU_FORMAT_ATTR(axi_mask, "config2:0-17");
271 static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_clear_counter() argument
273 if (counter == CYCLES_COUNTER) { in ddr_perf_clear_counter()
274 writel(0, pmu->base + PMC(counter) + 0x4); in ddr_perf_clear_counter()
275 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
277 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
281 static u64 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_read_counter() argument
286 if (counter != CYCLES_COUNTER) { in ddr_perf_read_counter()
287 val = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
291 /* special handling for reading 64bit cycle counter */ in ddr_perf_read_counter()
293 val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4); in ddr_perf_read_counter()
294 val_lower = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
295 } while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4)); in ddr_perf_read_counter()
308 ctrl = readl_relaxed(pmu->base + PMGC0); in ddr_perf_counter_global_config()
322 writel(ctrl, pmu->base + PMGC0); in ddr_perf_counter_global_config()
325 * Freeze all counters disabled, interrupt enabled, and freeze in ddr_perf_counter_global_config()
330 writel(ctrl, pmu->base + PMGC0); in ddr_perf_counter_global_config()
334 writel(ctrl, pmu->base + PMGC0); in ddr_perf_counter_global_config()
339 int counter, bool enable) in ddr_perf_counter_local_config() argument
343 ctrl_a = readl_relaxed(pmu->base + PMLCA(counter)); in ddr_perf_counter_local_config()
347 writel(ctrl_a, pmu->base + PMLCA(counter)); in ddr_perf_counter_local_config()
349 ddr_perf_clear_counter(pmu, counter); in ddr_perf_counter_local_config()
351 /* Freeze counter disabled, condition enabled, and program event.*/ in ddr_perf_counter_local_config()
356 writel(ctrl_a, pmu->base + PMLCA(counter)); in ddr_perf_counter_local_config()
358 /* Freeze counter. */ in ddr_perf_counter_local_config()
360 writel(ctrl_a, pmu->base + PMLCA(counter)); in ddr_perf_counter_local_config()
367 int event, counter; in ddr_perf_monitor_config() local
370 counter = (cfg & 0x0000FF00) >> 8; in ddr_perf_monitor_config()
372 pmcfg1 = readl_relaxed(pmu->base + PMCFG1); in ddr_perf_monitor_config()
374 if (counter == 2 && event == 73) in ddr_perf_monitor_config()
376 else if (counter == 2 && event != 73) in ddr_perf_monitor_config()
379 if (counter == 3 && event == 73) in ddr_perf_monitor_config()
381 else if (counter == 3 && event != 73) in ddr_perf_monitor_config()
384 if (counter == 4 && event == 73) in ddr_perf_monitor_config()
386 else if (counter == 4 && event != 73) in ddr_perf_monitor_config()
391 writel(pmcfg1, pmu->base + PMCFG1); in ddr_perf_monitor_config()
393 pmcfg2 = readl_relaxed(pmu->base + PMCFG2); in ddr_perf_monitor_config()
396 writel(pmcfg2, pmu->base + PMCFG2); in ddr_perf_monitor_config()
401 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_update()
402 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_update()
403 int counter = hwc->idx; in ddr_perf_event_update() local
406 new_raw_count = ddr_perf_read_counter(pmu, counter); in ddr_perf_event_update()
407 local64_add(new_raw_count, &event->count); in ddr_perf_event_update()
409 /* clear counter's value every time */ in ddr_perf_event_update()
410 ddr_perf_clear_counter(pmu, counter); in ddr_perf_event_update()
415 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_init()
416 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_init()
419 if (event->attr.type != event->pmu->type) in ddr_perf_event_init()
420 return -ENOENT; in ddr_perf_event_init()
422 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) in ddr_perf_event_init()
423 return -EOPNOTSUPP; in ddr_perf_event_init()
425 if (event->cpu < 0) { in ddr_perf_event_init()
426 dev_warn(pmu->dev, "Can't provide per-task data!\n"); in ddr_perf_event_init()
427 return -EOPNOTSUPP; in ddr_perf_event_init()
433 * periodically read when a hrtimer aka cpu-clock leader triggers). in ddr_perf_event_init()
435 if (event->group_leader->pmu != event->pmu && in ddr_perf_event_init()
436 !is_software_event(event->group_leader)) in ddr_perf_event_init()
437 return -EINVAL; in ddr_perf_event_init()
439 for_each_sibling_event(sibling, event->group_leader) { in ddr_perf_event_init()
440 if (sibling->pmu != event->pmu && in ddr_perf_event_init()
442 return -EINVAL; in ddr_perf_event_init()
445 event->cpu = pmu->cpu; in ddr_perf_event_init()
446 hwc->idx = -1; in ddr_perf_event_init()
453 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_start()
454 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_start()
455 int counter = hwc->idx; in ddr_perf_event_start() local
457 local64_set(&hwc->prev_count, 0); in ddr_perf_event_start()
459 ddr_perf_counter_local_config(pmu, event->attr.config, counter, true); in ddr_perf_event_start()
460 hwc->state = 0; in ddr_perf_event_start()
465 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_add()
466 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_add()
467 int cfg = event->attr.config; in ddr_perf_event_add()
468 int cfg1 = event->attr.config1; in ddr_perf_event_add()
469 int cfg2 = event->attr.config2; in ddr_perf_event_add()
470 int counter; in ddr_perf_event_add() local
472 counter = (cfg & 0x0000FF00) >> 8; in ddr_perf_event_add()
474 pmu->events[counter] = event; in ddr_perf_event_add()
475 pmu->active_events++; in ddr_perf_event_add()
476 hwc->idx = counter; in ddr_perf_event_add()
477 hwc->state |= PERF_HES_STOPPED; in ddr_perf_event_add()
490 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_stop()
491 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_stop()
492 int counter = hwc->idx; in ddr_perf_event_stop() local
494 ddr_perf_counter_local_config(pmu, event->attr.config, counter, false); in ddr_perf_event_stop()
497 hwc->state |= PERF_HES_STOPPED; in ddr_perf_event_stop()
502 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); in ddr_perf_event_del()
503 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_del()
507 pmu->active_events--; in ddr_perf_event_del()
508 hwc->idx = -1; in ddr_perf_event_del()
555 * Counters can generate an interrupt on an overflow when msb of a in ddr_perf_irq_handler()
556 * counter changes from 0 to 1. For the interrupt to be signalled, in ddr_perf_irq_handler()
559 * When an interrupt is signalled, PMGC0[FAC] is set by hardware and in ddr_perf_irq_handler()
561 * Software can clear the interrupt condition by resetting the performance in ddr_perf_irq_handler()
562 * monitor and clearing the most significant bit of the counter that in ddr_perf_irq_handler()
566 if (!pmu->events[i]) in ddr_perf_irq_handler()
569 event = pmu->events[i]; in ddr_perf_irq_handler()
584 if (cpu != pmu->cpu) in ddr_perf_offline_cpu()
591 perf_pmu_migrate_context(&pmu->pmu, cpu, target); in ddr_perf_offline_cpu()
592 pmu->cpu = target; in ddr_perf_offline_cpu()
594 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu))); in ddr_perf_offline_cpu()
610 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL); in ddr_perf_probe()
612 return -ENOMEM; in ddr_perf_probe()
614 ddr_perf_init(pmu, base, &pdev->dev); in ddr_perf_probe()
616 pmu->devtype_data = of_device_get_match_data(&pdev->dev); in ddr_perf_probe()
620 pmu->id = ida_simple_get(&ddr_ida, 0, 0, GFP_KERNEL); in ddr_perf_probe()
621 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", pmu->id); in ddr_perf_probe()
623 ret = -ENOMEM; in ddr_perf_probe()
627 pmu->cpu = raw_smp_processor_id(); in ddr_perf_probe()
631 dev_err(&pdev->dev, "Failed to add callbacks for multi state\n"); in ddr_perf_probe()
634 pmu->cpuhp_state = ret; in ddr_perf_probe()
637 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_probe()
639 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret); in ddr_perf_probe()
650 ret = devm_request_irq(&pdev->dev, irq, ddr_perf_irq_handler, in ddr_perf_probe()
654 dev_err(&pdev->dev, "Request irq failed: %d", ret); in ddr_perf_probe()
658 pmu->irq = irq; in ddr_perf_probe()
659 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)); in ddr_perf_probe()
661 dev_err(pmu->dev, "Failed to set interrupt affinity\n"); in ddr_perf_probe()
665 ret = perf_pmu_register(&pmu->pmu, name, -1); in ddr_perf_probe()
672 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_probe()
674 cpuhp_remove_multi_state(pmu->cpuhp_state); in ddr_perf_probe()
677 ida_simple_remove(&ddr_ida, pmu->id); in ddr_perf_probe()
678 dev_warn(&pdev->dev, "i.MX9 DDR Perf PMU failed (%d), disabled\n", ret); in ddr_perf_probe()
686 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); in ddr_perf_remove()
687 cpuhp_remove_multi_state(pmu->cpuhp_state); in ddr_perf_remove()
689 perf_pmu_unregister(&pmu->pmu); in ddr_perf_remove()
691 ida_simple_remove(&ddr_ida, pmu->id); in ddr_perf_remove()
698 .name = "imx9-ddr-pmu",