u-boot/include/fsl_fman.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
5  * Copyright 2010-2011 Freescale Semiconductor, Inc.
18 	u32	fmbm_ievr;	/* interrupt event register */
19 	u32	fmbm_ier;	/* interrupt enable register */
20 	u32	fmbm_ifr;	/* interrupt force register */
35 	u32	fmqm_eie;	/* error interrupt event register */
36 	u32	fmqm_eien;	/* error interrupt enable register */
37 	u32	fmqm_eif;	/* error interrupt force register */
38 	u32	fmqm_ie;	/* interrupt event register */
39 	u32	fmqm_ien;	/* interrupt enable register */
40 	u32	fmqm_if;	/* interrupt force register */
43 	u32	fmqm_etfc;	/* enqueue total frame counter */
44 	u32	fmqm_dtfc;	/* dequeue total frame counter */
45 	u32	fmqm_dc0;	/* dequeue counter 0 */
46 	u32	fmqm_dc1;	/* dequeue counter 1 */
47 	u32	fmqm_dc2;	/* dequeue counter 2 */
48 	u32	fmqm_dc3;	/* dequeue counter 3 */
49 	u32	fmqm_dfnoc;	/* dequeue FQID not override counter */
50 	u32	fmqm_dfcc;	/* dequeue FQID from context counter */
51 	u32	fmqm_dffc;	/* dequeue FQID from FD counter */
52 	u32	fmqm_dcc;	/* dequeue confirm counter */
92 	u32 fmbm_acnt[0x8];	/* allocate counter */
99 	u32 fmbm_rfbc;		/* Rx bad frames counter */
100 	u32 fmbm_rlfc;		/* Rx large frames counter */
101 	u32 fmbm_rffc;		/* Rx filter frames counter */
102 	u32 fmbm_rfdc;		/* Rx frame discard counter */
103 	u32 fmbm_rfldec;	/* Rx frames list DMA error counter */
104 	u32 fmbm_rodc;		/* Rx out of buffers discard counter */
105 	u32 fmbm_rbdc;		/* Rx buffers deallocate counter */
109 	u32 fmbm_rccn;		/* Rx cycle counter */
110 	u32 fmbm_rtuc;		/* Rx tasks utilization counter */
111 	u32 fmbm_rrquc;		/* Rx receive queue utilization counter */
112 	u32 fmbm_rduc;		/* Rx DMA utilization counter */
113 	u32 fmbm_rfuc;		/* Rx FIFO utilization counter */
114 	u32 fmbm_rpac;		/* Rx pause activation counter */
119 /* FMBM_RCFG - Rx configuration */
124 /* FMBM_RST - Rx status */
127 /* FMBM_RFCA - Rx frame command attributes */
132 /* FMBM_RSTC - Rx statistics */
151 	u32 fmbm_tfrc;	/* Tx frame counter */
152 	u32 fmbm_tfdc;	/* Tx frames discard counter */
153 	u32 fmbm_tfledc;/* Tx frame length error discard counter */
154 	u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
155 	u32 fmbm_tbdc;	/* Tx buffers deallocate counter */
159 	u32 fmbm_tccn;	/* Tx cycle counter */
160 	u32 fmbm_ttuc;	/* Tx tasks utilization counter */
161 	u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
162 	u32 fmbm_tduc;	/* Tx DMA utilization counter */
163 	u32 fmbm_tfuc;	/* Tx FIFO utilization counter */
168 /* FMBM_TCFG - Tx configuration */
172 /* FMBM_TST - Tx status */
175 /* FMBM_TFCA - Tx frame command attributes */
180 /* FMBM_TSTC - Tx statistics counters */
183 /* FMBM_INIT - BMI initialization register */
186 /* FMBM_CFG1 - BMI configuration 1 */
191 /* FMBM_IEVR - interrupt event */
197 /* FMBM_IER - interrupt enable */
198 #define FMBM_IER_PECE		0x80000000 /* PEC interrupt enable */
199 #define FMBM_IER_LECE		0x40000000 /* LEC interrupt enable */
200 #define FMBM_IER_SECE		0x20000000 /* SEC interrupt enable */
204 /* FMBM_PP - BMI Port Parameters */
206 #define FMBM_PP_MXT(x)		(((x-1) << 24) & FMBM_PP_MXT_MASK)
208 #define FMBM_PP_MXD(x)		(((x-1) << 8) & FMBM_PP_MXD_MASK)
210 /* FMBM_PFS - BMI Port FIFO Size */
214 /* FMQM_GC - global configuration */
223 /* FMQM_EIE - error interrupt event register */
224 #define FMQM_EIE_DEE		0x80000000 /* double-bit ECC error */
228 /* FMQM_EIEN - error interrupt enable register */
229 #define FMQM_EIEN_DEEN		0x80000000 /* double-bit ECC error */
233 /* FMQM_IE - interrupt event register */
234 #define FMQM_IE_SEE		0x80000000 /* single-bit ECC error detected */
237 /* FMQM_IEN - interrupt enable register */
238 #define FMQM_IEN_SEE		0x80000000 /* single-bit ECC err IRQ enable */
241 /* NIA - next invoked action */
275 	u32	fmdmdcr;	/* debug counter */
278 	u32	fmdmplr[32];	/* FM DMA PID-LIODN # register */
282 /* FMDMSR - Fman DMA status register */
300 /* FMDMMR - FMan DMA mode register */
311 	u32	fmrie;		/* rams interrupt enable */
312 	u32	fpmfcevent[0x4];/* FMan controller event 0-3 */
314 	u32	fpmfcmask[0x4];	/* FMan controller mask 0-3 */
322 	u32	fpmdrd[0x4];	/* data_ram data 0-3 */
332 	u32	fpmcev[0x4];	/* CPU event 0-3 */
340 /* FMFP_PRC - FPM Port_ID Control Register */
351 /* FMFP_EE - FPM event and enable register */
356 #define FMFPEE_DECC_EN		0x00008000 /* double ECC interrupt enable */
357 #define FMFPEE_STL_EN		0x00004000 /* stall of task interrupt enable */
358 #define FMFPEE_SECC_EN		0x00002000 /* single ECC err interrupt enable */
368 /* FMFP_RCR - FMan Rams Control and Event */
398 	u8	res1[0x1000 - 0x138];