| /openbmc/linux/drivers/gpu/drm/etnaviv/ |
| H A D | etnaviv_iommu_v2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Etnaviv Project
7 #include <linux/dma-mapping.h>
32 unsigned short id; member
52 drm_mm_takedown(&context->mm); in etnaviv_iommuv2_free()
55 if (v2_context->stlb_cpu[i]) in etnaviv_iommuv2_free()
56 dma_free_wc(context->global->dev, SZ_4K, in etnaviv_iommuv2_free()
57 v2_context->stlb_cpu[i], in etnaviv_iommuv2_free()
58 v2_context->stlb_dma[i]); in etnaviv_iommuv2_free()
61 dma_free_wc(context->global->dev, SZ_4K, v2_context->mtlb_cpu, in etnaviv_iommuv2_free()
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| H A D | etnaviv_buffer.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2018 Etnaviv Project
27 u32 *vaddr = (u32 *)buffer->vaddr; in OUT()
29 BUG_ON(buffer->user_size >= buffer->size); in OUT()
31 vaddr[buffer->user_size / 4] = data; in OUT()
32 buffer->user_size += 4; in OUT()
40 buffer->user_size = ALIGN(buffer->user_size, 8); in CMD_LOAD_STATE()
51 buffer->user_size = ALIGN(buffer->user_size, 8); in CMD_END()
59 buffer->user_size = ALIGN(buffer->user_size, 8); in CMD_WAIT()
67 buffer->user_size = ALIGN(buffer->user_size, 8); in CMD_LINK()
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| H A D | etnaviv_perfmon.c | 1 // SPDX-License-Identifier: GPL-2.0
18 u32 (*sample)(struct etnaviv_gpu *gpu,
40 static u32 perf_reg_read(struct etnaviv_gpu *gpu, in perf_reg_read() argument
44 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
46 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
49 static inline void pipe_select(struct etnaviv_gpu *gpu, u32 clock, unsigned pipe) in pipe_select() argument
54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_select()
57 static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu, in pipe_perf_reg_read() argument
61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read()
65 for (i = 0; i < gpu->identity.pixel_pipes; i++) { in pipe_perf_reg_read()
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| H A D | etnaviv_drv.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2015-2018 Etnaviv Project
32 int id; member
39 struct etnaviv_gpu *gpu[ETNA_MAX_PIPES]; member
72 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);
73 u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);
74 u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id);
75 void etnaviv_buffer_end(struct etnaviv_gpu *gpu);
76 void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);
77 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
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| /openbmc/linux/drivers/gpu/drm/msm/ |
| H A D | msm_ringbuffer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 struct msm_fence_context *fctx = submit->ring->fctx; in msm_job_run()
18 struct msm_gpu *gpu = submit->gpu; in msm_job_run() local
19 struct msm_drm_private *priv = gpu->dev->dev_private; in msm_job_run()
22 msm_fence_init(submit->hw_fence, fctx); in msm_job_run()
24 mutex_lock(&priv->lru.lock); in msm_job_run()
26 for (i = 0; i < submit->nr_bos; i++) { in msm_job_run()
27 struct drm_gem_object *obj = submit->bos[i].obj; in msm_job_run()
30 submit->bos[i].flags &= ~BO_PINNED; in msm_job_run()
33 mutex_unlock(&priv->lru.lock); in msm_job_run()
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| H A D | msm_gpu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/adreno-smmu-priv.h>
47 int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
49 int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
51 int (*hw_init)(struct msm_gpu *gpu);
56 int (*ucode_load)(struct msm_gpu *gpu);
58 int (*pm_suspend)(struct msm_gpu *gpu);
59 int (*pm_resume)(struct msm_gpu *gpu);
60 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
61 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
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| H A D | msm_submitqueue.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 struct msm_gpu *gpu, int sysprof) in msm_file_private_set_sysprof() argument
21 return -EINVAL; in msm_file_private_set_sysprof()
23 pm_runtime_get_sync(&gpu->pdev->dev); in msm_file_private_set_sysprof()
26 refcount_inc(&gpu->sysprof_active); in msm_file_private_set_sysprof()
33 switch (ctx->sysprof) { in msm_file_private_set_sysprof()
35 pm_runtime_put_autosuspend(&gpu->pdev->dev); in msm_file_private_set_sysprof()
38 refcount_dec(&gpu->sysprof_active); in msm_file_private_set_sysprof()
44 ctx->sysprof = sysprof; in msm_file_private_set_sysprof()
55 for (i = 0; i < ARRAY_SIZE(ctx->entities); i++) { in __msm_file_private_destroy()
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| /openbmc/linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a5xx_preempt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 enum preempt_state cur = atomic_cmpxchg(&a5xx_gpu->preempt_state, in try_preempt_state()
25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
48 spin_lock_irqsave(&ring->preempt_lock, flags); in update_wptr()
50 spin_unlock_irqrestore(&ring->preempt_lock, flags); in update_wptr()
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
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| H A D | a6xx_gpu_state.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
99 list_add_tail(&obj->node, &a6xx_state->objs); in state_kcalloc()
100 return &obj->data; in state_kcalloc()
114 * Allocate 1MB for the crashdumper scratch region - 8k for the script and
118 #define A6XX_CD_DATA_SIZE (SZ_1M - 8192)
120 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
123 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
124 SZ_1M, MSM_BO_WC, gpu->aspace, in a6xx_crashdumper_init()
125 &dumper->bo, &dumper->iova); in a6xx_crashdumper_init()
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| H A D | a5xx_gpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
10 #include <linux/nvmem-consumer.h>
17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
26 if (a5xx_gpu->has_whereami) { in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
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| H A D | a6xx_gpu.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
14 #include <linux/soc/qcom/llcc-qcom.h>
18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
24 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
39 if (!adreno_idle(gpu, ring)) in a6xx_idle()
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| H A D | a5xx_power.c | 1 // SPDX-License-Identifier: GPL-2.0-only
103 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument
105 struct drm_device *dev = gpu->dev; in _get_mvolts()
106 struct msm_drm_private *priv = dev->dev_private; in _get_mvolts()
107 struct platform_device *pdev = priv->gpu_pdev; in _get_mvolts()
111 opp = dev_pm_opp_find_freq_exact(&pdev->dev, freq, true); in _get_mvolts()
122 static void a530_lm_setup(struct msm_gpu *gpu) in a530_lm_setup() argument
124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a530_lm_setup()
130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
133 /* Hard code the A530 GPU thermal sensor ID for the GPMU */ in a530_lm_setup()
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| /openbmc/linux/drivers/gpu/vga/ |
| H A D | vga_switcheroo.c | 2 * vga_switcheroo.c - Support for laptop with dual GPU using one set of outputs
33 #include <linux/apple-gmux.h>
66 * for the inactive GPU.) Also, muxes are often used to cut power to the
67 * discrete GPU while it is not used.
71 * handler to control the power state of the discrete GPU, its ->switchto
72 * callback is a no-op for obvious reasons. The discrete GPU is often equipped
75 * suspend/resume order when changing the discrete GPU's power state. In total
77 * client (on the discrete GPU). The code is mostly prepared to support
80 * The GPU to which the outputs are currently switched is called the
81 * active client in vga_switcheroo parlance. The GPU not in use is the
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| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | nvidia-pmu.rst | 9 * NVLink-C2C0
10 * NVLink-C2C1
15 ----------
19 PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes
22 the driver provides "cpumask" sysfs attribute to show the CPU id used to handle
29 -------
32 strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
37 see /sys/bus/event_sources/devices/nvidia_scf_pmu_<socket-id>.
41 * Count event id 0x0 in socket 0::
43 perf stat -a -e nvidia_scf_pmu_0/event=0x0/
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| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_atpx_handler.c | 1 // SPDX-License-Identifier: GPL-2.0-only
37 /* handle for device - and atpx */
81 * radeon_atpx_call - call an ATPX method
106 atpx_arg_elements[1].buffer.length = params->length; in radeon_atpx_call()
107 atpx_arg_elements[1].buffer.pointer = params->pointer; in radeon_atpx_call()
128 * radeon_atpx_parse_functions - parse supported functions
139 f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED; in radeon_atpx_parse_functions()
140 f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
141 f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
142 f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
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| /openbmc/linux/drivers/gpu/drm/i915/gvt/ |
| H A D | vgpu.c | 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
40 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in populate_pvinfo_page()
46 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; in populate_pvinfo_page()
66 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); in populate_pvinfo_page()
73 drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE); in populate_pvinfo_page()
77 * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU
82 * vGPU on same physical GPU depending on available resource. Each vGPU
98 * intel_gvt_init_vgpu_types - initialize vGPU type list
106 unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; in intel_gvt_init_vgpu_types()
107 unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; in intel_gvt_init_vgpu_types()
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| /openbmc/linux/Documentation/devicetree/bindings/display/msm/ |
| H A D | gpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/display/msm/gpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
16 - description: |
18 figure out the chip-id.
20 … - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
21 - const: qcom,adreno
22 - description: |
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| /openbmc/linux/Documentation/gpu/ |
| H A D | msm-crash-dump.rst | 7 Following a GPU hang the MSM driver outputs debugging information via
14 by a (-).
17 --------
35 ID of the GPU that generated the crash formatted as
38 rbbm-status
39 The current value of RBBM_STATUS which shows what top level GPU
44 identified with an id number.
46 id
47 Ringbuffer ID (0 based index). Each ringbuffer in the section
48 will have its own unique id.
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_atpx_handler.c | 1 // SPDX-License-Identifier: GPL-2.0-only
49 /* handle for device - and atpx */
105 * amdgpu_atpx_call - call an ATPX method
130 atpx_arg_elements[1].buffer.length = params->length; in amdgpu_atpx_call()
131 atpx_arg_elements[1].buffer.pointer = params->pointer; in amdgpu_atpx_call()
152 * amdgpu_atpx_parse_functions - parse supported functions
163 f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED; in amdgpu_atpx_parse_functions()
164 f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED; in amdgpu_atpx_parse_functions()
165 f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED; in amdgpu_atpx_parse_functions()
166 f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED; in amdgpu_atpx_parse_functions()
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| H A D | psp_gfx_if.h | 38 * Command ID must be between 0x00010000 and 0x000F0000.
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
53 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
57 /*-----------------------------------------------------------------------------
59 GPU Virtual Addresses.
64 * SRBM-to-PSP mailbox registers (total 8 registers).
73 … volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
74 …volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
108 /* PSP boot config sub-commands */
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| /openbmc/linux/include/linux/ |
| H A D | vga_switcheroo.h | 2 * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs
39 * enum vga_switcheroo_handler_flags_t - handler flags bitmask
45 * GPU needs to train the link and communicate the link parameters to the
46 * inactive GPU (mediated by vga_switcheroo). The inactive GPU may then
47 * skip the AUX handshake and set up its output with these pre-calibrated
59 * enum vga_switcheroo_state - client power state
76 * enum vga_switcheroo_client_id - client identifier
78 * Determining the id requires the handler, so GPUs are given their
79 * true id in a delayed fashion in vga_switcheroo_enable()
94 * struct vga_switcheroo_handler - handler callbacks
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| /openbmc/linux/include/uapi/drm/ |
| H A D | amdgpu_drm.h | 1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
83 * pages of system memory, allows GPU access system memory in a linearized
89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
153 * May depend on GPU instructions to flush caches explicitly
159 /* Flag that BO should not be cached by GPU. Coherent without having to flush
160 * GPU caches explicitly
235 /* GPU reset status */
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| /openbmc/linux/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_pm.c | 2 * SPDX-License-Identifier: MIT
28 GEM_TRACE("%s\n", dev_name(i915->drm.dev)); in i915_gem_suspend()
30 intel_wakeref_auto(&i915->runtime_pm.userfault_wakeref, 0); in i915_gem_suspend()
31 flush_workqueue(i915->wq); in i915_gem_suspend()
37 * leaves the i915->kernel_context still active when in i915_gem_suspend()
38 * we actually suspend, and its image in memory may not match the GPU in i915_gem_suspend()
51 int ret = 0, id; in lmem_restore() local
53 for_each_memory_region(mr, i915, id) { in lmem_restore()
54 if (mr->type == INTEL_MEMORY_LOCAL) { in lmem_restore()
67 int ret = 0, id; in lmem_suspend() local
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| /openbmc/linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_topology.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
45 /* topology_device_list - Master list of all topology devices */
59 if (top_dev->proximity_domain == proximity_domain) { in kfd_topology_device_by_proximity_domain_no_lock()
89 if (top_dev->gpu_id == gpu_id) { in kfd_topology_device_by_id()
107 return top_dev->gpu; in kfd_device_by_id()
118 if (top_dev->gpu && top_dev->gpu->adev->pdev == pdev) { in kfd_device_by_pci_dev()
119 device = top_dev->gpu; in kfd_device_by_pci_dev()
137 list_del(&dev->list); in kfd_release_topology_device()
139 while (dev->mem_props.next != &dev->mem_props) { in kfd_release_topology_device()
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| /openbmc/linux/drivers/platform/x86/ |
| H A D | apple-gmux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2012 Andreas Heider <andreas@meetr.de>
19 #include <linux/apple-gmux.h>
32 * A `Lattice XP2`_ on pre-retinas, a `Renesas R4F2113`_ on pre-T2 retinas.
36 * the voltage regulators of the discrete GPU, drives the display panel power,
41 * dual GPUs but no built-in display.)
45 * to access a pre-retina gmux are infixed ``_pio_``, those for a pre-T2
54 * https://www.nxp.com/docs/en/data-sheet/PCAL6524.pdf
112 return inb(gmux_data->iostart + port); in gmux_pio_read8()
118 outb(val, gmux_data->iostart + port); in gmux_pio_write8()
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