181629cbaSAlex Deucher /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 281629cbaSAlex Deucher * 381629cbaSAlex Deucher * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 481629cbaSAlex Deucher * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 581629cbaSAlex Deucher * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 681629cbaSAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 781629cbaSAlex Deucher * 881629cbaSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 981629cbaSAlex Deucher * copy of this software and associated documentation files (the "Software"), 1081629cbaSAlex Deucher * to deal in the Software without restriction, including without limitation 1181629cbaSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1281629cbaSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1381629cbaSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1481629cbaSAlex Deucher * 1581629cbaSAlex Deucher * The above copyright notice and this permission notice shall be included in 1681629cbaSAlex Deucher * all copies or substantial portions of the Software. 1781629cbaSAlex Deucher * 1881629cbaSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1981629cbaSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2081629cbaSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2181629cbaSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2281629cbaSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2381629cbaSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2481629cbaSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2581629cbaSAlex Deucher * 2681629cbaSAlex Deucher * Authors: 2781629cbaSAlex Deucher * Kevin E. Martin <martin@valinux.com> 2881629cbaSAlex Deucher * Gareth Hughes <gareth@valinux.com> 2981629cbaSAlex Deucher * Keith Whitwell <keith@tungstengraphics.com> 3081629cbaSAlex Deucher */ 3181629cbaSAlex Deucher 3281629cbaSAlex Deucher #ifndef __AMDGPU_DRM_H__ 3381629cbaSAlex Deucher #define __AMDGPU_DRM_H__ 3481629cbaSAlex Deucher 35b3fcf36aSMichel Dänzer #include "drm.h" 3681629cbaSAlex Deucher 37cfa7152fSEmil Velikov #if defined(__cplusplus) 38cfa7152fSEmil Velikov extern "C" { 39cfa7152fSEmil Velikov #endif 40cfa7152fSEmil Velikov 4181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_CREATE 0x00 4281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_MMAP 0x01 4381629cbaSAlex Deucher #define DRM_AMDGPU_CTX 0x02 4481629cbaSAlex Deucher #define DRM_AMDGPU_BO_LIST 0x03 4581629cbaSAlex Deucher #define DRM_AMDGPU_CS 0x04 4681629cbaSAlex Deucher #define DRM_AMDGPU_INFO 0x05 4781629cbaSAlex Deucher #define DRM_AMDGPU_GEM_METADATA 0x06 4881629cbaSAlex Deucher #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4981629cbaSAlex Deucher #define DRM_AMDGPU_GEM_VA 0x08 5081629cbaSAlex Deucher #define DRM_AMDGPU_WAIT_CS 0x09 5181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_OP 0x10 5281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_USERPTR 0x11 53eef18a82SJunwei Zhang #define DRM_AMDGPU_WAIT_FENCES 0x12 54cfbcacf4SChunming Zhou #define DRM_AMDGPU_VM 0x13 557ca24cf2SMarek Olšák #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 5652c6a62cSAndres Rodriguez #define DRM_AMDGPU_SCHED 0x15 5781629cbaSAlex Deucher 5881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 6081629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 6181629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 6281629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 6381629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 6481629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 6581629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 6634b5f6a6SChristian König #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 6781629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70eef18a82SJunwei Zhang #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71cfbcacf4SChunming Zhou #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 727ca24cf2SMarek Olšák #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 7352c6a62cSAndres Rodriguez #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 7481629cbaSAlex Deucher 75b646c1dcSSamuel Li /** 76b646c1dcSSamuel Li * DOC: memory domains 77b646c1dcSSamuel Li * 78b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79b646c1dcSSamuel Li * Memory in this pool could be swapped out to disk if there is pressure. 80b646c1dcSSamuel Li * 81b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82b646c1dcSSamuel Li * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83326db0dcSYann Dirson * pages of system memory, allows GPU access system memory in a linearized 84b646c1dcSSamuel Li * fashion. 85b646c1dcSSamuel Li * 86b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87b646c1dcSSamuel Li * carved out by the BIOS. 88b646c1dcSSamuel Li * 89b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90b646c1dcSSamuel Li * across shader threads. 91b646c1dcSSamuel Li * 92b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93b646c1dcSSamuel Li * execution of all the waves on a device. 94b646c1dcSSamuel Li * 95b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96b646c1dcSSamuel Li * for appending data. 97*89927235SAlex Deucher * 98*89927235SAlex Deucher * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 99*89927235SAlex Deucher * signalling user mode queues. 100b646c1dcSSamuel Li */ 10181629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_CPU 0x1 10281629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GTT 0x2 10381629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_VRAM 0x4 10481629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GDS 0x8 10581629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GWS 0x10 10681629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_OA 0x20 107*89927235SAlex Deucher #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 1083f188453SChunming Zhou #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 1093f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GTT | \ 1103f188453SChunming Zhou AMDGPU_GEM_DOMAIN_VRAM | \ 1113f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GDS | \ 1123f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GWS | \ 113*89927235SAlex Deucher AMDGPU_GEM_DOMAIN_OA | \ 114*89927235SAlex Deucher AMDGPU_GEM_DOMAIN_DOORBELL) 11581629cbaSAlex Deucher 11681629cbaSAlex Deucher /* Flag that CPU access will be required for the case of VRAM domain */ 11781629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 11881629cbaSAlex Deucher /* Flag that CPU access will not work, this VRAM domain is invisible */ 11981629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 12081629cbaSAlex Deucher /* Flag that USWC attributes should be used for GTT */ 12188671288SJammy Zhou #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 1224fea83ffSFlora Cui /* Flag that the memory should be in VRAM and cleared */ 1234fea83ffSFlora Cui #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 12403f48dd5SChristian König /* Flag that allocating the BO should use linear VRAM */ 12503f48dd5SChristian König #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 126e1eb899bSChristian König /* Flag that BO is always valid in this VM */ 127e1eb899bSChristian König #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 128177ae09bSAndres Rodriguez /* Flag that BO sharing will be explicitly synchronized */ 129177ae09bSAndres Rodriguez #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 130959a2091SYong Zhao /* Flag that indicates allocating MQD gart on GFX9, where the mtype 131fa5bde80SYong Zhao * for the second page onward should be set to NC. It should never 132fa5bde80SYong Zhao * be used by user space applications. 133959a2091SYong Zhao */ 134fa5bde80SYong Zhao #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 135d8f4981eSFelix Kuehling /* Flag that BO may contain sensitive data that must be wiped before 136d8f4981eSFelix Kuehling * releasing the memory 137d8f4981eSFelix Kuehling */ 138d8f4981eSFelix Kuehling #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 13935ce0060SAlex Deucher /* Flag that BO will be encrypted and that the TMZ bit should be 14035ce0060SAlex Deucher * set in the PTEs when mapping this buffer via GPUVM or 14135ce0060SAlex Deucher * accessing it with various hw blocks 14235ce0060SAlex Deucher */ 14335ce0060SAlex Deucher #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 144b453e42aSFelix Kuehling /* Flag that BO will be used only in preemptible context, which does 145b453e42aSFelix Kuehling * not require GTT memory accounting 146b453e42aSFelix Kuehling */ 147b453e42aSFelix Kuehling #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 148fab2cc83SChristian König /* Flag that BO can be discarded under memory pressure without keeping the 149fab2cc83SChristian König * content. 150fab2cc83SChristian König */ 151fab2cc83SChristian König #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 152d1a372afSFelix Kuehling /* Flag that BO is shared coherently between multiple devices or CPU threads. 153d1a372afSFelix Kuehling * May depend on GPU instructions to flush caches explicitly 154d1a372afSFelix Kuehling * 155d1a372afSFelix Kuehling * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 156d1a372afSFelix Kuehling * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 157d1a372afSFelix Kuehling */ 158d1a372afSFelix Kuehling #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 159d1a372afSFelix Kuehling /* Flag that BO should not be cached by GPU. Coherent without having to flush 160d1a372afSFelix Kuehling * GPU caches explicitly 161d1a372afSFelix Kuehling * 162d1a372afSFelix Kuehling * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 163d1a372afSFelix Kuehling * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 164d1a372afSFelix Kuehling */ 165d1a372afSFelix Kuehling #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 16681629cbaSAlex Deucher 16781629cbaSAlex Deucher struct drm_amdgpu_gem_create_in { 16881629cbaSAlex Deucher /** the requested memory size */ 1692ce9dde0SMikko Rapeli __u64 bo_size; 17081629cbaSAlex Deucher /** physical start_addr alignment in bytes for some HW requirements */ 1712ce9dde0SMikko Rapeli __u64 alignment; 17281629cbaSAlex Deucher /** the requested memory domains */ 1732ce9dde0SMikko Rapeli __u64 domains; 17481629cbaSAlex Deucher /** allocation flags */ 1752ce9dde0SMikko Rapeli __u64 domain_flags; 17681629cbaSAlex Deucher }; 17781629cbaSAlex Deucher 17881629cbaSAlex Deucher struct drm_amdgpu_gem_create_out { 17981629cbaSAlex Deucher /** returned GEM object handle */ 1802ce9dde0SMikko Rapeli __u32 handle; 1812ce9dde0SMikko Rapeli __u32 _pad; 18281629cbaSAlex Deucher }; 18381629cbaSAlex Deucher 18481629cbaSAlex Deucher union drm_amdgpu_gem_create { 18581629cbaSAlex Deucher struct drm_amdgpu_gem_create_in in; 18681629cbaSAlex Deucher struct drm_amdgpu_gem_create_out out; 18781629cbaSAlex Deucher }; 18881629cbaSAlex Deucher 18981629cbaSAlex Deucher /** Opcode to create new residency list. */ 19081629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_CREATE 0 19181629cbaSAlex Deucher /** Opcode to destroy previously created residency list */ 19281629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_DESTROY 1 19381629cbaSAlex Deucher /** Opcode to update resource information in the list */ 19481629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_UPDATE 2 19581629cbaSAlex Deucher 19681629cbaSAlex Deucher struct drm_amdgpu_bo_list_in { 19781629cbaSAlex Deucher /** Type of operation */ 1982ce9dde0SMikko Rapeli __u32 operation; 19981629cbaSAlex Deucher /** Handle of list or 0 if we want to create one */ 2002ce9dde0SMikko Rapeli __u32 list_handle; 20181629cbaSAlex Deucher /** Number of BOs in list */ 2022ce9dde0SMikko Rapeli __u32 bo_number; 20381629cbaSAlex Deucher /** Size of each element describing BO */ 2042ce9dde0SMikko Rapeli __u32 bo_info_size; 20581629cbaSAlex Deucher /** Pointer to array describing BOs */ 2062ce9dde0SMikko Rapeli __u64 bo_info_ptr; 20781629cbaSAlex Deucher }; 20881629cbaSAlex Deucher 20981629cbaSAlex Deucher struct drm_amdgpu_bo_list_entry { 21081629cbaSAlex Deucher /** Handle of BO */ 2112ce9dde0SMikko Rapeli __u32 bo_handle; 21281629cbaSAlex Deucher /** New (if specified) BO priority to be used during migration */ 2132ce9dde0SMikko Rapeli __u32 bo_priority; 21481629cbaSAlex Deucher }; 21581629cbaSAlex Deucher 21681629cbaSAlex Deucher struct drm_amdgpu_bo_list_out { 21781629cbaSAlex Deucher /** Handle of resource list */ 2182ce9dde0SMikko Rapeli __u32 list_handle; 2192ce9dde0SMikko Rapeli __u32 _pad; 22081629cbaSAlex Deucher }; 22181629cbaSAlex Deucher 22281629cbaSAlex Deucher union drm_amdgpu_bo_list { 22381629cbaSAlex Deucher struct drm_amdgpu_bo_list_in in; 22481629cbaSAlex Deucher struct drm_amdgpu_bo_list_out out; 22581629cbaSAlex Deucher }; 22681629cbaSAlex Deucher 22781629cbaSAlex Deucher /* context related */ 22881629cbaSAlex Deucher #define AMDGPU_CTX_OP_ALLOC_CTX 1 22981629cbaSAlex Deucher #define AMDGPU_CTX_OP_FREE_CTX 2 23081629cbaSAlex Deucher #define AMDGPU_CTX_OP_QUERY_STATE 3 231bc1b1bf6SMonk Liu #define AMDGPU_CTX_OP_QUERY_STATE2 4 2328cda7a4fSAlex Deucher #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 2338cda7a4fSAlex Deucher #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 23481629cbaSAlex Deucher 235d94aed5aSMarek Olšák /* GPU reset status */ 236d94aed5aSMarek Olšák #define AMDGPU_CTX_NO_RESET 0 237675da0ddSChristian König /* this the context caused it */ 238675da0ddSChristian König #define AMDGPU_CTX_GUILTY_RESET 1 239675da0ddSChristian König /* some other context caused it */ 240675da0ddSChristian König #define AMDGPU_CTX_INNOCENT_RESET 2 241675da0ddSChristian König /* unknown cause */ 242675da0ddSChristian König #define AMDGPU_CTX_UNKNOWN_RESET 3 243d94aed5aSMarek Olšák 244bc1b1bf6SMonk Liu /* indicate gpu reset occured after ctx created */ 245bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 246bc1b1bf6SMonk Liu /* indicate vram lost occured after ctx created */ 247bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 248bc1b1bf6SMonk Liu /* indicate some job from this context once cause gpu hang */ 249bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 250ae363a21Sxinhui pan /* indicate some errors are detected by RAS */ 251ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 252ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 253489763afSPierre-Eric Pelloux-Prayer /* indicate that the reset hasn't completed yet */ 254489763afSPierre-Eric Pelloux-Prayer #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 255bc1b1bf6SMonk Liu 256c2636dc5SAndres Rodriguez /* Context priority level */ 257f3d19bf8SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_UNSET -2048 2588bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 2598bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_LOW -512 260c2636dc5SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_NORMAL 0 261cf034477SEmil Velikov /* 262cf034477SEmil Velikov * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 263cf034477SEmil Velikov * CAP_SYS_NICE or DRM_MASTER 264cf034477SEmil Velikov */ 2658bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_HIGH 512 2668bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 267c2636dc5SAndres Rodriguez 2688cda7a4fSAlex Deucher /* select a stable profiling pstate for perfmon tools */ 2698cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 2708cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 2718cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 2728cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 2738cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 2748cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 2758cda7a4fSAlex Deucher 27681629cbaSAlex Deucher struct drm_amdgpu_ctx_in { 277675da0ddSChristian König /** AMDGPU_CTX_OP_* */ 2782ce9dde0SMikko Rapeli __u32 op; 2798cda7a4fSAlex Deucher /** Flags */ 2802ce9dde0SMikko Rapeli __u32 flags; 2812ce9dde0SMikko Rapeli __u32 ctx_id; 282cf034477SEmil Velikov /** AMDGPU_CTX_PRIORITY_* */ 283c2636dc5SAndres Rodriguez __s32 priority; 28481629cbaSAlex Deucher }; 28581629cbaSAlex Deucher 28681629cbaSAlex Deucher union drm_amdgpu_ctx_out { 28781629cbaSAlex Deucher struct { 2882ce9dde0SMikko Rapeli __u32 ctx_id; 2892ce9dde0SMikko Rapeli __u32 _pad; 29081629cbaSAlex Deucher } alloc; 29181629cbaSAlex Deucher 29281629cbaSAlex Deucher struct { 293675da0ddSChristian König /** For future use, no flags defined so far */ 2942ce9dde0SMikko Rapeli __u64 flags; 295d94aed5aSMarek Olšák /** Number of resets caused by this context so far. */ 2962ce9dde0SMikko Rapeli __u32 hangs; 297d94aed5aSMarek Olšák /** Reset status since the last call of the ioctl. */ 2982ce9dde0SMikko Rapeli __u32 reset_status; 29981629cbaSAlex Deucher } state; 3008cda7a4fSAlex Deucher 3018cda7a4fSAlex Deucher struct { 3028cda7a4fSAlex Deucher __u32 flags; 3038cda7a4fSAlex Deucher __u32 _pad; 3048cda7a4fSAlex Deucher } pstate; 30581629cbaSAlex Deucher }; 30681629cbaSAlex Deucher 30781629cbaSAlex Deucher union drm_amdgpu_ctx { 30881629cbaSAlex Deucher struct drm_amdgpu_ctx_in in; 30981629cbaSAlex Deucher union drm_amdgpu_ctx_out out; 31081629cbaSAlex Deucher }; 31181629cbaSAlex Deucher 312cfbcacf4SChunming Zhou /* vm ioctl */ 313cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_RESERVE_VMID 1 314cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_UNRESERVE_VMID 2 315cfbcacf4SChunming Zhou 316cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in { 317cfbcacf4SChunming Zhou /** AMDGPU_VM_OP_* */ 318cfbcacf4SChunming Zhou __u32 op; 319cfbcacf4SChunming Zhou __u32 flags; 320cfbcacf4SChunming Zhou }; 321cfbcacf4SChunming Zhou 322cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out { 323cfbcacf4SChunming Zhou /** For future use, no flags defined so far */ 324cfbcacf4SChunming Zhou __u64 flags; 325cfbcacf4SChunming Zhou }; 326cfbcacf4SChunming Zhou 327cfbcacf4SChunming Zhou union drm_amdgpu_vm { 328cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in in; 329cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out out; 330cfbcacf4SChunming Zhou }; 331cfbcacf4SChunming Zhou 33252c6a62cSAndres Rodriguez /* sched ioctl */ 33352c6a62cSAndres Rodriguez #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 334b5bb37edSBas Nieuwenhuizen #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 33552c6a62cSAndres Rodriguez 33652c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in { 33752c6a62cSAndres Rodriguez /* AMDGPU_SCHED_OP_* */ 33852c6a62cSAndres Rodriguez __u32 op; 33952c6a62cSAndres Rodriguez __u32 fd; 340cf034477SEmil Velikov /** AMDGPU_CTX_PRIORITY_* */ 34152c6a62cSAndres Rodriguez __s32 priority; 342b5bb37edSBas Nieuwenhuizen __u32 ctx_id; 34352c6a62cSAndres Rodriguez }; 34452c6a62cSAndres Rodriguez 34552c6a62cSAndres Rodriguez union drm_amdgpu_sched { 34652c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in in; 34752c6a62cSAndres Rodriguez }; 34852c6a62cSAndres Rodriguez 34981629cbaSAlex Deucher /* 35081629cbaSAlex Deucher * This is not a reliable API and you should expect it to fail for any 35181629cbaSAlex Deucher * number of reasons and have fallback path that do not use userptr to 35281629cbaSAlex Deucher * perform any operation. 35381629cbaSAlex Deucher */ 35481629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 35581629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 35681629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 35781629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 35881629cbaSAlex Deucher 35981629cbaSAlex Deucher struct drm_amdgpu_gem_userptr { 3602ce9dde0SMikko Rapeli __u64 addr; 3612ce9dde0SMikko Rapeli __u64 size; 362675da0ddSChristian König /* AMDGPU_GEM_USERPTR_* */ 3632ce9dde0SMikko Rapeli __u32 flags; 364675da0ddSChristian König /* Resulting GEM handle */ 3652ce9dde0SMikko Rapeli __u32 handle; 36681629cbaSAlex Deucher }; 36781629cbaSAlex Deucher 36800ac6f6bSAlex Deucher /* SI-CI-VI: */ 369fbd76d59SMarek Olšák /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 370fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 371fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 372fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 373fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 374fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 375fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 376fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 377fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 378fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 379fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 380fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 381fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 382fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 383fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 384fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 385fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 386fbd76d59SMarek Olšák 38700ac6f6bSAlex Deucher /* GFX9 and later: */ 38800ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 38900ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 390ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 391ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 392ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 393ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 394ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 395ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 396c5705372SMarek Olšák #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 397c5705372SMarek Olšák #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 398c5705372SMarek Olšák #define AMDGPU_TILING_SCANOUT_SHIFT 63 399c5705372SMarek Olšák #define AMDGPU_TILING_SCANOUT_MASK 0x1 40000ac6f6bSAlex Deucher 40100ac6f6bSAlex Deucher /* Set/Get helpers for tiling flags. */ 402fbd76d59SMarek Olšák #define AMDGPU_TILING_SET(field, value) \ 40300ac6f6bSAlex Deucher (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 404fbd76d59SMarek Olšák #define AMDGPU_TILING_GET(value, field) \ 40500ac6f6bSAlex Deucher (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 40681629cbaSAlex Deucher 40781629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 40881629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 40981629cbaSAlex Deucher 41081629cbaSAlex Deucher /** The same structure is shared for input/output */ 41181629cbaSAlex Deucher struct drm_amdgpu_gem_metadata { 412675da0ddSChristian König /** GEM Object handle */ 4132ce9dde0SMikko Rapeli __u32 handle; 414675da0ddSChristian König /** Do we want get or set metadata */ 4152ce9dde0SMikko Rapeli __u32 op; 41681629cbaSAlex Deucher struct { 417675da0ddSChristian König /** For future use, no flags defined so far */ 4182ce9dde0SMikko Rapeli __u64 flags; 419675da0ddSChristian König /** family specific tiling info */ 4202ce9dde0SMikko Rapeli __u64 tiling_info; 4212ce9dde0SMikko Rapeli __u32 data_size_bytes; 4222ce9dde0SMikko Rapeli __u32 data[64]; 42381629cbaSAlex Deucher } data; 42481629cbaSAlex Deucher }; 42581629cbaSAlex Deucher 42681629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in { 427675da0ddSChristian König /** the GEM object handle */ 4282ce9dde0SMikko Rapeli __u32 handle; 4292ce9dde0SMikko Rapeli __u32 _pad; 43081629cbaSAlex Deucher }; 43181629cbaSAlex Deucher 43281629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out { 433675da0ddSChristian König /** mmap offset from the vma offset manager */ 4342ce9dde0SMikko Rapeli __u64 addr_ptr; 43581629cbaSAlex Deucher }; 43681629cbaSAlex Deucher 43781629cbaSAlex Deucher union drm_amdgpu_gem_mmap { 43881629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in in; 43981629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out out; 44081629cbaSAlex Deucher }; 44181629cbaSAlex Deucher 44281629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in { 443675da0ddSChristian König /** GEM object handle */ 4442ce9dde0SMikko Rapeli __u32 handle; 445675da0ddSChristian König /** For future use, no flags defined so far */ 4462ce9dde0SMikko Rapeli __u32 flags; 447675da0ddSChristian König /** Absolute timeout to wait */ 4482ce9dde0SMikko Rapeli __u64 timeout; 44981629cbaSAlex Deucher }; 45081629cbaSAlex Deucher 45181629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out { 452675da0ddSChristian König /** BO status: 0 - BO is idle, 1 - BO is busy */ 4532ce9dde0SMikko Rapeli __u32 status; 454675da0ddSChristian König /** Returned current memory domain */ 4552ce9dde0SMikko Rapeli __u32 domain; 45681629cbaSAlex Deucher }; 45781629cbaSAlex Deucher 45881629cbaSAlex Deucher union drm_amdgpu_gem_wait_idle { 45981629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in in; 46081629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out out; 46181629cbaSAlex Deucher }; 46281629cbaSAlex Deucher 46381629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in { 464d7b1eeb2SMonk Liu /* Command submission handle 465d7b1eeb2SMonk Liu * handle equals 0 means none to wait for 466080b24ebSAlex Deucher * handle equals ~0ull means wait for the latest sequence number 467d7b1eeb2SMonk Liu */ 4682ce9dde0SMikko Rapeli __u64 handle; 469675da0ddSChristian König /** Absolute timeout to wait */ 4702ce9dde0SMikko Rapeli __u64 timeout; 4712ce9dde0SMikko Rapeli __u32 ip_type; 4722ce9dde0SMikko Rapeli __u32 ip_instance; 4732ce9dde0SMikko Rapeli __u32 ring; 4742ce9dde0SMikko Rapeli __u32 ctx_id; 47581629cbaSAlex Deucher }; 47681629cbaSAlex Deucher 47781629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out { 478675da0ddSChristian König /** CS status: 0 - CS completed, 1 - CS still busy */ 4792ce9dde0SMikko Rapeli __u64 status; 48081629cbaSAlex Deucher }; 48181629cbaSAlex Deucher 48281629cbaSAlex Deucher union drm_amdgpu_wait_cs { 48381629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in in; 48481629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out out; 48581629cbaSAlex Deucher }; 48681629cbaSAlex Deucher 487eef18a82SJunwei Zhang struct drm_amdgpu_fence { 488eef18a82SJunwei Zhang __u32 ctx_id; 489eef18a82SJunwei Zhang __u32 ip_type; 490eef18a82SJunwei Zhang __u32 ip_instance; 491eef18a82SJunwei Zhang __u32 ring; 492eef18a82SJunwei Zhang __u64 seq_no; 493eef18a82SJunwei Zhang }; 494eef18a82SJunwei Zhang 495eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in { 496eef18a82SJunwei Zhang /** This points to uint64_t * which points to fences */ 497eef18a82SJunwei Zhang __u64 fences; 498eef18a82SJunwei Zhang __u32 fence_count; 499eef18a82SJunwei Zhang __u32 wait_all; 500eef18a82SJunwei Zhang __u64 timeout_ns; 501eef18a82SJunwei Zhang }; 502eef18a82SJunwei Zhang 503eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out { 504eef18a82SJunwei Zhang __u32 status; 505eef18a82SJunwei Zhang __u32 first_signaled; 506eef18a82SJunwei Zhang }; 507eef18a82SJunwei Zhang 508eef18a82SJunwei Zhang union drm_amdgpu_wait_fences { 509eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in in; 510eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out out; 511eef18a82SJunwei Zhang }; 512eef18a82SJunwei Zhang 51381629cbaSAlex Deucher #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 514d8f65a23SMarek Olšák #define AMDGPU_GEM_OP_SET_PLACEMENT 1 51581629cbaSAlex Deucher 516675da0ddSChristian König /* Sets or returns a value associated with a buffer. */ 517675da0ddSChristian König struct drm_amdgpu_gem_op { 518675da0ddSChristian König /** GEM object handle */ 5192ce9dde0SMikko Rapeli __u32 handle; 520675da0ddSChristian König /** AMDGPU_GEM_OP_* */ 5212ce9dde0SMikko Rapeli __u32 op; 522675da0ddSChristian König /** Input or return value */ 5232ce9dde0SMikko Rapeli __u64 value; 524675da0ddSChristian König }; 525675da0ddSChristian König 52681629cbaSAlex Deucher #define AMDGPU_VA_OP_MAP 1 52781629cbaSAlex Deucher #define AMDGPU_VA_OP_UNMAP 2 528dc54d3d1SChristian König #define AMDGPU_VA_OP_CLEAR 3 52980f95c57SChristian König #define AMDGPU_VA_OP_REPLACE 4 53081629cbaSAlex Deucher 531fc220f65SChristian König /* Delay the page table update till the next CS */ 532fc220f65SChristian König #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 533fc220f65SChristian König 53481629cbaSAlex Deucher /* Mapping flags */ 53581629cbaSAlex Deucher /* readable mapping */ 53681629cbaSAlex Deucher #define AMDGPU_VM_PAGE_READABLE (1 << 1) 53781629cbaSAlex Deucher /* writable mapping */ 53881629cbaSAlex Deucher #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 53981629cbaSAlex Deucher /* executable mapping, new for VI */ 54081629cbaSAlex Deucher #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 541b85891bdSJunwei Zhang /* partially resident texture */ 542b85891bdSJunwei Zhang #define AMDGPU_VM_PAGE_PRT (1 << 4) 54366e02bc3SAlex Xie /* MTYPE flags use bit 5 to 8 */ 54466e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 54566e02bc3SAlex Xie /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 54666e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 547130c8893SYong Zhao /* Use Non Coherent MTYPE instead of default MTYPE */ 54866e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_NC (1 << 5) 549130c8893SYong Zhao /* Use Write Combine MTYPE instead of default MTYPE */ 55066e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_WC (2 << 5) 551130c8893SYong Zhao /* Use Cache Coherent MTYPE instead of default MTYPE */ 55266e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_CC (3 << 5) 553130c8893SYong Zhao /* Use UnCached MTYPE instead of default MTYPE */ 55466e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_UC (4 << 5) 555130c8893SYong Zhao /* Use Read Write MTYPE instead of default MTYPE */ 556484deaedSOak Zeng #define AMDGPU_VM_MTYPE_RW (5 << 5) 557b6c65a2cSChristian König /* don't allocate MALL */ 558b6c65a2cSChristian König #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 55981629cbaSAlex Deucher 56034b5f6a6SChristian König struct drm_amdgpu_gem_va { 561675da0ddSChristian König /** GEM object handle */ 5622ce9dde0SMikko Rapeli __u32 handle; 5632ce9dde0SMikko Rapeli __u32 _pad; 564675da0ddSChristian König /** AMDGPU_VA_OP_* */ 5652ce9dde0SMikko Rapeli __u32 operation; 566675da0ddSChristian König /** AMDGPU_VM_PAGE_* */ 5672ce9dde0SMikko Rapeli __u32 flags; 568675da0ddSChristian König /** va address to assign . Must be correctly aligned.*/ 5692ce9dde0SMikko Rapeli __u64 va_address; 570675da0ddSChristian König /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 5712ce9dde0SMikko Rapeli __u64 offset_in_bo; 572675da0ddSChristian König /** Specify mapping size. Must be correctly aligned. */ 5732ce9dde0SMikko Rapeli __u64 map_size; 57481629cbaSAlex Deucher }; 57581629cbaSAlex Deucher 57681629cbaSAlex Deucher #define AMDGPU_HW_IP_GFX 0 57781629cbaSAlex Deucher #define AMDGPU_HW_IP_COMPUTE 1 57881629cbaSAlex Deucher #define AMDGPU_HW_IP_DMA 2 57981629cbaSAlex Deucher #define AMDGPU_HW_IP_UVD 3 58081629cbaSAlex Deucher #define AMDGPU_HW_IP_VCE 4 581a50798b6SLeo Liu #define AMDGPU_HW_IP_UVD_ENC 5 58266e236f1SLeo Liu #define AMDGPU_HW_IP_VCN_DEC 6 5834528c186SRuijing Dong /* 5844528c186SRuijing Dong * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 5854528c186SRuijing Dong * both encoding and decoding jobs. 5864528c186SRuijing Dong */ 587fcfc5a90SLeo Liu #define AMDGPU_HW_IP_VCN_ENC 7 58881d35014SBoyuan Zhang #define AMDGPU_HW_IP_VCN_JPEG 8 58981d35014SBoyuan Zhang #define AMDGPU_HW_IP_NUM 9 59081629cbaSAlex Deucher 59181629cbaSAlex Deucher #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 59281629cbaSAlex Deucher 59381629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_IB 0x01 59481629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_FENCE 0x02 5952b48d323SChristian König #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 596660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 597660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 598964d0fbfSAndrey Grodzovsky #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 59967dd1a36SAndrey Grodzovsky #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 6002624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 6012624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 602043dc33fSAlex Deucher #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 603675da0ddSChristian König 60481629cbaSAlex Deucher struct drm_amdgpu_cs_chunk { 6052ce9dde0SMikko Rapeli __u32 chunk_id; 6062ce9dde0SMikko Rapeli __u32 length_dw; 6072ce9dde0SMikko Rapeli __u64 chunk_data; 60881629cbaSAlex Deucher }; 60981629cbaSAlex Deucher 61081629cbaSAlex Deucher struct drm_amdgpu_cs_in { 61181629cbaSAlex Deucher /** Rendering context id */ 6122ce9dde0SMikko Rapeli __u32 ctx_id; 61381629cbaSAlex Deucher /** Handle of resource list associated with CS */ 6142ce9dde0SMikko Rapeli __u32 bo_list_handle; 6152ce9dde0SMikko Rapeli __u32 num_chunks; 616e90c2b21SLuben Tuikov __u32 flags; 6172ce9dde0SMikko Rapeli /** this points to __u64 * which point to cs chunks */ 6182ce9dde0SMikko Rapeli __u64 chunks; 61981629cbaSAlex Deucher }; 62081629cbaSAlex Deucher 62181629cbaSAlex Deucher struct drm_amdgpu_cs_out { 6222ce9dde0SMikko Rapeli __u64 handle; 62381629cbaSAlex Deucher }; 62481629cbaSAlex Deucher 62581629cbaSAlex Deucher union drm_amdgpu_cs { 62681629cbaSAlex Deucher struct drm_amdgpu_cs_in in; 62781629cbaSAlex Deucher struct drm_amdgpu_cs_out out; 62881629cbaSAlex Deucher }; 62981629cbaSAlex Deucher 63081629cbaSAlex Deucher /* Specify flags to be used for IB */ 63181629cbaSAlex Deucher 63281629cbaSAlex Deucher /* This IB should be submitted to CE */ 63381629cbaSAlex Deucher #define AMDGPU_IB_FLAG_CE (1<<0) 63481629cbaSAlex Deucher 635ed834af2SMonk Liu /* Preamble flag, which means the IB could be dropped if no context switch */ 636cab6d57cSJammy Zhou #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 637aa2bdb24SJammy Zhou 63871aec257SMonk Liu /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 63971aec257SMonk Liu #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 64071aec257SMonk Liu 641d240cd9eSMarek Olšák /* The IB fence should do the L2 writeback but not invalidate any shader 642d240cd9eSMarek Olšák * caches (L2/vL1/sL1/I$). */ 643d240cd9eSMarek Olšák #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 644d240cd9eSMarek Olšák 64541cca166SMarek Olšák /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 64641cca166SMarek Olšák * This will reset wave ID counters for the IB. 64741cca166SMarek Olšák */ 64841cca166SMarek Olšák #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 64941cca166SMarek Olšák 6500bb5d5b0SLuben Tuikov /* Flag the IB as secure (TMZ) 6510bb5d5b0SLuben Tuikov */ 6520bb5d5b0SLuben Tuikov #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 6530bb5d5b0SLuben Tuikov 65443c8546bSAndrey Grodzovsky /* Tell KMD to flush and invalidate caches 65543c8546bSAndrey Grodzovsky */ 65643c8546bSAndrey Grodzovsky #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 65743c8546bSAndrey Grodzovsky 65881629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib { 6592ce9dde0SMikko Rapeli __u32 _pad; 660675da0ddSChristian König /** AMDGPU_IB_FLAG_* */ 6612ce9dde0SMikko Rapeli __u32 flags; 662675da0ddSChristian König /** Virtual address to begin IB execution */ 6632ce9dde0SMikko Rapeli __u64 va_start; 664675da0ddSChristian König /** Size of submission */ 6652ce9dde0SMikko Rapeli __u32 ib_bytes; 666675da0ddSChristian König /** HW IP to submit to */ 6672ce9dde0SMikko Rapeli __u32 ip_type; 668675da0ddSChristian König /** HW IP index of the same type to submit to */ 6692ce9dde0SMikko Rapeli __u32 ip_instance; 670675da0ddSChristian König /** Ring index to submit to */ 6712ce9dde0SMikko Rapeli __u32 ring; 67281629cbaSAlex Deucher }; 67381629cbaSAlex Deucher 6742b48d323SChristian König struct drm_amdgpu_cs_chunk_dep { 6752ce9dde0SMikko Rapeli __u32 ip_type; 6762ce9dde0SMikko Rapeli __u32 ip_instance; 6772ce9dde0SMikko Rapeli __u32 ring; 6782ce9dde0SMikko Rapeli __u32 ctx_id; 6792ce9dde0SMikko Rapeli __u64 handle; 6802b48d323SChristian König }; 6812b48d323SChristian König 68281629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence { 6832ce9dde0SMikko Rapeli __u32 handle; 6842ce9dde0SMikko Rapeli __u32 offset; 68581629cbaSAlex Deucher }; 68681629cbaSAlex Deucher 687660e8558SDave Airlie struct drm_amdgpu_cs_chunk_sem { 688660e8558SDave Airlie __u32 handle; 689660e8558SDave Airlie }; 690660e8558SDave Airlie 6912624dd15SChunming Zhou struct drm_amdgpu_cs_chunk_syncobj { 6922624dd15SChunming Zhou __u32 handle; 6932624dd15SChunming Zhou __u32 flags; 6942624dd15SChunming Zhou __u64 point; 6952624dd15SChunming Zhou }; 6962624dd15SChunming Zhou 6977ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 6987ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 6997ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 7007ca24cf2SMarek Olšák 7017ca24cf2SMarek Olšák union drm_amdgpu_fence_to_handle { 7027ca24cf2SMarek Olšák struct { 7037ca24cf2SMarek Olšák struct drm_amdgpu_fence fence; 7047ca24cf2SMarek Olšák __u32 what; 70556e0349fSDave Airlie __u32 pad; 7067ca24cf2SMarek Olšák } in; 7077ca24cf2SMarek Olšák struct { 7087ca24cf2SMarek Olšák __u32 handle; 7097ca24cf2SMarek Olšák } out; 7107ca24cf2SMarek Olšák }; 7117ca24cf2SMarek Olšák 71281629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_data { 71381629cbaSAlex Deucher union { 71481629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib ib_data; 71581629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence fence_data; 71681629cbaSAlex Deucher }; 71781629cbaSAlex Deucher }; 71881629cbaSAlex Deucher 719043dc33fSAlex Deucher #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 720043dc33fSAlex Deucher 721043dc33fSAlex Deucher struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 722043dc33fSAlex Deucher __u64 shadow_va; 723043dc33fSAlex Deucher __u64 csa_va; 724043dc33fSAlex Deucher __u64 gds_va; 725043dc33fSAlex Deucher __u64 flags; 726043dc33fSAlex Deucher }; 727043dc33fSAlex Deucher 728c45dd3bdSMauro Carvalho Chehab /* 72981629cbaSAlex Deucher * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 73081629cbaSAlex Deucher * 73181629cbaSAlex Deucher */ 73281629cbaSAlex Deucher #define AMDGPU_IDS_FLAGS_FUSION 0x1 733aafcafa0SMonk Liu #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 73416c642ecSPierre-Eric Pelloux-Prayer #define AMDGPU_IDS_FLAGS_TMZ 0x4 735b299221fSMarek Olšák #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 73681629cbaSAlex Deucher 73781629cbaSAlex Deucher /* indicate if acceleration can be working */ 73881629cbaSAlex Deucher #define AMDGPU_INFO_ACCEL_WORKING 0x00 73981629cbaSAlex Deucher /* get the crtc_id from the mode object id? */ 74081629cbaSAlex Deucher #define AMDGPU_INFO_CRTC_FROM_ID 0x01 74181629cbaSAlex Deucher /* query hw IP info */ 74281629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_INFO 0x02 74381629cbaSAlex Deucher /* query hw IP instance count for the specified type */ 74481629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_COUNT 0x03 74581629cbaSAlex Deucher /* timestamp for GL_ARB_timer_query */ 74681629cbaSAlex Deucher #define AMDGPU_INFO_TIMESTAMP 0x05 74781629cbaSAlex Deucher /* Query the firmware version */ 74881629cbaSAlex Deucher #define AMDGPU_INFO_FW_VERSION 0x0e 74981629cbaSAlex Deucher /* Subquery id: Query VCE firmware version */ 75081629cbaSAlex Deucher #define AMDGPU_INFO_FW_VCE 0x1 75181629cbaSAlex Deucher /* Subquery id: Query UVD firmware version */ 75281629cbaSAlex Deucher #define AMDGPU_INFO_FW_UVD 0x2 75381629cbaSAlex Deucher /* Subquery id: Query GMC firmware version */ 75481629cbaSAlex Deucher #define AMDGPU_INFO_FW_GMC 0x03 75581629cbaSAlex Deucher /* Subquery id: Query GFX ME firmware version */ 75681629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_ME 0x04 75781629cbaSAlex Deucher /* Subquery id: Query GFX PFP firmware version */ 75881629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_PFP 0x05 75981629cbaSAlex Deucher /* Subquery id: Query GFX CE firmware version */ 76081629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_CE 0x06 76181629cbaSAlex Deucher /* Subquery id: Query GFX RLC firmware version */ 76281629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_RLC 0x07 76381629cbaSAlex Deucher /* Subquery id: Query GFX MEC firmware version */ 76481629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_MEC 0x08 76581629cbaSAlex Deucher /* Subquery id: Query SMC firmware version */ 76681629cbaSAlex Deucher #define AMDGPU_INFO_FW_SMC 0x0a 76781629cbaSAlex Deucher /* Subquery id: Query SDMA firmware version */ 76881629cbaSAlex Deucher #define AMDGPU_INFO_FW_SDMA 0x0b 7696a7ed07eSHuang Rui /* Subquery id: Query PSP SOS firmware version */ 7706a7ed07eSHuang Rui #define AMDGPU_INFO_FW_SOS 0x0c 7716a7ed07eSHuang Rui /* Subquery id: Query PSP ASD firmware version */ 7726a7ed07eSHuang Rui #define AMDGPU_INFO_FW_ASD 0x0d 7733ac952b1SAlex Deucher /* Subquery id: Query VCN firmware version */ 7743ac952b1SAlex Deucher #define AMDGPU_INFO_FW_VCN 0x0e 775621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLC firmware version */ 776621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 777621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLG firmware version */ 778621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 779621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLS firmware version */ 780621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 7814d11b4b2SDavid Francis /* Subquery id: Query DMCU firmware version */ 7824d11b4b2SDavid Francis #define AMDGPU_INFO_FW_DMCU 0x12 7839b9ca62dSxinhui pan #define AMDGPU_INFO_FW_TA 0x13 784976e51a7SNicholas Kazlauskas /* Subquery id: Query DMCUB firmware version */ 785976e51a7SNicholas Kazlauskas #define AMDGPU_INFO_FW_DMCUB 0x14 7866fbcb00cSHuang Rui /* Subquery id: Query TOC firmware version */ 7876fbcb00cSHuang Rui #define AMDGPU_INFO_FW_TOC 0x15 788c4381d0eSBokun Zhang /* Subquery id: Query CAP firmware version */ 789c4381d0eSBokun Zhang #define AMDGPU_INFO_FW_CAP 0x16 7902f9d510fSHawking Zhang /* Subquery id: Query GFX RLCP firmware version */ 7912f9d510fSHawking Zhang #define AMDGPU_INFO_FW_GFX_RLCP 0x17 7922f9d510fSHawking Zhang /* Subquery id: Query GFX RLCV firmware version */ 7932f9d510fSHawking Zhang #define AMDGPU_INFO_FW_GFX_RLCV 0x18 79410faf078SYifan Zhang /* Subquery id: Query MES_KIQ firmware version */ 79510faf078SYifan Zhang #define AMDGPU_INFO_FW_MES_KIQ 0x19 79610faf078SYifan Zhang /* Subquery id: Query MES firmware version */ 79710faf078SYifan Zhang #define AMDGPU_INFO_FW_MES 0x1a 798b7236296SDavid Francis /* Subquery id: Query IMU firmware version */ 799b7236296SDavid Francis #define AMDGPU_INFO_FW_IMU 0x1b 800976e51a7SNicholas Kazlauskas 80181629cbaSAlex Deucher /* number of bytes moved for TTM migration */ 80281629cbaSAlex Deucher #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 80381629cbaSAlex Deucher /* the used VRAM size */ 80481629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_USAGE 0x10 80581629cbaSAlex Deucher /* the used GTT size */ 80681629cbaSAlex Deucher #define AMDGPU_INFO_GTT_USAGE 0x11 80781629cbaSAlex Deucher /* Information about GDS, etc. resource configuration */ 80881629cbaSAlex Deucher #define AMDGPU_INFO_GDS_CONFIG 0x13 80981629cbaSAlex Deucher /* Query information about VRAM and GTT domains */ 81081629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_GTT 0x14 81181629cbaSAlex Deucher /* Query information about register in MMR address space*/ 81281629cbaSAlex Deucher #define AMDGPU_INFO_READ_MMR_REG 0x15 81381629cbaSAlex Deucher /* Query information about device: rev id, family, etc. */ 81481629cbaSAlex Deucher #define AMDGPU_INFO_DEV_INFO 0x16 81581629cbaSAlex Deucher /* visible vram usage */ 81681629cbaSAlex Deucher #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 81783a59b63SMarek Olšák /* number of TTM buffer evictions */ 81883a59b63SMarek Olšák #define AMDGPU_INFO_NUM_EVICTIONS 0x18 819e0adf6c8SJunwei Zhang /* Query memory about VRAM and GTT domains */ 820e0adf6c8SJunwei Zhang #define AMDGPU_INFO_MEMORY 0x19 821bbe87974SAlex Deucher /* Query vce clock table */ 822bbe87974SAlex Deucher #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 82340ee5888SEvan Quan /* Query vbios related information */ 82440ee5888SEvan Quan #define AMDGPU_INFO_VBIOS 0x1B 82540ee5888SEvan Quan /* Subquery id: Query vbios size */ 82640ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_SIZE 0x1 82740ee5888SEvan Quan /* Subquery id: Query vbios image */ 82840ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_IMAGE 0x2 82929b4c589SJiawei Gu /* Subquery id: Query vbios info */ 83029b4c589SJiawei Gu #define AMDGPU_INFO_VBIOS_INFO 0x3 83144879b62SArindam Nath /* Query UVD handles */ 83244879b62SArindam Nath #define AMDGPU_INFO_NUM_HANDLES 0x1C 8335ebbac4bSAlex Deucher /* Query sensor related information */ 8345ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR 0x1D 8355ebbac4bSAlex Deucher /* Subquery id: Query GPU shader clock */ 8365ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 8375ebbac4bSAlex Deucher /* Subquery id: Query GPU memory clock */ 8385ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 8395ebbac4bSAlex Deucher /* Subquery id: Query GPU temperature */ 8405ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 8415ebbac4bSAlex Deucher /* Subquery id: Query GPU load */ 8425ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 8435ebbac4bSAlex Deucher /* Subquery id: Query average GPU power */ 8445ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 8455ebbac4bSAlex Deucher /* Subquery id: Query northbridge voltage */ 8465ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDNB 0x6 8475ebbac4bSAlex Deucher /* Subquery id: Query graphics voltage */ 8485ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 84960bbade2SRex Zhu /* Subquery id: Query GPU stable pstate shader clock */ 85060bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 85160bbade2SRex Zhu /* Subquery id: Query GPU stable pstate memory clock */ 85260bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 8535cfd9784SEvan Quan /* Subquery id: Query GPU peak pstate shader clock */ 8545cfd9784SEvan Quan #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 8555cfd9784SEvan Quan /* Subquery id: Query GPU peak pstate memory clock */ 8565cfd9784SEvan Quan #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 85768e2c5ffSMarek Olšák /* Number of VRAM page faults on CPU access. */ 85868e2c5ffSMarek Olšák #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 8591f7251b7SChristian König #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 8605cb77114Sxinhui pan /* query ras mask of enabled features*/ 8615cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 8625cb77114Sxinhui pan /* RAS MASK: UMC (VRAM) */ 8635cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 8645cb77114Sxinhui pan /* RAS MASK: SDMA */ 8655cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 8665cb77114Sxinhui pan /* RAS MASK: GFX */ 8675cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 8685cb77114Sxinhui pan /* RAS MASK: MMHUB */ 8695cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 8705cb77114Sxinhui pan /* RAS MASK: ATHUB */ 8715cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 8725cb77114Sxinhui pan /* RAS MASK: PCIE */ 8735cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 8745cb77114Sxinhui pan /* RAS MASK: HDP */ 8755cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 8765cb77114Sxinhui pan /* RAS MASK: XGMI */ 8775cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 8785cb77114Sxinhui pan /* RAS MASK: DF */ 8795cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 8805cb77114Sxinhui pan /* RAS MASK: SMN */ 8815cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 8825cb77114Sxinhui pan /* RAS MASK: SEM */ 8835cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 8845cb77114Sxinhui pan /* RAS MASK: MP0 */ 8855cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 8865cb77114Sxinhui pan /* RAS MASK: MP1 */ 8875cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 8885cb77114Sxinhui pan /* RAS MASK: FUSE */ 8895cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 89072f4c9d5SAlex Deucher /* query video encode/decode caps */ 89172f4c9d5SAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS 0x21 89272f4c9d5SAlex Deucher /* Subquery id: Decode */ 89372f4c9d5SAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 89472f4c9d5SAlex Deucher /* Subquery id: Encode */ 89572f4c9d5SAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 8964f18b9a6SBas Nieuwenhuizen /* Query the max number of IBs per gang per submission */ 8974f18b9a6SBas Nieuwenhuizen #define AMDGPU_INFO_MAX_IBS 0x22 89881629cbaSAlex Deucher 89981629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 90081629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 90181629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 90281629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 90381629cbaSAlex Deucher 904000cab9aSHuang Rui struct drm_amdgpu_query_fw { 905000cab9aSHuang Rui /** AMDGPU_INFO_FW_* */ 906000cab9aSHuang Rui __u32 fw_type; 907000cab9aSHuang Rui /** 908000cab9aSHuang Rui * Index of the IP if there are more IPs of 909000cab9aSHuang Rui * the same type. 910000cab9aSHuang Rui */ 911000cab9aSHuang Rui __u32 ip_instance; 912000cab9aSHuang Rui /** 913000cab9aSHuang Rui * Index of the engine. Whether this is used depends 914000cab9aSHuang Rui * on the firmware type. (e.g. MEC, SDMA) 915000cab9aSHuang Rui */ 916000cab9aSHuang Rui __u32 index; 917000cab9aSHuang Rui __u32 _pad; 918000cab9aSHuang Rui }; 919000cab9aSHuang Rui 92081629cbaSAlex Deucher /* Input structure for the INFO ioctl */ 92181629cbaSAlex Deucher struct drm_amdgpu_info { 92281629cbaSAlex Deucher /* Where the return value will be stored */ 9232ce9dde0SMikko Rapeli __u64 return_pointer; 92481629cbaSAlex Deucher /* The size of the return value. Just like "size" in "snprintf", 92581629cbaSAlex Deucher * it limits how many bytes the kernel can write. */ 9262ce9dde0SMikko Rapeli __u32 return_size; 92781629cbaSAlex Deucher /* The query request id. */ 9282ce9dde0SMikko Rapeli __u32 query; 92981629cbaSAlex Deucher 93081629cbaSAlex Deucher union { 93181629cbaSAlex Deucher struct { 9322ce9dde0SMikko Rapeli __u32 id; 9332ce9dde0SMikko Rapeli __u32 _pad; 93481629cbaSAlex Deucher } mode_crtc; 93581629cbaSAlex Deucher 93681629cbaSAlex Deucher struct { 93781629cbaSAlex Deucher /** AMDGPU_HW_IP_* */ 9382ce9dde0SMikko Rapeli __u32 type; 93981629cbaSAlex Deucher /** 940675da0ddSChristian König * Index of the IP if there are more IPs of the same 941675da0ddSChristian König * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 94281629cbaSAlex Deucher */ 9432ce9dde0SMikko Rapeli __u32 ip_instance; 94481629cbaSAlex Deucher } query_hw_ip; 94581629cbaSAlex Deucher 94681629cbaSAlex Deucher struct { 9472ce9dde0SMikko Rapeli __u32 dword_offset; 948675da0ddSChristian König /** number of registers to read */ 9492ce9dde0SMikko Rapeli __u32 count; 9502ce9dde0SMikko Rapeli __u32 instance; 951675da0ddSChristian König /** For future use, no flags defined so far */ 9522ce9dde0SMikko Rapeli __u32 flags; 95381629cbaSAlex Deucher } read_mmr_reg; 95481629cbaSAlex Deucher 955000cab9aSHuang Rui struct drm_amdgpu_query_fw query_fw; 95640ee5888SEvan Quan 95740ee5888SEvan Quan struct { 95840ee5888SEvan Quan __u32 type; 95940ee5888SEvan Quan __u32 offset; 96040ee5888SEvan Quan } vbios_info; 9615ebbac4bSAlex Deucher 9625ebbac4bSAlex Deucher struct { 9635ebbac4bSAlex Deucher __u32 type; 9645ebbac4bSAlex Deucher } sensor_info; 965f35e9bdbSAlex Deucher 966f35e9bdbSAlex Deucher struct { 967f35e9bdbSAlex Deucher __u32 type; 968f35e9bdbSAlex Deucher } video_cap; 96981629cbaSAlex Deucher }; 97081629cbaSAlex Deucher }; 97181629cbaSAlex Deucher 97281629cbaSAlex Deucher struct drm_amdgpu_info_gds { 97381629cbaSAlex Deucher /** GDS GFX partition size */ 9742ce9dde0SMikko Rapeli __u32 gds_gfx_partition_size; 97581629cbaSAlex Deucher /** GDS compute partition size */ 9762ce9dde0SMikko Rapeli __u32 compute_partition_size; 97781629cbaSAlex Deucher /** total GDS memory size */ 9782ce9dde0SMikko Rapeli __u32 gds_total_size; 97981629cbaSAlex Deucher /** GWS size per GFX partition */ 9802ce9dde0SMikko Rapeli __u32 gws_per_gfx_partition; 98181629cbaSAlex Deucher /** GSW size per compute partition */ 9822ce9dde0SMikko Rapeli __u32 gws_per_compute_partition; 98381629cbaSAlex Deucher /** OA size per GFX partition */ 9842ce9dde0SMikko Rapeli __u32 oa_per_gfx_partition; 98581629cbaSAlex Deucher /** OA size per compute partition */ 9862ce9dde0SMikko Rapeli __u32 oa_per_compute_partition; 9872ce9dde0SMikko Rapeli __u32 _pad; 98881629cbaSAlex Deucher }; 98981629cbaSAlex Deucher 99081629cbaSAlex Deucher struct drm_amdgpu_info_vram_gtt { 9912ce9dde0SMikko Rapeli __u64 vram_size; 9922ce9dde0SMikko Rapeli __u64 vram_cpu_accessible_size; 9932ce9dde0SMikko Rapeli __u64 gtt_size; 99481629cbaSAlex Deucher }; 99581629cbaSAlex Deucher 996e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info { 997e0adf6c8SJunwei Zhang /** max. physical memory */ 998e0adf6c8SJunwei Zhang __u64 total_heap_size; 999e0adf6c8SJunwei Zhang 1000e0adf6c8SJunwei Zhang /** Theoretical max. available memory in the given heap */ 1001e0adf6c8SJunwei Zhang __u64 usable_heap_size; 1002e0adf6c8SJunwei Zhang 1003e0adf6c8SJunwei Zhang /** 1004e0adf6c8SJunwei Zhang * Number of bytes allocated in the heap. This includes all processes 1005e0adf6c8SJunwei Zhang * and private allocations in the kernel. It changes when new buffers 1006e0adf6c8SJunwei Zhang * are allocated, freed, and moved. It cannot be larger than 1007e0adf6c8SJunwei Zhang * heap_size. 1008e0adf6c8SJunwei Zhang */ 1009e0adf6c8SJunwei Zhang __u64 heap_usage; 1010e0adf6c8SJunwei Zhang 1011e0adf6c8SJunwei Zhang /** 1012e0adf6c8SJunwei Zhang * Theoretical possible max. size of buffer which 1013e0adf6c8SJunwei Zhang * could be allocated in the given heap 1014e0adf6c8SJunwei Zhang */ 1015e0adf6c8SJunwei Zhang __u64 max_allocation; 10169f6163e7SJunwei Zhang }; 10179f6163e7SJunwei Zhang 1018e0adf6c8SJunwei Zhang struct drm_amdgpu_memory_info { 1019e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info vram; 1020e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info cpu_accessible_vram; 1021e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info gtt; 1022cfa32556SJunwei Zhang }; 1023cfa32556SJunwei Zhang 102481629cbaSAlex Deucher struct drm_amdgpu_info_firmware { 10252ce9dde0SMikko Rapeli __u32 ver; 10262ce9dde0SMikko Rapeli __u32 feature; 102781629cbaSAlex Deucher }; 102881629cbaSAlex Deucher 102929b4c589SJiawei Gu struct drm_amdgpu_info_vbios { 103029b4c589SJiawei Gu __u8 name[64]; 103129b4c589SJiawei Gu __u8 vbios_pn[64]; 103229b4c589SJiawei Gu __u32 version; 103329b4c589SJiawei Gu __u32 pad; 103429b4c589SJiawei Gu __u8 vbios_ver_str[32]; 103529b4c589SJiawei Gu __u8 date[32]; 103629b4c589SJiawei Gu }; 103729b4c589SJiawei Gu 103881c59f54SKen Wang #define AMDGPU_VRAM_TYPE_UNKNOWN 0 103981c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR1 1 104081c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR2 2 104181c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR3 3 104281c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR4 4 104381c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR5 5 104481c59f54SKen Wang #define AMDGPU_VRAM_TYPE_HBM 6 104581c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR3 7 10461e09b053SHawking Zhang #define AMDGPU_VRAM_TYPE_DDR4 8 1047d67383e6SHuang Rui #define AMDGPU_VRAM_TYPE_GDDR6 9 10481e483203SHuang Rui #define AMDGPU_VRAM_TYPE_DDR5 10 1049d534ca71SAlex Deucher #define AMDGPU_VRAM_TYPE_LPDDR4 11 1050d534ca71SAlex Deucher #define AMDGPU_VRAM_TYPE_LPDDR5 12 105181c59f54SKen Wang 105281629cbaSAlex Deucher struct drm_amdgpu_info_device { 105381629cbaSAlex Deucher /** PCI Device ID */ 10542ce9dde0SMikko Rapeli __u32 device_id; 105581629cbaSAlex Deucher /** Internal chip revision: A0, A1, etc.) */ 10562ce9dde0SMikko Rapeli __u32 chip_rev; 10572ce9dde0SMikko Rapeli __u32 external_rev; 105881629cbaSAlex Deucher /** Revision id in PCI Config space */ 10592ce9dde0SMikko Rapeli __u32 pci_rev; 10602ce9dde0SMikko Rapeli __u32 family; 10612ce9dde0SMikko Rapeli __u32 num_shader_engines; 10622ce9dde0SMikko Rapeli __u32 num_shader_arrays_per_engine; 1063675da0ddSChristian König /* in KHz */ 10642ce9dde0SMikko Rapeli __u32 gpu_counter_freq; 10652ce9dde0SMikko Rapeli __u64 max_engine_clock; 10662ce9dde0SMikko Rapeli __u64 max_memory_clock; 106781629cbaSAlex Deucher /* cu information */ 10682ce9dde0SMikko Rapeli __u32 cu_active_number; 1069dbfe85eaSFlora Cui /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 10702ce9dde0SMikko Rapeli __u32 cu_ao_mask; 10712ce9dde0SMikko Rapeli __u32 cu_bitmap[4][4]; 107281629cbaSAlex Deucher /** Render backend pipe mask. One render backend is CB+DB. */ 10732ce9dde0SMikko Rapeli __u32 enabled_rb_pipes_mask; 10742ce9dde0SMikko Rapeli __u32 num_rb_pipes; 10752ce9dde0SMikko Rapeli __u32 num_hw_gfx_contexts; 1076e3e84b0aSMarek Olšák /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1077e3e84b0aSMarek Olšák __u32 pcie_gen; 10782ce9dde0SMikko Rapeli __u64 ids_flags; 107981629cbaSAlex Deucher /** Starting virtual address for UMDs. */ 10802ce9dde0SMikko Rapeli __u64 virtual_address_offset; 108102b70c8cSJammy Zhou /** The maximum virtual address */ 10822ce9dde0SMikko Rapeli __u64 virtual_address_max; 108381629cbaSAlex Deucher /** Required alignment of virtual addresses. */ 10842ce9dde0SMikko Rapeli __u32 virtual_address_alignment; 108581629cbaSAlex Deucher /** Page table entry - fragment size */ 10862ce9dde0SMikko Rapeli __u32 pte_fragment_size; 10872ce9dde0SMikko Rapeli __u32 gart_page_size; 1088a101a899SKen Wang /** constant engine ram size*/ 10892ce9dde0SMikko Rapeli __u32 ce_ram_size; 1090cab6d57cSJammy Zhou /** video memory type info*/ 10912ce9dde0SMikko Rapeli __u32 vram_type; 109281c59f54SKen Wang /** video memory bit width*/ 10932ce9dde0SMikko Rapeli __u32 vram_bit_width; 1094fa92754eSLeo Liu /* vce harvesting instance */ 10952ce9dde0SMikko Rapeli __u32 vce_harvest_config; 1096df6e2c4aSJunwei Zhang /* gfx double offchip LDS buffers */ 1097df6e2c4aSJunwei Zhang __u32 gc_double_offchip_lds_buf; 1098bce23e00SAlex Deucher /* NGG Primitive Buffer */ 1099bce23e00SAlex Deucher __u64 prim_buf_gpu_addr; 1100bce23e00SAlex Deucher /* NGG Position Buffer */ 1101bce23e00SAlex Deucher __u64 pos_buf_gpu_addr; 1102bce23e00SAlex Deucher /* NGG Control Sideband */ 1103bce23e00SAlex Deucher __u64 cntl_sb_buf_gpu_addr; 1104bce23e00SAlex Deucher /* NGG Parameter Cache */ 1105bce23e00SAlex Deucher __u64 param_buf_gpu_addr; 1106408bfe7cSJunwei Zhang __u32 prim_buf_size; 1107408bfe7cSJunwei Zhang __u32 pos_buf_size; 1108408bfe7cSJunwei Zhang __u32 cntl_sb_buf_size; 1109408bfe7cSJunwei Zhang __u32 param_buf_size; 1110408bfe7cSJunwei Zhang /* wavefront size*/ 1111408bfe7cSJunwei Zhang __u32 wave_front_size; 1112408bfe7cSJunwei Zhang /* shader visible vgprs*/ 1113408bfe7cSJunwei Zhang __u32 num_shader_visible_vgprs; 1114408bfe7cSJunwei Zhang /* CU per shader array*/ 1115408bfe7cSJunwei Zhang __u32 num_cu_per_sh; 1116408bfe7cSJunwei Zhang /* number of tcc blocks*/ 1117408bfe7cSJunwei Zhang __u32 num_tcc_blocks; 1118408bfe7cSJunwei Zhang /* gs vgt table depth*/ 1119408bfe7cSJunwei Zhang __u32 gs_vgt_table_depth; 1120408bfe7cSJunwei Zhang /* gs primitive buffer depth*/ 1121408bfe7cSJunwei Zhang __u32 gs_prim_buffer_depth; 1122408bfe7cSJunwei Zhang /* max gs wavefront per vgt*/ 1123408bfe7cSJunwei Zhang __u32 max_gs_waves_per_vgt; 1124e3e84b0aSMarek Olšák /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1125e3e84b0aSMarek Olšák __u32 pcie_num_lanes; 1126dbfe85eaSFlora Cui /* always on cu bitmap */ 1127dbfe85eaSFlora Cui __u32 cu_ao_bitmap[4][4]; 11285b565e0eSChristian König /** Starting high virtual address for UMDs. */ 11295b565e0eSChristian König __u64 high_va_offset; 11305b565e0eSChristian König /** The maximum high virtual address */ 11315b565e0eSChristian König __u64 high_va_max; 113222e96fa6SHawking Zhang /* gfx10 pa_sc_tile_steering_override */ 113322e96fa6SHawking Zhang __u32 pa_sc_tile_steering_override; 1134cf21e76aSMarek Olšák /* disabled TCCs */ 1135cf21e76aSMarek Olšák __u64 tcc_disabled_mask; 113688347fa1SEvan Quan __u64 min_engine_clock; 113788347fa1SEvan Quan __u64 min_memory_clock; 1138b299221fSMarek Olšák /* The following fields are only set on gfx11+, older chips set 0. */ 1139b299221fSMarek Olšák __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1140b299221fSMarek Olšák __u32 num_sqc_per_wgp; 1141b299221fSMarek Olšák __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1142b299221fSMarek Olšák __u32 sqc_inst_cache_size; 1143b299221fSMarek Olšák __u32 gl1c_cache_size; 1144b299221fSMarek Olšák __u32 gl2c_cache_size; 1145b299221fSMarek Olšák __u64 mall_size; /* AKA infinity cache */ 1146b299221fSMarek Olšák /* high 32 bits of the rb pipes mask */ 1147b299221fSMarek Olšák __u32 enabled_rb_pipes_mask_hi; 1148edd90380SAlex Deucher /* shadow area size for gfx11 */ 1149edd90380SAlex Deucher __u32 shadow_size; 1150edd90380SAlex Deucher /* shadow area base virtual alignment for gfx11 */ 1151edd90380SAlex Deucher __u32 shadow_alignment; 1152edd90380SAlex Deucher /* context save area size for gfx11 */ 1153edd90380SAlex Deucher __u32 csa_size; 1154edd90380SAlex Deucher /* context save area base virtual alignment for gfx11 */ 1155edd90380SAlex Deucher __u32 csa_alignment; 115681629cbaSAlex Deucher }; 115781629cbaSAlex Deucher 115881629cbaSAlex Deucher struct drm_amdgpu_info_hw_ip { 115981629cbaSAlex Deucher /** Version of h/w IP */ 11602ce9dde0SMikko Rapeli __u32 hw_ip_version_major; 11612ce9dde0SMikko Rapeli __u32 hw_ip_version_minor; 116281629cbaSAlex Deucher /** Capabilities */ 11632ce9dde0SMikko Rapeli __u64 capabilities_flags; 116471062f43SKen Wang /** command buffer address start alignment*/ 11652ce9dde0SMikko Rapeli __u32 ib_start_alignment; 116671062f43SKen Wang /** command buffer size alignment*/ 11672ce9dde0SMikko Rapeli __u32 ib_size_alignment; 116881629cbaSAlex Deucher /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 11692ce9dde0SMikko Rapeli __u32 available_rings; 1170af14e7c2SAlex Deucher /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1171af14e7c2SAlex Deucher __u32 ip_discovery_version; 117281629cbaSAlex Deucher }; 117381629cbaSAlex Deucher 117444879b62SArindam Nath struct drm_amdgpu_info_num_handles { 117544879b62SArindam Nath /** Max handles as supported by firmware for UVD */ 117644879b62SArindam Nath __u32 uvd_max_handles; 117744879b62SArindam Nath /** Handles currently in use for UVD */ 117844879b62SArindam Nath __u32 uvd_used_handles; 117944879b62SArindam Nath }; 118044879b62SArindam Nath 1181bbe87974SAlex Deucher #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1182bbe87974SAlex Deucher 1183bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry { 1184bbe87974SAlex Deucher /** System clock */ 1185bbe87974SAlex Deucher __u32 sclk; 1186bbe87974SAlex Deucher /** Memory clock */ 1187bbe87974SAlex Deucher __u32 mclk; 1188bbe87974SAlex Deucher /** VCE clock */ 1189bbe87974SAlex Deucher __u32 eclk; 1190bbe87974SAlex Deucher __u32 pad; 1191bbe87974SAlex Deucher }; 1192bbe87974SAlex Deucher 1193bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table { 1194bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1195bbe87974SAlex Deucher __u32 num_valid_entries; 1196bbe87974SAlex Deucher __u32 pad; 1197bbe87974SAlex Deucher }; 1198bbe87974SAlex Deucher 1199f35e9bdbSAlex Deucher /* query video encode/decode caps */ 1200f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1201f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1202f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1203f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1204f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1205f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1206f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1207f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1208f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1209f35e9bdbSAlex Deucher 1210f35e9bdbSAlex Deucher struct drm_amdgpu_info_video_codec_info { 1211f35e9bdbSAlex Deucher __u32 valid; 1212f35e9bdbSAlex Deucher __u32 max_width; 1213f35e9bdbSAlex Deucher __u32 max_height; 1214f35e9bdbSAlex Deucher __u32 max_pixels_per_frame; 1215f35e9bdbSAlex Deucher __u32 max_level; 1216f35e9bdbSAlex Deucher __u32 pad; 1217f35e9bdbSAlex Deucher }; 1218f35e9bdbSAlex Deucher 1219f35e9bdbSAlex Deucher struct drm_amdgpu_info_video_caps { 1220f35e9bdbSAlex Deucher struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1221f35e9bdbSAlex Deucher }; 1222f35e9bdbSAlex Deucher 122381629cbaSAlex Deucher /* 122481629cbaSAlex Deucher * Supported GPU families 122581629cbaSAlex Deucher */ 122681629cbaSAlex Deucher #define AMDGPU_FAMILY_UNKNOWN 0 1227295d0dafSKen Wang #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 122881629cbaSAlex Deucher #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 122981629cbaSAlex Deucher #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 123081629cbaSAlex Deucher #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 123139bb0c92SSamuel Li #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1232a8f1f1ceSAlex Deucher #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 12332ca8a5d2SChunming Zhou #define AMDGPU_FAMILY_RV 142 /* Raven */ 1234107c34bcSHuang Rui #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1235f7b2cdb2SHuang Rui #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 12365eca8379SHawking Zhang #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 123790a187d2SAaron Liu #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1238cbe757ecSHuang Rui #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1239874bfdfaSYifan Zhang #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1240a65dbf7cSPrike Liang #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 124181629cbaSAlex Deucher 1242cfa7152fSEmil Velikov #if defined(__cplusplus) 1243cfa7152fSEmil Velikov } 1244cfa7152fSEmil Velikov #endif 1245cfa7152fSEmil Velikov 124681629cbaSAlex Deucher #endif 1247