Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70 |
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#
89927235 |
| 20-Sep-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add UAPI for allocating doorbell memory
This patch adds flags for a new gem domain AMDGPU_GEM_DOMAIN_DOORBELL in the UAPI layer.
V2: Drop 'memory' from description (Christian)
Cc: Alex
drm/amdgpu: add UAPI for allocating doorbell memory
This patch adds flags for a new gem domain AMDGPU_GEM_DOMAIN_DOORBELL in the UAPI layer.
V2: Drop 'memory' from description (Christian)
Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Reviewed-by: Christian Koenig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
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#
489763af |
| 24-Apr-2023 |
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> |
drm/amdgpu: add new flag to AMDGPU_CTX_QUERY2
OpenGL EXT_robustness extension expects the driver to stop reporting GUILTY_CONTEXT_RESET when the reset has completed and the GPU is ready to accept su
drm/amdgpu: add new flag to AMDGPU_CTX_QUERY2
OpenGL EXT_robustness extension expects the driver to stop reporting GUILTY_CONTEXT_RESET when the reset has completed and the GPU is ready to accept submission again.
This commit adds a AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS flag, that let the UMD know that the reset is still not finished.
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290
Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: André Almeida <andrealmeid@igalia.com> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
edd90380 |
| 09-Mar-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add UAPI to query GFX shadow sizes
Add UAPI to query the GFX shadow buffer requirements for preemption on GFX11. UMDs need to specify the shadow areas for preemption.
v2: move into exi
drm/amdgpu: add UAPI to query GFX shadow sizes
Add UAPI to query the GFX shadow buffer requirements for preemption on GFX11. UMDs need to specify the shadow areas for preemption.
v2: move into existing asic info query drop GDS as its use is determined by the UMD (Marek) v3: Update comments to note that alignment is base virtual alignment (Alex)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
043dc33f |
| 09-Mar-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/UAPI: add new CS chunk for GFX shadow buffers
For GFX11, the UMD needs to allocate some shadow buffers to be used for preemption. The UMD allocates the buffers and passes the GPU virtual
drm/amdgpu/UAPI: add new CS chunk for GFX shadow buffers
For GFX11, the UMD needs to allocate some shadow buffers to be used for preemption. The UMD allocates the buffers and passes the GPU virtual address to the kernel since the kernel will program the packet that specified these addresses as part of its IB submission frame.
v2: UMD passes shadow init to tell kernel when to initialize the shadow
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4f18b9a6 |
| 13-Apr-2023 |
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> |
drm/amdgpu: Add support for querying the max ibs in a submission. (v3)
This info would be used by radv to figure out when we need to split a submission into multiple submissions. radv currently has
drm/amdgpu: Add support for querying the max ibs in a submission. (v3)
This info would be used by radv to figure out when we need to split a submission into multiple submissions. radv currently has a limit of 192 which seems to work for most gfx submissions, but is way too high for e.g. compute or sdma.
Userspace is available at https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3
v3: Completely rewrote based on suggestion of making it a separate query.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b299221f |
| 29-Jan-2023 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: add more fields into device info, caches sizes, etc.
AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD: important for conformance on gfx11 Other fields are exposed from IP discovery. enabled_rb_pi
drm/amdgpu: add more fields into device info, caches sizes, etc.
AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD: important for conformance on gfx11 Other fields are exposed from IP discovery. enabled_rb_pipes_mask_hi is added for future chips, currently 0.
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e3e84b0a |
| 24-Dec-2022 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: return the PCIe gen and lanes from the INFO ioctl
For computing PCIe bandwidth in userspace and troubleshooting PCIe bandwidth issues. Note that this intentionally fills holes and paddin
drm/amdgpu: return the PCIe gen and lanes from the INFO ioctl
For computing PCIe bandwidth in userspace and troubleshooting PCIe bandwidth issues. Note that this intentionally fills holes and padding in drm_amdgpu_info_device.
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20790
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
88347fa1 |
| 04-Dec-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: expose the minimum shader/memory clock frequency
Otherwise, some UMD tools will treate them as 0 at default while actually they are not.
Signed-off-by: Evan Quan <evan.quan@amd.com> Rev
drm/amdgpu: expose the minimum shader/memory clock frequency
Otherwise, some UMD tools will treate them as 0 at default while actually they are not.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5cfd9784 |
| 05-Dec-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: expose peak profiling mode shader/memory clocks
Expose those informations to UMD who need them as for standard profiling mode.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by:
drm/amdgpu: expose peak profiling mode shader/memory clocks
Expose those informations to UMD who need them as for standard profiling mode.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64 |
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#
d1a372af |
| 26-Aug-2022 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Set MTYPE in PTE based on BO flags
The same BO may need different MTYPEs and SNOOP flags in PTEs depending on its current location relative to the mapping GPU. Setting MTYPEs from client
drm/amdgpu: Set MTYPE in PTE based on BO flags
The same BO may need different MTYPEs and SNOOP flags in PTEs depending on its current location relative to the mapping GPU. Setting MTYPEs from clients ahead of time is not practical for coherent memory sharing. Instead determine the correct MTYPE for the desired coherence model and current BO location when updating the page tables.
To maintain backwards compatibility with MTYPE-selection in AMDGPU_VA_OP_MAP, the coherence-model-based MTYPE selection is only applied if it chooses an MTYPE other than MTYPE_NC (the default).
Add two AMDGPU_GEM_CREATE_... flags to indicate the coherence model. The default if no flag is specified is non-coherent (i.e. coarse-grained coherent at dispatch boundaries).
Update amdgpu_amdkfd_gpuvm.c to use this new method to choose the correct MTYPE depending on the current memory location.
v2: * check that bo is not NULL (e.g. PRT mappings) * Fix missing ~ bitmask in gmc_v11_0.c v3: * squash in "drm/amdgpu: Inherit coherence flags on dmabuf import"
Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
68bc1473 |
| 16-Sep-2022 |
David Francis <David.Francis@amd.com> |
drm/amd: Add IMU fw version to fw version queries
IMU is a new firmware for GFX11.
There are four means by which firmware version can be queried from the driver: device attributes, vf2pf, debugfs,
drm/amd: Add IMU fw version to fw version queries
IMU is a new firmware for GFX11.
There are four means by which firmware version can be queried from the driver: device attributes, vf2pf, debugfs, and the AMDGPU_INFO_FW_VERSION option in the amdgpu info ioctl.
Add IMU as an option for those four methods.
V2: Added debugfs
Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b7236296 |
| 16-Sep-2022 |
David Francis <David.Francis@amd.com> |
drm/amd: Add IMU fw version to fw version queries
IMU is a new firmware for GFX11.
There are four means by which firmware version can be queried from the driver: device attributes, vf2pf, debugfs,
drm/amd: Add IMU fw version to fw version queries
IMU is a new firmware for GFX11.
There are four means by which firmware version can be queried from the driver: device attributes, vf2pf, debugfs, and the AMDGPU_INFO_FW_VERSION option in the amdgpu info ioctl.
Add IMU as an option for those four methods.
V2: Added debugfs
Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
10faf078 |
| 15-Sep-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add MES and MES-KIQ version in debugfs
This patch addes MES and MES-KIQ version in debugfs.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com>
drm/amdgpu: add MES and MES-KIQ version in debugfs
This patch addes MES and MES-KIQ version in debugfs.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2f9d510f |
| 13-Sep-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add two new subquery ids
To support query rlcp and rlcv firmware version from existing AMDGPU_INFO_FW_VERSION interface
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
drm/amdgpu: add two new subquery ids
To support query rlcp and rlcv firmware version from existing AMDGPU_INFO_FW_VERSION interface
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38 |
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#
af14e7c2 |
| 05-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add the IP discovery IP versions for HW INFO data
Use the former pad element to store the IP versions from the IP discovery table. This allows userspace to get the IP version from the k
drm/amdgpu: add the IP discovery IP versions for HW INFO data
Use the former pad element to store the IP versions from the IP discovery table. This allows userspace to get the IP version from the kernel to better align with hardware IP versions.
Proposed mesa patch: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411/diffs?commit_id=c8a63590dfd0d64e6e6a634dcfed993f135dd075
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4528c186 |
| 14-Jul-2022 |
Ruijing Dong <ruijing.dong@amd.com> |
drm/amdgpu: add comment to HW_IP_VCN_ENC type
From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support both encoding and decoding jobs.
Link: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/2
drm/amdgpu: add comment to HW_IP_VCN_ENC type
From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support both encoding and decoding jobs.
Link: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/245/commits Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b6c65a2c |
| 06-May-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add AMDGPU_VM_NOALLOC v2
Add the AMDGPU_VM_NOALLOC flag to let userspace control MALL allocation.
v2: also add the flag to the allowed flags.
Signed-off-by: Christian König <christian.
drm/amdgpu: add AMDGPU_VM_NOALLOC v2
Add the AMDGPU_VM_NOALLOC flag to let userspace control MALL allocation.
v2: also add the flag to the allowed flags.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fab2cc83 |
| 06-May-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add AMDGPU_GEM_CREATE_DISCARDABLE
Add a AMDGPU_GEM_CREATE_DISCARDABLE flag to note that the content of a BO doesn't needs to be preserved during eviction.
KFD was already using a simila
drm/amdgpu: add AMDGPU_GEM_CREATE_DISCARDABLE
Add a AMDGPU_GEM_CREATE_DISCARDABLE flag to note that the content of a BO doesn't needs to be preserved during eviction.
KFD was already using a similar functionality for SVM BOs so replace the internal flag with the new UAPI.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d534ca71 |
| 23-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: differentiate between LP and non-LP DDR memory
Some applications want to know whether the memory is LP or not.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deu
drm/amdgpu: differentiate between LP and non-LP DDR memory
Some applications want to know whether the memory is LP or not.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60 |
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#
cbe757ec |
| 01-Aug-2021 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add GC 11.0.1 family id
Add a flag to define GC 11.0.1.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.de
drm/amdgpu: add GC 11.0.1 family id
Add a flag to define GC 11.0.1.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5eca8379 |
| 21-Feb-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add GC v11_0_0 family id
Add GC v11_0_0 family id
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.
drm/amdgpu: add GC v11_0_0 family id
Add GC v11_0_0 family id
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
874bfdfa |
| 10-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add gc 10.3.6 support
this patch adds gc 10.3.6 support.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <
drm/amdgpu: add gc 10.3.6 support
this patch adds gc 10.3.6 support.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a65dbf7c |
| 22-Dec-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/gfx10: Add GC 10.3.7 Support
Needed to properly initialize GC 10.3.7.
Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by
drm/amdgpu/gfx10: Add GC 10.3.7 Support
Needed to properly initialize GC 10.3.7.
Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8cda7a4f |
| 07-Jan-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/UAPI: add new CTX OP to get/set stable pstates
Add a new CTX ioctl operation to set stable pstates for profiling. When creating traces for tools like RGP or using SPM or doing performance
drm/amdgpu/UAPI: add new CTX OP to get/set stable pstates
Add a new CTX ioctl operation to set stable pstates for profiling. When creating traces for tools like RGP or using SPM or doing performance profiling, it's required to enable a special stable profiling power state on the GPU. These profiling states set fixed clocks and disable certain other power features like powergating which may impact the results.
Historically, these profiling pstates were enabled via sysfs, but this adds an interface to enable it via the CTX ioctl from the application. Since the power state is global only one application can set it at a time, so if multiple applications try and use it only the first will get it, the ioctl will return -EBUSY for others. The sysfs interface will override whatever has been set by this interface.
Mesa MR: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/207
v2: don't default r = 0; v3: rebase on Evan's PM cleanup
Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c4381d0e |
| 12-Jan-2022 |
Bokun Zhang <Bokun.Zhang@amd.com> |
drm/amdgpu: Add interface to load SRIOV cap FW
- Add interface to load SRIOV cap FW. If the FW does not exist, simply skip this FW loading routine. This FW will only be loaded under SRIOV. Other
drm/amdgpu: Add interface to load SRIOV cap FW
- Add interface to load SRIOV cap FW. If the FW does not exist, simply skip this FW loading routine. This FW will only be loaded under SRIOV. Other driver configuration will not be affected. By adding this interface, it will make us easier to prepare SRIOV Linux guest driver for different users.
- Update sysfs interface to read cap FW version.
- Refactor PSP FW loading routine under SRIOV to use a unified SWITCH statement instead of using IF statement
- Remove redundant amdgpu_sriov_vf() check in FW loading routine
Acked-by: Monk Liu <monk.liu@amd.com> Acked-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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