182d375d1SZhi Wang /*
282d375d1SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
382d375d1SZhi Wang *
482d375d1SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a
582d375d1SZhi Wang * copy of this software and associated documentation files (the "Software"),
682d375d1SZhi Wang * to deal in the Software without restriction, including without limitation
782d375d1SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
882d375d1SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the
982d375d1SZhi Wang * Software is furnished to do so, subject to the following conditions:
1082d375d1SZhi Wang *
1182d375d1SZhi Wang * The above copyright notice and this permission notice (including the next
1282d375d1SZhi Wang * paragraph) shall be included in all copies or substantial portions of the
1382d375d1SZhi Wang * Software.
1482d375d1SZhi Wang *
1582d375d1SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1682d375d1SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1782d375d1SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1882d375d1SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1982d375d1SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2082d375d1SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2182d375d1SZhi Wang * SOFTWARE.
2282d375d1SZhi Wang *
2382d375d1SZhi Wang * Authors:
2482d375d1SZhi Wang * Eddie Dong <eddie.dong@intel.com>
2582d375d1SZhi Wang * Kevin Tian <kevin.tian@intel.com>
2682d375d1SZhi Wang *
2782d375d1SZhi Wang * Contributors:
2882d375d1SZhi Wang * Ping Gao <ping.a.gao@intel.com>
2982d375d1SZhi Wang * Zhi Wang <zhi.a.wang@intel.com>
3082d375d1SZhi Wang * Bing Niu <bing.niu@intel.com>
3182d375d1SZhi Wang *
3282d375d1SZhi Wang */
3382d375d1SZhi Wang
3482d375d1SZhi Wang #include "i915_drv.h"
35feddf6e8SZhenyu Wang #include "gvt.h"
36feddf6e8SZhenyu Wang #include "i915_pvinfo.h"
3782d375d1SZhi Wang
populate_pvinfo_page(struct intel_vgpu * vgpu)3823736d1bSPing Gao void populate_pvinfo_page(struct intel_vgpu *vgpu)
3982d375d1SZhi Wang {
40a61ac1e7SChris Wilson struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
4182d375d1SZhi Wang /* setup the ballooning information */
4290551a12SZhenyu Wang vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
4390551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
4490551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
4590551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
4690551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
47a2ae95afSWeinan Li
48ca6ac684SChris Wilson vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
4990551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
50aa36ed6dSChangbin Du vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
51a2ae95afSWeinan Li
5290551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
5382d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu);
5490551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
5582d375d1SZhi Wang vgpu_aperture_sz(vgpu);
5690551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
5782d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu);
5890551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
5982d375d1SZhi Wang vgpu_hidden_sz(vgpu);
6082d375d1SZhi Wang
6190551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
6282d375d1SZhi Wang
631c6ccad8STina Zhang vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
641c6ccad8STina Zhang vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
651c6ccad8STina Zhang
6682d375d1SZhi Wang gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
6782d375d1SZhi Wang gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
6882d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
6982d375d1SZhi Wang gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
7082d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
7182d375d1SZhi Wang gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
7282d375d1SZhi Wang
7312d58619SPankaj Bharadiya drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
7482d375d1SZhi Wang }
7582d375d1SZhi Wang
761aa3834fSChristoph Hellwig /*
771aa3834fSChristoph Hellwig * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU
781aa3834fSChristoph Hellwig * generation type (e.g V4 as BDW server, V5 as SKL server).
791aa3834fSChristoph Hellwig *
801aa3834fSChristoph Hellwig * Depening on the physical SKU resource, we might see vGPU types like
811aa3834fSChristoph Hellwig * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create different types of
821aa3834fSChristoph Hellwig * vGPU on same physical GPU depending on available resource. Each vGPU
831aa3834fSChristoph Hellwig * type will have a different number of avail_instance to indicate how
841aa3834fSChristoph Hellwig * many vGPU instance can be created for this type.
851aa3834fSChristoph Hellwig */
86bc90d097SPing Gao #define VGPU_MAX_WEIGHT 16
87bc90d097SPing Gao #define VGPU_WEIGHT(vgpu_num) \
88bc90d097SPing Gao (VGPU_MAX_WEIGHT / (vgpu_num))
89bc90d097SPing Gao
901aa3834fSChristoph Hellwig static const struct intel_vgpu_config intel_vgpu_configs[] = {
91bc90d097SPing Gao { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
92bc90d097SPing Gao { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
93bc90d097SPing Gao { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
94bc90d097SPing Gao { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
95191020b6SZhenyu Wang };
96191020b6SZhenyu Wang
9782d375d1SZhi Wang /**
981f31c829SZhenyu Wang * intel_gvt_init_vgpu_types - initialize vGPU type list
991f31c829SZhenyu Wang * @gvt : GVT device
1001f31c829SZhenyu Wang *
1011f31c829SZhenyu Wang * Initialize vGPU type list based on available resource.
1021f31c829SZhenyu Wang *
1031f31c829SZhenyu Wang */
intel_gvt_init_vgpu_types(struct intel_gvt * gvt)1041f31c829SZhenyu Wang int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
1051f31c829SZhenyu Wang {
1061aa3834fSChristoph Hellwig unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
1071aa3834fSChristoph Hellwig unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
1081aa3834fSChristoph Hellwig unsigned int num_types = ARRAY_SIZE(intel_vgpu_configs);
1091aa3834fSChristoph Hellwig unsigned int i;
1101f31c829SZhenyu Wang
1116396bb22SKees Cook gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type),
1121f31c829SZhenyu Wang GFP_KERNEL);
1131f31c829SZhenyu Wang if (!gvt->types)
1141f31c829SZhenyu Wang return -ENOMEM;
1151f31c829SZhenyu Wang
116da44c340SChristoph Hellwig gvt->mdev_types = kcalloc(num_types, sizeof(*gvt->mdev_types),
117da44c340SChristoph Hellwig GFP_KERNEL);
118da44c340SChristoph Hellwig if (!gvt->mdev_types)
119da44c340SChristoph Hellwig goto out_free_types;
120da44c340SChristoph Hellwig
1211f31c829SZhenyu Wang for (i = 0; i < num_types; ++i) {
1221aa3834fSChristoph Hellwig const struct intel_vgpu_config *conf = &intel_vgpu_configs[i];
1231aa3834fSChristoph Hellwig
1241aa3834fSChristoph Hellwig if (low_avail / conf->low_mm == 0)
1251f31c829SZhenyu Wang break;
1261aa3834fSChristoph Hellwig if (conf->weight < 1 || conf->weight > VGPU_MAX_WEIGHT)
127da44c340SChristoph Hellwig goto out_free_mdev_types;
128bc90d097SPing Gao
1291aa3834fSChristoph Hellwig sprintf(gvt->types[i].name, "GVTg_V%u_%s",
1301aa3834fSChristoph Hellwig GRAPHICS_VER(gvt->gt->i915) == 8 ? 4 : 5, conf->name);
1311aa3834fSChristoph Hellwig gvt->types[i].conf = conf;
1321f31c829SZhenyu Wang
133bc90d097SPing Gao gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
134f2fbc72eSChristoph Hellwig i, gvt->types[i].name,
135f2fbc72eSChristoph Hellwig min(low_avail / conf->low_mm,
136f2fbc72eSChristoph Hellwig high_avail / conf->high_mm),
1371aa3834fSChristoph Hellwig conf->low_mm, conf->high_mm, conf->fence,
1381aa3834fSChristoph Hellwig conf->weight, vgpu_edid_str(conf->edid));
139da44c340SChristoph Hellwig
140da44c340SChristoph Hellwig gvt->mdev_types[i] = &gvt->types[i].type;
141da44c340SChristoph Hellwig gvt->mdev_types[i]->sysfs_name = gvt->types[i].name;
1421f31c829SZhenyu Wang }
1431f31c829SZhenyu Wang
1441f31c829SZhenyu Wang gvt->num_types = i;
1451f31c829SZhenyu Wang return 0;
14698828955SChristoph Hellwig
147da44c340SChristoph Hellwig out_free_mdev_types:
148da44c340SChristoph Hellwig kfree(gvt->mdev_types);
14998828955SChristoph Hellwig out_free_types:
15098828955SChristoph Hellwig kfree(gvt->types);
15198828955SChristoph Hellwig return -EINVAL;
1521f31c829SZhenyu Wang }
1531f31c829SZhenyu Wang
intel_gvt_clean_vgpu_types(struct intel_gvt * gvt)1541f31c829SZhenyu Wang void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
1551f31c829SZhenyu Wang {
156da44c340SChristoph Hellwig kfree(gvt->mdev_types);
1571f31c829SZhenyu Wang kfree(gvt->types);
1581f31c829SZhenyu Wang }
1591f31c829SZhenyu Wang
1601f31c829SZhenyu Wang /**
161df947eb6SMauro Carvalho Chehab * intel_gvt_activate_vgpu - activate a virtual GPU
162b79c52aeSZhi Wang * @vgpu: virtual GPU
163b79c52aeSZhi Wang *
164b79c52aeSZhi Wang * This function is called when user wants to activate a virtual GPU.
165b79c52aeSZhi Wang *
166b79c52aeSZhi Wang */
intel_gvt_activate_vgpu(struct intel_vgpu * vgpu)167b79c52aeSZhi Wang void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
168b79c52aeSZhi Wang {
169a06d4b9eSZhi Wang set_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);
170b79c52aeSZhi Wang }
171b79c52aeSZhi Wang
172b79c52aeSZhi Wang /**
173df947eb6SMauro Carvalho Chehab * intel_gvt_deactivate_vgpu - deactivate a virtual GPU
174b79c52aeSZhi Wang * @vgpu: virtual GPU
175b79c52aeSZhi Wang *
176b79c52aeSZhi Wang * This function is called when user wants to deactivate a virtual GPU.
177f9090d4cSHang Yuan * The virtual GPU will be stopped.
178b79c52aeSZhi Wang *
179b79c52aeSZhi Wang */
intel_gvt_deactivate_vgpu(struct intel_vgpu * vgpu)180b79c52aeSZhi Wang void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
181b79c52aeSZhi Wang {
182f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock);
183b79c52aeSZhi Wang
184a06d4b9eSZhi Wang clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);
185b79c52aeSZhi Wang
1861406a14bSZhi Wang if (atomic_read(&vgpu->submission.running_workload_num)) {
187f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock);
188b79c52aeSZhi Wang intel_gvt_wait_vgpu_idle(vgpu);
189f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock);
190b79c52aeSZhi Wang }
191b79c52aeSZhi Wang
192b79c52aeSZhi Wang intel_vgpu_stop_schedule(vgpu);
193b79c52aeSZhi Wang
194f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock);
195b79c52aeSZhi Wang }
196b79c52aeSZhi Wang
197b79c52aeSZhi Wang /**
198f9090d4cSHang Yuan * intel_gvt_release_vgpu - release a virtual GPU
199f9090d4cSHang Yuan * @vgpu: virtual GPU
200f9090d4cSHang Yuan *
201f9090d4cSHang Yuan * This function is called when user wants to release a virtual GPU.
202f9090d4cSHang Yuan * The virtual GPU will be stopped and all runtime information will be
203f9090d4cSHang Yuan * destroyed.
204f9090d4cSHang Yuan *
205f9090d4cSHang Yuan */
intel_gvt_release_vgpu(struct intel_vgpu * vgpu)206f9090d4cSHang Yuan void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
207f9090d4cSHang Yuan {
208f9090d4cSHang Yuan intel_gvt_deactivate_vgpu(vgpu);
209f9090d4cSHang Yuan
210f9090d4cSHang Yuan mutex_lock(&vgpu->vgpu_lock);
211ba25d977SColin Xu vgpu->d3_entered = false;
212f9090d4cSHang Yuan intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
213f9090d4cSHang Yuan intel_vgpu_dmabuf_cleanup(vgpu);
214f9090d4cSHang Yuan mutex_unlock(&vgpu->vgpu_lock);
215f9090d4cSHang Yuan }
216f9090d4cSHang Yuan
217f9090d4cSHang Yuan /**
21882d375d1SZhi Wang * intel_gvt_destroy_vgpu - destroy a virtual GPU
21982d375d1SZhi Wang * @vgpu: virtual GPU
22082d375d1SZhi Wang *
22182d375d1SZhi Wang * This function is called when user wants to destroy a virtual GPU.
22282d375d1SZhi Wang *
22382d375d1SZhi Wang */
intel_gvt_destroy_vgpu(struct intel_vgpu * vgpu)22482d375d1SZhi Wang void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
22582d375d1SZhi Wang {
22682d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt;
227a61ac1e7SChris Wilson struct drm_i915_private *i915 = gvt->gt->i915;
22882d375d1SZhi Wang
229a06d4b9eSZhi Wang drm_WARN(&i915->drm, test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status),
230a06d4b9eSZhi Wang "vGPU is still active!\n");
231b79c52aeSZhi Wang
23204d6067fSZhenyu Wang /*
23304d6067fSZhenyu Wang * remove idr first so later clean can judge if need to stop
23404d6067fSZhenyu Wang * service if no active vgpu.
23504d6067fSZhenyu Wang */
23604d6067fSZhenyu Wang mutex_lock(&gvt->lock);
23704d6067fSZhenyu Wang idr_remove(&gvt->vgpu_idr, vgpu->id);
23804d6067fSZhenyu Wang mutex_unlock(&gvt->lock);
23904d6067fSZhenyu Wang
24004d6067fSZhenyu Wang mutex_lock(&vgpu->vgpu_lock);
241bc7b0be3SChangbin Du intel_gvt_debugfs_remove_vgpu(vgpu);
2424b63960eSZhi Wang intel_vgpu_clean_sched_policy(vgpu);
243874b6a91SZhi Wang intel_vgpu_clean_submission(vgpu);
24404d348aeSZhi Wang intel_vgpu_clean_display(vgpu);
2454d60c5fdSZhi Wang intel_vgpu_clean_opregion(vgpu);
2467759ca3aSZhipeng Gong intel_vgpu_reset_ggtt(vgpu, true);
2472707e444SZhi Wang intel_vgpu_clean_gtt(vgpu);
2484c705ad0SChristoph Hellwig intel_vgpu_detach_regions(vgpu);
24982d375d1SZhi Wang intel_vgpu_free_resource(vgpu);
250cdcc4347SChangbin Du intel_vgpu_clean_mmio(vgpu);
251e546e281STina Zhang intel_vgpu_dmabuf_cleanup(vgpu);
252f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock);
25382d375d1SZhi Wang }
25482d375d1SZhi Wang
255afe04fbeSPing Gao #define IDLE_VGPU_IDR 0
256afe04fbeSPing Gao
257afe04fbeSPing Gao /**
258afe04fbeSPing Gao * intel_gvt_create_idle_vgpu - create an idle virtual GPU
259afe04fbeSPing Gao * @gvt: GVT device
260afe04fbeSPing Gao *
261afe04fbeSPing Gao * This function is called when user wants to create an idle virtual GPU.
262afe04fbeSPing Gao *
263afe04fbeSPing Gao * Returns:
264afe04fbeSPing Gao * pointer to intel_vgpu, error pointer if failed.
265afe04fbeSPing Gao */
intel_gvt_create_idle_vgpu(struct intel_gvt * gvt)266afe04fbeSPing Gao struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
267afe04fbeSPing Gao {
268afe04fbeSPing Gao struct intel_vgpu *vgpu;
269afe04fbeSPing Gao enum intel_engine_id i;
270afe04fbeSPing Gao int ret;
271afe04fbeSPing Gao
272afe04fbeSPing Gao vgpu = vzalloc(sizeof(*vgpu));
273afe04fbeSPing Gao if (!vgpu)
274afe04fbeSPing Gao return ERR_PTR(-ENOMEM);
275afe04fbeSPing Gao
276afe04fbeSPing Gao vgpu->id = IDLE_VGPU_IDR;
277afe04fbeSPing Gao vgpu->gvt = gvt;
278f25a49abSColin Xu mutex_init(&vgpu->vgpu_lock);
279afe04fbeSPing Gao
280afe04fbeSPing Gao for (i = 0; i < I915_NUM_ENGINES; i++)
2811406a14bSZhi Wang INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
282afe04fbeSPing Gao
283afe04fbeSPing Gao ret = intel_vgpu_init_sched_policy(vgpu);
284afe04fbeSPing Gao if (ret)
285afe04fbeSPing Gao goto out_free_vgpu;
286afe04fbeSPing Gao
287a06d4b9eSZhi Wang clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);
288afe04fbeSPing Gao return vgpu;
289afe04fbeSPing Gao
290afe04fbeSPing Gao out_free_vgpu:
291afe04fbeSPing Gao vfree(vgpu);
292afe04fbeSPing Gao return ERR_PTR(ret);
293afe04fbeSPing Gao }
294afe04fbeSPing Gao
295afe04fbeSPing Gao /**
296df947eb6SMauro Carvalho Chehab * intel_gvt_destroy_idle_vgpu - destroy an idle virtual GPU
297afe04fbeSPing Gao * @vgpu: virtual GPU
298afe04fbeSPing Gao *
299afe04fbeSPing Gao * This function is called when user wants to destroy an idle virtual GPU.
300afe04fbeSPing Gao *
301afe04fbeSPing Gao */
intel_gvt_destroy_idle_vgpu(struct intel_vgpu * vgpu)302afe04fbeSPing Gao void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
303afe04fbeSPing Gao {
304f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock);
305afe04fbeSPing Gao intel_vgpu_clean_sched_policy(vgpu);
306f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock);
307f25a49abSColin Xu
308afe04fbeSPing Gao vfree(vgpu);
309afe04fbeSPing Gao }
310afe04fbeSPing Gao
intel_gvt_create_vgpu(struct intel_vgpu * vgpu,const struct intel_vgpu_config * conf)3111aa3834fSChristoph Hellwig int intel_gvt_create_vgpu(struct intel_vgpu *vgpu,
3121aa3834fSChristoph Hellwig const struct intel_vgpu_config *conf)
31382d375d1SZhi Wang {
314a5ddd2a9SKevin Tian struct intel_gvt *gvt = vgpu->gvt;
31528284943SZhenyu Wang struct drm_i915_private *dev_priv = gvt->gt->i915;
31682d375d1SZhi Wang int ret;
31782d375d1SZhi Wang
3181aa3834fSChristoph Hellwig gvt_dbg_core("low %u MB high %u MB fence %u\n",
3191aa3834fSChristoph Hellwig BYTES_TO_MB(conf->low_mm), BYTES_TO_MB(conf->high_mm),
3201aa3834fSChristoph Hellwig conf->fence);
32182d375d1SZhi Wang
3221aa3834fSChristoph Hellwig mutex_lock(&gvt->lock);
323afe04fbeSPing Gao ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
324afe04fbeSPing Gao GFP_KERNEL);
32582d375d1SZhi Wang if (ret < 0)
326*dd62071fSDeepak R Varma goto out_unlock;
32782d375d1SZhi Wang
32882d375d1SZhi Wang vgpu->id = ret;
3291aa3834fSChristoph Hellwig vgpu->sched_ctl.weight = conf->weight;
330f25a49abSColin Xu mutex_init(&vgpu->vgpu_lock);
331d6c6113bSHang Yuan mutex_init(&vgpu->dmabuf_lock);
332e546e281STina Zhang INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
333e502a2afSChangbin Du INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
33464e65f44SDeepak R Varma idr_init_base(&vgpu->object_idr, 1);
3351aa3834fSChristoph Hellwig intel_vgpu_init_cfg_space(vgpu, 1);
336ba25d977SColin Xu vgpu->d3_entered = false;
33782d375d1SZhi Wang
338cdcc4347SChangbin Du ret = intel_vgpu_init_mmio(vgpu);
33982d375d1SZhi Wang if (ret)
3404e537891SJike Song goto out_clean_idr;
34182d375d1SZhi Wang
3421aa3834fSChristoph Hellwig ret = intel_vgpu_alloc_resource(vgpu, conf);
34382d375d1SZhi Wang if (ret)
34482d375d1SZhi Wang goto out_clean_vgpu_mmio;
34582d375d1SZhi Wang
34682d375d1SZhi Wang populate_pvinfo_page(vgpu);
34782d375d1SZhi Wang
3482707e444SZhi Wang ret = intel_vgpu_init_gtt(vgpu);
3492707e444SZhi Wang if (ret)
35062980cacSChristoph Hellwig goto out_clean_vgpu_resource;
3512707e444SZhi Wang
3524dff110bSXiong Zhang ret = intel_vgpu_init_opregion(vgpu);
35304d348aeSZhi Wang if (ret)
3548f89743bSJike Song goto out_clean_gtt;
35504d348aeSZhi Wang
3561aa3834fSChristoph Hellwig ret = intel_vgpu_init_display(vgpu, conf->edid);
3574dff110bSXiong Zhang if (ret)
3584dff110bSXiong Zhang goto out_clean_opregion;
3594dff110bSXiong Zhang
360ad1d3636SZhi Wang ret = intel_vgpu_setup_submission(vgpu);
3618453d674SZhi Wang if (ret)
3628453d674SZhi Wang goto out_clean_display;
3638453d674SZhi Wang
3644b63960eSZhi Wang ret = intel_vgpu_init_sched_policy(vgpu);
3654b63960eSZhi Wang if (ret)
366ad1d3636SZhi Wang goto out_clean_submission;
3674b63960eSZhi Wang
368f8871ec8SGreg Kroah-Hartman intel_gvt_debugfs_add_vgpu(vgpu);
369bc7b0be3SChangbin Du
370f9399b0eSChristoph Hellwig ret = intel_gvt_set_opregion(vgpu);
371b851adeaSTina Zhang if (ret)
372b851adeaSTina Zhang goto out_clean_sched_policy;
373b851adeaSTina Zhang
3744ceb06e7SColin Xu if (IS_BROADWELL(dev_priv) || IS_BROXTON(dev_priv))
375f9399b0eSChristoph Hellwig ret = intel_gvt_set_edid(vgpu, PORT_B);
3764ceb06e7SColin Xu else
377f9399b0eSChristoph Hellwig ret = intel_gvt_set_edid(vgpu, PORT_D);
37839c68e87SHang Yuan if (ret)
37939c68e87SHang Yuan goto out_clean_sched_policy;
38039c68e87SHang Yuan
3811aa3834fSChristoph Hellwig intel_gvt_update_reg_whitelist(vgpu);
3821aa3834fSChristoph Hellwig mutex_unlock(&gvt->lock);
383a5ddd2a9SKevin Tian return 0;
38482d375d1SZhi Wang
385bc7b0be3SChangbin Du out_clean_sched_policy:
386bc7b0be3SChangbin Du intel_vgpu_clean_sched_policy(vgpu);
387ad1d3636SZhi Wang out_clean_submission:
388874b6a91SZhi Wang intel_vgpu_clean_submission(vgpu);
3898453d674SZhi Wang out_clean_display:
3908453d674SZhi Wang intel_vgpu_clean_display(vgpu);
3914dff110bSXiong Zhang out_clean_opregion:
3924dff110bSXiong Zhang intel_vgpu_clean_opregion(vgpu);
3934d60c5fdSZhi Wang out_clean_gtt:
3944d60c5fdSZhi Wang intel_vgpu_clean_gtt(vgpu);
39582d375d1SZhi Wang out_clean_vgpu_resource:
39682d375d1SZhi Wang intel_vgpu_free_resource(vgpu);
39782d375d1SZhi Wang out_clean_vgpu_mmio:
398cdcc4347SChangbin Du intel_vgpu_clean_mmio(vgpu);
3994e537891SJike Song out_clean_idr:
4004e537891SJike Song idr_remove(&gvt->vgpu_idr, vgpu->id);
4011aa3834fSChristoph Hellwig out_unlock:
402f25a49abSColin Xu mutex_unlock(&gvt->lock);
403a5ddd2a9SKevin Tian return ret;
4041f31c829SZhenyu Wang }
4059ec1e66bSJike Song
4069ec1e66bSJike Song /**
407cfe65f40SChangbin Du * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
408cfe65f40SChangbin Du * @vgpu: virtual GPU
409cfe65f40SChangbin Du * @dmlr: vGPU Device Model Level Reset or GT Reset
410cfe65f40SChangbin Du * @engine_mask: engines to reset for GT reset
411cfe65f40SChangbin Du *
412cfe65f40SChangbin Du * This function is called when user wants to reset a virtual GPU through
413f25a49abSColin Xu * device model reset or GT reset. The caller should hold the vgpu lock.
414cfe65f40SChangbin Du *
415cfe65f40SChangbin Du * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
416cfe65f40SChangbin Du * the whole vGPU to default state as when it is created. This vGPU function
417cfe65f40SChangbin Du * is required both for functionary and security concerns.The ultimate goal
418cfe65f40SChangbin Du * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
419cfe65f40SChangbin Du * assign a vGPU to a virtual machine we must isse such reset first.
420cfe65f40SChangbin Du *
421cfe65f40SChangbin Du * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
422cfe65f40SChangbin Du * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
423cfe65f40SChangbin Du * Unlike the FLR, GT reset only reset particular resource of a vGPU per
424cfe65f40SChangbin Du * the reset request. Guest driver can issue a GT reset by programming the
425cfe65f40SChangbin Du * virtual GDRST register to reset specific virtual GPU engine or all
426cfe65f40SChangbin Du * engines.
427cfe65f40SChangbin Du *
428cfe65f40SChangbin Du * The parameter dev_level is to identify if we will do DMLR or GT reset.
429cfe65f40SChangbin Du * The parameter engine_mask is to specific the engines that need to be
430cfe65f40SChangbin Du * resetted. If value ALL_ENGINES is given for engine_mask, it means
431cfe65f40SChangbin Du * the caller requests a full GT reset that we will reset all virtual
432cfe65f40SChangbin Du * GPU engines. For FLR, engine_mask is ignored.
433cfe65f40SChangbin Du */
intel_gvt_reset_vgpu_locked(struct intel_vgpu * vgpu,bool dmlr,intel_engine_mask_t engine_mask)434cfe65f40SChangbin Du void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
4353a891a62SChris Wilson intel_engine_mask_t engine_mask)
436cfe65f40SChangbin Du {
437cfe65f40SChangbin Du struct intel_gvt *gvt = vgpu->gvt;
438cfe65f40SChangbin Du struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
4393a891a62SChris Wilson intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
440cfe65f40SChangbin Du
441cfe65f40SChangbin Du gvt_dbg_core("------------------------------------------\n");
442cfe65f40SChangbin Du gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
443cfe65f40SChangbin Du vgpu->id, dmlr, engine_mask);
4446184cc8dSChuanxiao Dong
4456184cc8dSChuanxiao Dong vgpu->resetting_eng = resetting_eng;
446cfe65f40SChangbin Du
447cfe65f40SChangbin Du intel_vgpu_stop_schedule(vgpu);
448cfe65f40SChangbin Du /*
449cfe65f40SChangbin Du * The current_vgpu will set to NULL after stopping the
450cfe65f40SChangbin Du * scheduler when the reset is triggered by current vgpu.
451cfe65f40SChangbin Du */
452cfe65f40SChangbin Du if (scheduler->current_vgpu == NULL) {
453f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock);
454cfe65f40SChangbin Du intel_gvt_wait_vgpu_idle(vgpu);
455f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock);
456cfe65f40SChangbin Du }
457cfe65f40SChangbin Du
45806bb372fSZhi Wang intel_vgpu_reset_submission(vgpu, resetting_eng);
459cfe65f40SChangbin Du /* full GPU reset or device model level reset */
460cfe65f40SChangbin Du if (engine_mask == ALL_ENGINES || dmlr) {
4617569a06dSWeinan Li intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
462ba25d977SColin Xu if (engine_mask == ALL_ENGINES)
463730c8eadSZhi Wang intel_vgpu_invalidate_ppgtt(vgpu);
464615c16a9Sfred gao /*fence will not be reset during virtual reset */
4654d3e67bbSChuanxiao Dong if (dmlr) {
466ba25d977SColin Xu if(!vgpu->d3_entered) {
467ba25d977SColin Xu intel_vgpu_invalidate_ppgtt(vgpu);
468ba25d977SColin Xu intel_vgpu_destroy_all_ppgtt_mm(vgpu);
469ba25d977SColin Xu }
470ba25d977SColin Xu intel_vgpu_reset_ggtt(vgpu, true);
471cfe65f40SChangbin Du intel_vgpu_reset_resource(vgpu);
4724d3e67bbSChuanxiao Dong }
473615c16a9Sfred gao
474615c16a9Sfred gao intel_vgpu_reset_mmio(vgpu, dmlr);
475cfe65f40SChangbin Du populate_pvinfo_page(vgpu);
476cfe65f40SChangbin Du
477fd64be63SMin He if (dmlr) {
4783eb55e6fSTina Zhang intel_vgpu_reset_display(vgpu);
479cfe65f40SChangbin Du intel_vgpu_reset_cfg_space(vgpu);
480fd64be63SMin He /* only reset the failsafe mode when dmlr reset */
481fd64be63SMin He vgpu->failsafe = false;
482ba25d977SColin Xu /*
483ba25d977SColin Xu * PCI_D0 is set before dmlr, so reset d3_entered here
484ba25d977SColin Xu * after done using.
485ba25d977SColin Xu */
486ba25d977SColin Xu if(vgpu->d3_entered)
487ba25d977SColin Xu vgpu->d3_entered = false;
4889e7c0efaSColin Xu else
4899e7c0efaSColin Xu vgpu->pv_notified = false;
490fd64be63SMin He }
491cfe65f40SChangbin Du }
492cfe65f40SChangbin Du
4936184cc8dSChuanxiao Dong vgpu->resetting_eng = 0;
494cfe65f40SChangbin Du gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
495cfe65f40SChangbin Du gvt_dbg_core("------------------------------------------\n");
496cfe65f40SChangbin Du }
497cfe65f40SChangbin Du
498cfe65f40SChangbin Du /**
499cfe65f40SChangbin Du * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
5009ec1e66bSJike Song * @vgpu: virtual GPU
5019ec1e66bSJike Song *
5029ec1e66bSJike Song * This function is called when user wants to reset a virtual GPU.
5039ec1e66bSJike Song *
5049ec1e66bSJike Song */
intel_gvt_reset_vgpu(struct intel_vgpu * vgpu)5059ec1e66bSJike Song void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
5069ec1e66bSJike Song {
507f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock);
508cfe65f40SChangbin Du intel_gvt_reset_vgpu_locked(vgpu, true, 0);
509f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock);
5109ec1e66bSJike Song }
511